JPH0515049Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bar display device that can display numerical values in an analog manner by lighting up an appropriate number of adjacent bar display elements.

[Prior Art] Today, bar display devices that display various measured values in analog form, such as temperature display, speed display, and noise decibel display, are often used.

In this bar display device, a large number of display elements are arranged adjacent to each other in a strip shape, and when the display elements are arranged horizontally, an appropriate number of the display elements are lit in a continuous state starting from the left end, for example, and the display elements are If they are arranged vertically, for example, the required number of display elements are lit in succession from the bottom, so that the magnitude of the measured value corresponds to the number of lit display elements, thereby displaying the measured value in an analog manner. (For example, JP-A-60-123727
No.).

[Problems to be solved by the invention] As mentioned above, in a bar display device in which the number of lit display elements simply corresponds to the magnitude of the measured value, when the range of change in the measured value is wide, an extremely large number of display elements are used. , the bar display device becomes larger,
Furthermore, there is a drawback that the manufacturing cost becomes high.

[Means for solving the problem] The present invention includes a sensor circuit that outputs a detection signal corresponding to a measured value, and a sensor circuit that digitally processes the detection signal to generate first digit signals A0 to A9, which are the ones digit, and the tens digit. An arithmetic processing circuit that outputs the second digit signals B1 to B9 and an appropriate number of display elements are arranged, and the necessary number of display elements is arranged based on the first digit signals A0 to A9 and the second digit signals B1 to B9. In a bar display device having a bar display section that lights up a display element, the first digit signal A0
A 1st place display circuit that outputs 1st place signals C1 to C10, which are parallel signals in which a number of valid signals corresponding to the numerical value of ~A9 and a signal one higher than the valid signals are intermittent signals; and the second digit signal. A display in which the first signal C1 to C10 is added to the top of the 10th signal, which is a parallel signal with a non-lighting signal added to the top of each valid signal, which is a number of valid signals corresponding to the numerical values of B1 to B9. signal S1
A display signal circuit for outputting signals S28 to S28 to the bar display section is provided, and the bar display section lights up display elements corresponding to valid signals in the display signals S1 to S28.

[Operation] The bar display device according to the present invention has a second digit signal B1.
It has a display signal circuit that can convert ~B9 into a 10th place signal, and the display signal S1 that is output from the display signal circuit ~
The 10th place signal representing the 10th place value in S28 is
A required number of parallel signals can be obtained by combining one valid signal and one non-lighting signal.

Then, the 1st digit signal A0 ~
A9 is converted to the 1st signal, which is a parallel signal with valid signals adjacent to each other, and the display signal circuit
The 10th signal and the 1st signal are output in parallel as S1 to S28, and while the 10th signal and the 1st signal are distinguished, the numerical value 10 is divided into one valid signal and one non-lit signal. This is expressed by a 10th place signal which is a combination with a signal, and 10 numerical values are displayed using two display elements as a set. Therefore, in the bar display section which lights up the display elements corresponding to the valid signals of the display signals S1 to S28. The number of display elements can be reduced.

[Embodiment] As shown in FIG. 1, an embodiment of the present invention has a sensor circuit 12 comprising a detection section 14 such as a temperature sensor and an amplifier 16 that appropriately amplifies the output signal from the detection section 14. The detection signal outputted from the sensor circuit 12 is converted into a digital signal and subjected to arithmetic processing, and the first digit signal A0~ is used to represent the numerical value in the ones place.
A9 and the second digit signal B1 to B9 representing the tens digit value
, an arithmetic processing circuit 18 that outputs the first digit signals A0 to A9, and a 1st digit display circuit 42 that outputs the 1st digit signals C1 to C10, and Display signals S1 to S28 after receiving signals B1 to B9
a display signal circuit 44 that outputs the display signals S1 to S28 from the display signal circuit 44;
Display element 5 corresponding to valid signals in S1 to S28
It is composed of a bar display section 48 that lights up 0.

The arithmetic processing circuit 18 includes a voltage frequency converter 20 for receiving a detection signal from the sensor circuit 12 and converting the detection signal, which is an analog signal, into a pulse signal, and a voltage frequency converter 20 for converting the detection signal, which is an analog signal, into a pulse signal. A frequency divider 22 that divides the frequency into appropriate frequencies;
A first pulse counter 24 and a second pulse counter 2 that count pulse signals from the frequency divider 22.
6, and further generates a reference signal.
8, a frequency divider 30 that divides the frequency of the reference signal, and the first pulse counter 2 based on the frequency-divided reference signal.
4 and a second pulse counter 26, and a timing signal generation circuit 32 that outputs timing signals to a first latch circuit 34 and a second latch circuit 36, which will be described later.
a first latch circuit 34 that latches the count value of the first pulse counter 24; a second latch circuit 36 that latches the count value of the second pulse counter 26; The count value of 1st digit signal A0~A9
The first line decoder 38 and the second line decoder 38 output as
Second pulse counter 26 via latch circuit 36
and a second line decoder 40 that outputs the count value of as second digit signals B1 to B9.

The first pulse counter 24 and the second pulse counter 26 are decimal counters, and the pulse signal from the voltage frequency converter 20 via the frequency divider 22 is input to the φ input terminal of the first pulse counter 24,
The carry signal of the first pulse counter 24 is input to the φ input terminal of the second pulse counter 36, and the first pulse counter 24 and the second pulse counter 26 are reset at regular intervals by the timing signal from the timing signal generation circuit 32. do as you like.

Moreover, the first latch circuit 34 and the second latch circuit 3
Reference numeral 6 indicates a first pulse counter 24 or a second pulse counter 2 at regular intervals based on the timing signal.
6 is read and sent to the first line decoder 38 or the second line decoder 40, and the first line decoder 38 reads the count value sent from the first latch circuit 34 as shown in FIG. When the count value is 0, only the A0 signal is used as an H level valid signal, when the count value is 1, the A1 signal is used as a H level valid signal, and when the count value is 2, A1
and A2 signal as an effective signal of H level,
The second line decoder 40 outputs the first digit signals A0 to A9 whose valid signals are the number according to the count value sequentially from the lower order. Similarly to the first line decoder 38, the second line decoder 40 also outputs the signals from the second latch circuit 36. When the count value is 1, only the B1 signal is used as an H-level valid signal, when it is 2, B1 and B2 signals are used as H-level valid signals, and when it is 3, B1, B2, and B3 signals are used as H-level valid signals. The second digit signals B1 to B9 are sequentially output from the lower order as shown in FIG.

The 1st place display circuit 42 is composed of 10 AND circuits and 9 OR circuits as shown in FIG. oscillator 28 via a frequency divider 30 to the other input terminal of each AND circuit.
Connect each other input terminal of the AND circuit to the frequency divider 30 so as to input the φ ₁ reference signal from the AND circuit, and
The output terminal of each AND circuit is connected to the input terminal of each OR circuit, and each signal line of the A1 to A9 signals in the first digit signals A0 to A9 is also connected to the input terminal of each OR circuit.

Therefore, the first
When the A0 signal representing 0 in the digit signals A0 to A9 is used as a valid signal at H level, the AND circuit to which the A0 signal is input is opened, and the _φ1 reference signal passed through the AND circuit to which the A0 signal is input is is output to the C1 signal terminal via the OR circuit, and an intermittent signal based on the φ ₁ reference signal is output to the C1 signal, and
The first digit signal A0 to A9 is A1 to represent 3, for example.
When using the A3 to A3 signals as valid signals, each valid signal passes through the OR circuit to the first signal C1 to C10.
A valid signal at H level is output to the C1 to C3 signals, and the _φ1 reference signal that passes through the AND circuit opened by the A3 signal becomes an intermittent signal and is output as the C4 signal.

That is, the 1st digit display circuit 42 outputs the 1st digit signals A0 to A9.
Effective signals similar to the numerical value are outputted adjacently from the lowest order, and an intermittent signal is output from the terminal next to the terminal from which the effective signal is output, and the number of adjacent effective signals corresponding to the numerical value and one It outputs first-order signals C1 to C10 as parallel signals composed of intermittent signals.

In addition, the display signal circuit 44 has 1 as shown in FIG.
Nine shift circuits 46 each having 1 control input terminal, 10 main input terminals, 10 auxiliary input terminals, and 12 output terminals are used. Connect each main input terminal to each output terminal of the previous stage by shifting two output terminals with respect to the output terminal of the previous stage shift circuit 46, such that the No. 12 output terminal is connected to the main input terminal of the next stage shift circuit 46. The first-order signals C1 to C1 are connected to each of the auxiliary input terminals of each of the nine shift circuits 46 and the main input terminal of the first-stage shift circuit 46.
Each output terminal of the first place display circuit 42 is connected to each auxiliary input terminal of each shift circuit 46 and the main input terminal of the first stage shift circuit 46, such as inputting C10, and the control input terminal of each stage shift circuit 46 is connected. Each shift circuit 46 is connected to each output terminal of the second line decoder 40 in the arithmetic processing circuit 18 so that the second digit signals B1 to B9 are respectively input to the terminals,
In addition, each of the first output terminals and second output terminals in the first to eighth stage shift circuits 46 and all output terminals in the ninth stage shift circuit 46 are used as output terminals of the display signal circuit 44. It is something. This shift circuit 46 is constructed by combining an AND circuit and an OR circuit as shown in FIG.
is connected to the 3rd output terminal d3 to the 12th output terminal d12 in the shift circuit 46 at the previous stage, and when the B signal at L level is input to the control input terminal, the 1st main input in the shift circuit 46 The signals of each main input terminal D1 to D10 are outputted to the first output terminal d1, so that the signal of the terminal D1 is outputted to the first output terminal d1, and the signal of the second main input terminal D2 is outputted to the second output terminal d2. to No. 10 output terminal d10, and when a valid signal at H level is input as a B signal to the control input terminal, the No. 1 output terminal d1 is set to H level, and the second output terminal d2 is set to L level. At the same time, each signal of the ten auxiliary input terminals is outputted to the third output terminal d3 to the twelfth output terminal d12.

In this display signal circuit 44, seven of the C1 to C10 signals, C1 to C7, are valid signals as signals representing the numerical value 57, and an intermittent signal is output to the C8 signal. Signals C1 to C10 and
When a signal in which the B1 signal to B5 signal of the second digit signals B1 to B9 is set as an H level valid signal is input, the first to fifth stage shift circuits are activated as shown in FIG. 46 sets the first output terminal to H level,
And, while setting the second output terminal to L level,
The A1 signal to A7 signal will be output to the 3rd output terminal to the 9th output terminal, and the C8 signal will be output to the 10th output terminal, and the shift circuits 46 in the 6th to 9th stages will be Since the input to each control input terminal is at L level, the signal from the main input terminal is output to each output terminal, and the display signals S1 to S28 are S1.
A valid signal at H level and a non-lighting signal at L level are output alternately from signals to S10, and a valid signal at H level is output from signals S11 to S17, and an intermittent signal is output from signal S18. will be done.

Therefore, the display element 50 in the bar display section 48
As shown in FIG. 7, every other five display elements 50 from the left end are lit, seven display elements 50 from the 11th are lit continuously, and the 18th display element 50 is lit. It will blink.

As mentioned above, the display signal circuit 44 receives the second digit signal B.
The valid signal and the non-lighting signal are made into a set so that the non-lighting signal is inserted above each valid signal in 1 to B9, and the 10th place signal of the parallel signal is the number of sets according to the numerical value in the 10th place; 1 from the 1st place display circuit 42 above the 10th place signal based on the valid signal and the non-lighting signal.
By adding the adjacent valid signals and intermittent signals in the position signals C1 to C10, it is possible to output display signals S1 to S28 consisting of the 10th position signal and the 1st position signal. 10 representing the numerical value in the digit place
As a position signal, a valid signal and a non-lighting signal are combined, and a number of valid signals corresponding to the numerical value in the tens place are outputted every other place, thereby lighting up every other display element 50. , and since the valid signals are outputted adjacently as the first-place signals C1 to C10 of the ones digit, if the one digit is a value of 2 or more, the adjacent display elements 50 will light up continuously, You can tell the numerical value by distinguishing between the 10's digit and the 1's digit.

Also, if the value of the 1 digit is 0 or 1, it is a 1 in which an intermittent signal is combined in the upper part adjacent to the valid signal.
The position signals C1 to C10 are arranged above the 10th position signal by the display signal circuit 44, and the 10th position signal is a combination of a valid signal and a non-lighting signal, so for example, the numerical value 31 is as shown in FIG. 8A. , the first one located on the left side
In addition to the 3rd, 5th, and 7th display elements 50 lighting up, the 8th display element 50 adjacent to the 7th display element 50 blinks, and the blinking display The lighting of the fourth display element 50 adjacent to the element 50, that is, the seventh display element 50, indicates that the 1's digit is displayed, and the lighting of the display element 50 due to the 10th digit signal indicates that the number of display elements 50 is 3. 30, 4
The 1st lighting can represent the numerical value 1 in the 1s digit, and as shown in Figure 8B, the 1st, 3rd,
When the 5th and 7th display elements 50 light up and the 9th display element 50 blinks, the 1's digit is turned off due to the non-lighting of the 6th display element 50 adjacent to the blinking display element 50. 0, it is possible to confirm that the numerical value is 40, and even if every other display element 50 is lit, it can be distinguished by the relationship with the display element 50 that blinks.

In the above embodiment, the shift circuit 46 has ten main input terminals and ten auxiliary input terminals, but the other shift circuits 46 have one control input terminal and one control input terminal. , has only 10 input terminals and 12 output terminals, and has L on the control input terminal.
When a level signal is input, the signal of each input terminal is output to the 1st output terminal to the 10th output terminal,
When an H level signal is input to the control input terminal, the first
A shift circuit is used to set the No. 1 output terminal to H level, the No. 2 output terminal to L level, and output the signals of each input terminal to the No. 3 output terminal to the No. 12 output terminal, and the shift circuit in the previous stage The display signal circuit 44 is constructed by connecting the third to twelfth output terminals in the shift circuit 46 to each of the ten input terminals in the shift circuit 46 in the next stage. Input the 1st signal C1 to C10 to the terminal,
Further, it is also possible to configure the second digit signals B1 to B9 to be input to the control input terminals of each shift circuit 46.

[Effects of the invention] The bar display device according to the invention uses a display signal circuit to combine a number of valid signals and a non-lighting signal according to the numeric value as a 10th-place signal, thereby lighting every other display element. The display signals S1 to S28 are displayed as display signals S1 to S28, and the first digit display circuit 42 converts the first digit signals A0 to A9 of the ones digit into first digit signals consisting of a number of adjacent valid signals and an intermittent signal corresponding to the numerical value. signal
C1 to C10, and the display signals S1 to C10 are added in parallel to the upper part of the 10th signal, which is a combination of the non-lighting signal and the valid signal, by the display signal circuit.
Since the feed display element is lit in the bar display section 48 as S28, the tens digit and the ones digit are clearly distinguished.
In addition, the numerical value 1 in the second digit signals B1 to B9, that is, the measured value 10, can be represented with two display elements, whereas conventionally 99 elements were required to display the numerical value 1 to 99. A bar display device that allows display elements to be displayed using one-third or less of the number of display elements, which can easily downsize the bar display device, and which can be manufactured at low cost. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the circuit of a bar display device according to the present invention, FIG. 2 is a diagram showing an example of the output of a line decoder, FIG. 3 is a diagram showing an example of the first place display circuit, and FIG. is a diagram showing an example of a display signal circuit,
FIG. 5 is a diagram showing a circuit example of a shift circuit in a display signal circuit, FIG. 6 is a diagram showing an operation example of the display signal circuit, and FIGS. 7 and 8 are diagrams showing examples of lighting of display elements. 12...Sensor circuit, 18...Arithmetic processing circuit, 42...1st place display circuit, 44...Display signal circuit, 48...Bar display section.

Claims (1)

[Claims for Utility Model Registration] A sensor circuit that outputs a detection signal according to a measured value, and a sensor circuit that digitizes and performs arithmetic processing on the detection signal, thereby generating a first digit signal A0~ of the ones place based on the detection signal. A9
an arithmetic processing circuit that outputs second digit signals B1 to B9 of the tens digit; and an arithmetic processing circuit that receives the first digit signals A0 to A9 and outputs a number of valid signals according to the numerical value of the first digit signals A0 to A9. a 1st place display circuit that adds an intermittent signal to the upper 1st signal of the above, thereby outputting 1st place signals C1 to C10 as parallel signals consisting of a required number of valid signals and an intermittent signal, and the second digit signals B1 to B9 and 1st place signals C1 to C10 are input, and a non-lighting signal is inserted in the upper part of each valid signal of the number corresponding to the numerical value of 2nd digit signals B1 to B9. Add a signal and use
A display signal circuit that outputs display signals S1 to S28 as parallel signals consisting of a 10th-rank signal and a 1st-rank signal, and a required number of display elements arranged adjacent to each other, and each of the display signals S1 to S28 A bar display device comprising: a bar display section that lights up a display signal corresponding to a valid signal;