JPH0516536Y2 - - Google Patents
Info
- Publication number
- JPH0516536Y2 JPH0516536Y2 JP1983048397U JP4839783U JPH0516536Y2 JP H0516536 Y2 JPH0516536 Y2 JP H0516536Y2 JP 1983048397 U JP1983048397 U JP 1983048397U JP 4839783 U JP4839783 U JP 4839783U JP H0516536 Y2 JPH0516536 Y2 JP H0516536Y2
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- circuit
- signals
- circuit board
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案は、自己検査機能付プリント基板に関す
る。[Detailed description of the invention] (a) Industrial application field The present invention relates to a printed circuit board with a self-testing function.
(ロ) 従来技術
マイクロコンピユータを構成する各種回路ユニ
ツトのうち、CPUからの信号を得て作動する回
路ユニツトの調整や、動作確認テストのために
は、当然のことながらその回路とCPUとの間に
回路接続がなされていなければならない。従つ
て、当該回路ユニツトがCPUとは別の、独立し
た回路基板に構成され、この回路部分だけをコン
ピユータ本体より分離して、テスト、調整を行い
たいような場合には、CPUからの信号導入用の
リードを特別に用意する必要がある。また、
CPU自体も不良作動状態にあつて、しかもその
関連回路のテスト、調整を要する場合には、先
づ、CPUの「修理」を先行させなければならず、
上記関連回路のテストや調整の先行ないし同時進
行は不可能である。(b) Prior art Of the various circuit units that make up a microcomputer, it is natural that the circuit units that operate upon receiving signals from the CPU must be adjusted and tested to confirm their operation. Circuit connections must be made. Therefore, if the circuit unit in question is configured on an independent circuit board separate from the CPU and you want to separate this circuit part from the computer main body for testing and adjustment, it is necessary to use a circuit board for introducing signals from the CPU. It is necessary to prepare a special lead. Also,
If the CPU itself is in a malfunctioning state and its related circuits require testing and adjustment, the CPU must be "repaired" first.
It is not possible to test or adjust the related circuits in advance or simultaneously.
(ハ) 目的
従つて本考案の目的は、上記のような従来技術
に伴う不便ないし欠点を排除し、回路基板自体が
擬似CPU信号発生機能を備え、この回路基板上
に構成される回路の調整およびテストが、CPU
回路と独立に行われることを可能ならしめる、自
己検査機能付プリント基板の提供にある。(c) Purpose Therefore, the purpose of the present invention is to eliminate the inconveniences and shortcomings associated with the conventional technology as described above, to provide a circuit board itself with a pseudo CPU signal generation function, and to adjust the circuit configured on this circuit board. and the test is CPU
The purpose of the present invention is to provide a printed circuit board with a self-inspection function that enables the self-inspection to be performed independently of the circuit.
(ニ) 構成
上記の目的を達成するため、本考案によるプリ
ント基板には、CPUからの信号を導入する個々
の入力回路と所定の定電位ラインとの間を開閉す
るスイツチが、上記入力回路毎に設けられている
ことを特徴としている。(D) Configuration In order to achieve the above object, the printed circuit board according to the present invention is provided with a switch for opening and closing between each input circuit that introduces a signal from the CPU and a predetermined constant potential line for each input circuit. It is characterized by being provided in.
(ホ) 実施例
以下に本考案の実施例を図面に基づいて説明す
る。図面は本考案による自己検査機能付プリント
基板上に直流増幅器を構成して実施した場合の回
路図を示している。図において入力端子１および
２から別々に入力された２種類の入力信号はマル
チプレクサ（MPX）４を通じてその１つが選択
され、増幅回路５で増幅された後Ｄ−Ａ変換器６
の基準電圧端子に入力されている。Ｄ−Ａ変換器
６はマルチプライングＤ−Ａ変換器で、その各デ
ジタル信号入力端子は、プリント基板上の端子群
Ｊ２の各端子と１対１の対応接続を有し、端子群
Ｊ２にはCPUからの感度切換信号が入力される
ようになつている。また一方MPX４は、プリン
ト基板上の端子群Ｊ１を通じてCPUより送られ
てくる入力切換信号によつて制御され、入力端子
１および２から入力されてくる２種類の信号より
その１つを選択する。ところで、本考案による回
路基板には、CPUからの信号を受け入れる上記
端子群Ｊ１とＪ２のそれぞれに、各端子に係わる
ラインを独立に接地ラインに接続することのでき
るスイツチSW1およびSW2があらかじめ設けられ
ている。なお、上記端子群Ｊ１およびＪ２の各端
子ラインには抵抗を介して直流電源＋Ｖが印加さ
れている。以上の構成において通常の作動状態に
おいては上記両スイツチSW1とSW2の全回路は開
放状態にあり、端子群Ｊ１およびＪ２の各端子ラ
インの電位は、CPUの作動状態に従つて零と、
上記直流電源＋Ｖの電位との間に切り換えられ、
これらがCPUの信号となる。これらCPU信号の
うち、端子群Ｊ１の切換信号は増幅すべき上記２
種類の信号選択を制御し、端子群Ｊ２の信号は、
選択され増幅回路５で増幅された直流信号を「変
調」してＤ−Ａ変換器６の出力側より出力端子７
を経て出力する。(e) Examples Examples of the present invention will be described below based on the drawings. The drawing shows a circuit diagram of a DC amplifier constructed and implemented on a printed circuit board with a self-testing function according to the present invention. In the figure, one of two types of input signals inputted separately from input terminals 1 and 2 is selected through a multiplexer (MPX) 4, amplified by an amplifier circuit 5, and then sent to a D-A converter 6.
is input to the reference voltage terminal. The D-A converter 6 is a multiplying D-A converter, and each of its digital signal input terminals has a one-to-one correspondence connection with each terminal of the terminal group J2 on the printed circuit board. The sensitivity switching signal from the CPU is input. On the other hand, MPX4 is controlled by an input switching signal sent from the CPU through terminal group J1 on the printed circuit board, and selects one of two types of signals inputted from input terminals 1 and 2. By the way, on the circuit board according to the present invention, switches SW 1 and SW 2 are pre-installed in each of the terminal groups J1 and J2 that accept signals from the CPU, which can connect the lines related to each terminal to the ground line independently. It is provided. Note that a DC power supply +V is applied to each terminal line of the terminal groups J1 and J2 through a resistor. In the above configuration, in the normal operating state, all the circuits of the above-mentioned switches SW1 and SW2 are in an open state, and the potential of each terminal line of the terminal groups J1 and J2 becomes zero according to the operating state of the CPU.
Switched between the potential of the above DC power supply +V,
These become CPU signals. Among these CPU signals, the switching signal of terminal group J1 is the one mentioned above which should be amplified.
The type of signal selection is controlled, and the signal of terminal group J2 is
The DC signal selected and amplified by the amplifier circuit 5 is modulated and output from the output side of the D-A converter 6 to the output terminal 7.
Output via .
以上が本考案による回路基板上に構成された直
流増幅器の構成と、正常作動時の作用の説明であ
るが、本考案による回路基板によれば、上記直流
増幅回路テストや調整を行う場合には、次に説明
するように、端子群Ｊ１およびＪ２をCPUに接
続してその信号を得る必要がない。即ち、端子群
Ｊ１とＪ２をCPUから切り離した状態で、スイ
ツチSW1またはSW2の各開閉回路を閉じれば、そ
の回路に係わる端子回路の電位は零となり、ま
た、開閉回路を開ければ、直流電源＋Ｖの電位が
現われる。従つて、各開閉回路を開閉することに
より、端子群Ｊ１およびＪ２に属するいづれの端
子ラインにも、作動中のCPUよりの信号と同様
の「擬似CPU信号」を任意に発生することがで
き、この信号に基づき上記直流増幅回路の各段階
の増幅度の調整、あるいは作動状態のテスト等を
行うことができる。 The above is an explanation of the configuration of the DC amplifier configured on the circuit board according to the present invention and its operation during normal operation.According to the circuit board according to the present invention, when performing the above DC amplifier circuit test or adjustment, , as will be explained next, there is no need to connect the terminal groups J1 and J2 to the CPU to obtain its signals. That is, if you close each switching circuit of switch SW 1 or SW 2 with the terminal group J1 and J2 disconnected from the CPU, the potential of the terminal circuit related to that circuit becomes zero, and if you open the switching circuit, the DC A potential of power supply +V appears. Therefore, by opening and closing each switching circuit, a "pseudo CPU signal" similar to the signal from the operating CPU can be arbitrarily generated on any terminal line belonging to terminal groups J1 and J2. Based on this signal, it is possible to adjust the amplification degree of each stage of the DC amplifier circuit or test the operating state.
従つて、本考案による回路基板は、上記実施例
に限定されることなく、CPUの信号に直接係わ
りを有する他の回路、例えば、インタフエイスな
どの構成に使用した場合でも、CPUからの信号
なしに回路の調整やテストを独立に行うことがで
きるのは勿論である。 Therefore, the circuit board according to the present invention is not limited to the above-mentioned embodiments, and even when used in the configuration of other circuits that are directly related to CPU signals, such as an interface, there is no signal from the CPU. Of course, the circuit can be adjusted and tested independently.
(ヘ) 効果
以上の説明から明らかなように、本考案によれ
ば、構成された回路をCPUからの信号を受けず
に調整し、テストすることができる。(f) Effects As is clear from the above explanation, according to the present invention, the constructed circuit can be adjusted and tested without receiving any signals from the CPU.
図面は本考案実施例の回路構成を示す回路図で
ある。
Ｊ１，Ｊ２……CPUとの接続端子群、SW1，
SW2……スイツチ。
The drawing is a circuit diagram showing the circuit configuration of an embodiment of the present invention. J1, J2...Connection terminal group with CPU, SW 1 ,
SW 2 ...Switch.
Claims (1)
構成するためのプリント配線基板であつて、
CPUからの信号を導入する個々の入力回路と所
定の定電位ラインとの間を開閉するスイツチが、
上記入力回路毎に設けられでおり、これら複数の
スイツチの個々の開閉操作によつて当該プリント
配線基板に構成されろべき上記電子回路に疑似
CPU信号を入力することができるよう構成され
た、自己検査機能付プリント基板。 A printed wiring board for configuring an electronic circuit operated by signals from a CPU,
A switch that opens and closes between each input circuit that introduces a signal from the CPU and a predetermined constant potential line is
These switches are provided for each input circuit, and can simulate the electronic circuit that should be configured on the printed wiring board by opening and closing each of these multiple switches.
A printed circuit board with self-testing function configured to allow input of CPU signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4839783U JPS59154679U (en) | 1983-03-31 | 1983-03-31 | Printed circuit board with self-inspection function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4839783U JPS59154679U (en) | 1983-03-31 | 1983-03-31 | Printed circuit board with self-inspection function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59154679U JPS59154679U (en) | 1984-10-17 |
| JPH0516536Y2 true JPH0516536Y2 (en) | 1993-04-30 |
Family
ID=30178927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4839783U Granted JPS59154679U (en) | 1983-03-31 | 1983-03-31 | Printed circuit board with self-inspection function |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59154679U (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5213915B2 (en) * | 1972-02-14 | 1977-04-18 | ||
| JPS5423539U (en) * | 1977-07-20 | 1979-02-16 |
-
1983
- 1983-03-31 JP JP4839783U patent/JPS59154679U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59154679U (en) | 1984-10-17 |
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