JPH0518155B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing device having a graph display function, and more particularly to a graph display device that displays a graph with an abbreviated waveform.

[Prior art and its problems]

Generally, when creating various graphs on paper, wavy lines (abbreviated waveforms) as shown in Figure 1 are sometimes used to omit part of the scale due to paper size constraints or scaling considerations. .
However, in the past, in information processing equipment such as office computers, when displaying graphs on a CRT monitor, graphs were not displayed using wavy lines (abbreviated waveforms), which was inconvenient.

Therefore, it is conceivable to provide these information processing devices with a graph display function with wavy lines (abbreviated waveforms). A conceivable means for achieving this is to prepare a wavy line (abbreviated waveform) display pattern and directly overwrite the graph pattern. However, with this means, as shown in FIG. 2, the graph and the wavy lines (omitted waveforms) are displayed overlapping each other, making it difficult to see and unnatural.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a graph display device that has a simple configuration and yet displays graphs with wavy lines in an easy-to-read and natural state.

[Embodiments of the invention]

FIG. 3 shows a schematic configuration of an information processing device according to an embodiment of the present invention. In the figure, 10 is a disk file in which various data such as sales data is stored, and 20 is a classification/aggregation unit that classifies and aggregates the data stored in the disk file 10 and creates a data table. The data table created by the classification/aggregation section 20 is stored in another area of the disk file 10. 30 is an autoscaling control unit, and the disk file 1
Scaling is performed based on the maximum value, minimum value, etc. of the data in the data table stored in 0.
Therefore, the autoscaling control unit 30
An axis table is created and written into a graphics memory (not shown) in the graph drawing control section 40. Next, the autoscaling control section 30 creates a graph from the data table stored in the disk file 10, and writes it into the graphics memory within the graph drawing control section 40. In this way, the graph is overwritten on the x and y axis table. That is, a graph pattern is written into the graphic memory. The operations up to this point are performed using conventional techniques.

Next, the autoscaling control unit 30 outputs information specifying the abbreviated waveform display applicable area of the graph drawing control unit 40 to the graph drawing control unit 40 in order to write the abbreviated waveform to the graphic memory in the graph drawing control unit 40. At the same time, an activation signal is output to the abbreviated waveform drawing control section 50. As a result, the graph pattern in the abbreviated waveform display area of the graphic memory is read out in predetermined bit units and supplied to the abbreviated waveform drawing control section 50. This abbreviated waveform drawing control unit 50 has two functions related to abbreviated waveforms.
It has a function of generating seed patterns (a pattern applied to display erasure of the area within the waveform of the omitted waveform and a pattern applied to the display of the omitted waveform),
These two types of patterns are generated in predetermined bit units in response to a start signal from the autoscaling control section 30. Further, the abbreviated waveform drawing control section 50 has two types of logical addition functions (AND addition and OR addition). The abbreviated waveform drawing control unit 50 then AND-adds the display erasing pattern with the graph pattern in the abbreviated waveform display corresponding area in predetermined bit units, thereby creating a graph in which each bit corresponding to the abbreviated waveform area is turned OFF. Get the pattern. Next, the abbreviated waveform drawing control section 50 performs OR addition of the thus obtained graph pattern and the display pattern in predetermined bit units to obtain a graph pattern with an abbreviated waveform. This graph pattern with the abbreviated waveform is written in the original area of the graphics memory in the graph drawing control section 40 in units of predetermined bits. Using the contents of this graphic memory
By displaying the screen on the CRT monitor 60,
Graphs with abbreviated waveforms are displayed in a natural state.

The outline of one embodiment of the present invention has been described above. Next, one embodiment of the present invention will be described in detail with reference to FIGS. 4 to 8. FIG. 4 mainly shows the main configurations of the graph drawing control section 40 and the abbreviated waveform drawing control section 50. In the same figure, 3
1 is an address control signal generating section. The address control signal generation section 31 is an autoscaling control section 3.
0, and outputs an address to the graph drawing control section 40 and an activation signal to the abbreviated waveform drawing control section 50 when creating a graph pattern with an abbreviated waveform. Graph drawing control unit 40
has a graphics memory 41 in which graph patterns are stored, an address control device 42 that generates addresses for the graphics memory 41, and a graphics control device 43 that performs read/write control for the graphics memory 41. . The abbreviated waveform drawing control unit 50 also includes shift registers 51 and 52 that can be shifted left and right, a shift control device 53 that controls shifts of the shift registers 51 and 52 to the left and right, and a
A left end/right end detection device 54 detects that the ON bit exists at the left end or right end bit position and instructs the shift control device 53 to change the shift direction.
, an AND circuit 55 , and an OR circuit 56 .

In the initial state, the shift register (first shift register) 52 stores, for example, a 16-bit column pattern (first type (column pattern) is set as shown in FIG. 5a. In this example, the above
The 16-bit column pattern is the bit pattern data necessary to display the above-mentioned one-cycle waveform.
This is, for example, the first column pattern of the 16-bit OR pattern PTN1 (see the operation diagram in FIG. 7). On the other hand, in the initial state, the shift register (second shift register) 51 has a 16-bit column pattern (second type column pattern) necessary for display erasing the area within the column waveform of the predetermined column as shown in FIG. 6a. Set as shown. In this embodiment, the 16-bit column pattern (second type column pattern) is an AND pattern PTN2 (see FIG. This is the first row pattern of (see operation explanatory diagram). In this embodiment, in the 16-bit column pattern (second type column pattern), each bit corresponding to the area inside the column waveform is turned ON, and each bit corresponding to the area outside the column waveform is OFF.

When a graph pattern with an abbreviated waveform is required, the autoscaling control unit 30 stores information in the graphic memory 41 that corresponds to each one-cycle waveform display area constituting the abbreviated waveform display area determined by scaling. The start address of each area is sequentially generated from the address control signal generating section 31.
Further, the autoscaling control section 30 also generates a start signal from the address control signal generation section 31 when the above-mentioned first address is generated. This activation signal is guided to the shift control device 53 in the abbreviated waveform drawing control section 50. As a result, the shift control device 53 shifts the shift registers 52 and 51 to the right one bit at a time, for example, as shown in FIGS. 5 b to e and 6 b to e, at respective timings. Therefore, when the shift registers 52 and 51 undergo right shift operations four times from their initial states (see FIGS. 5a and 6a), one of the ON bits in the shift register 52 is shifted to the rightmost bit position. (Figure 5e). As a result, the left end/right end detection device 54 detects the right end position and instructs the shift control device 53 to change the shift direction. As a result, shift control device 53
(from the fifth shift operation) shifts the shift registers 52 and 51 to the left one bit at a time as shown in FIGS. 5 f-m and FIG. 6 f-m. Thus, when shift registers 52 and 51 undergo eight left shift operations, one of the ON bits in shift register 52 is shifted to the leftmost bit position (see FIG. 5m). As a result, the left end/right end detection device 54 detects the left end position, and the shift control device 5
3 to change the shift direction. As a result, the shift control device 53 (from the 13th shift operation) shifts the shift registers 52, 51 to
p, again shifted to the right one bit at a time as shown in FIG. 6n-p.

The contents of FIGS. 5 a to 5 p and FIGS. 6 a to 6 correspond to each column pattern from the first column of the OR pattern PTN1 and AND pattern PTN2 shown in the operation explanatory diagram of FIG. 7. This is OR pattern PTN1,
AND pattern PTN2 is the shift register 52,
This indicates that each column pattern of 51 to 16 bits is output in parallel at each timing. That is, according to this embodiment, 16 types can be created by simply preparing the column patterns of the first column in the OR pattern PTN1 and the AND pattern PTN2 (by shifting the one column pattern to the left or right). column pattern can be realized. As mentioned above, 16 types of column patterns can be obtained by 15 shift operations, but in this embodiment, 16 shift operations are performed to return the contents of the shift registers 51 and 52 to their initial states. It will be done.
The 16-bit column pattern output in parallel from the shift register 51 is guided to one input of an AND circuit 55. Further, the 16-bit column pattern output in parallel from the shift register 52 is guided to one input section of the OR circuit 56.

On the other hand, the start address generated from the address control signal generation section 31 (that is, the start address of a certain one-cycle waveform display area in the graphics memory 41) is guided to the address control device 42 in the graph drawing control section 40. The data is loaded into an address counter (not shown) of the address control device 42. As a result, the first address is supplied as an address to the graphics memory 41. The address control device 42 repeatedly increments an address counter at a predetermined timing, and stores an address string following the above-mentioned top address corresponding to the one-cycle waveform display area in the graphics memory 41 (specified by the autoscaling control section 30). are output one address at a time. As a result, the area corresponding to the designated one-cycle waveform display in the graphics memory 41 is designated by the address string starting from the above-mentioned top address. The graphics control device 43 is configured to first execute a read cycle and then execute a write cycle in response to one address output from the address control device 42. Now, considering only the read cycle as appropriate, the designation of the address output from the address control device 42 causes the graphics memory 4
1, the graph patterns within the area corresponding to the one-cycle waveform display are sequentially read out in units of 16-bit column patterns starting from the first column pattern. This indicates that the graph pattern GPTN1 within the area corresponding to the one-cycle waveform display is cut out from the graphic memory 41, as shown in the operation explanatory diagram of FIG.
The 16-bit column pattern read from graphics memory 41 is directed to the other input of AND circuit 55.

The AND circuit 55 is composed of 16 two-input AND gates (not shown), and the shift register 51
The level-inverted data of the 16-bit column pattern, which is the parallel output of the
Add AND. As a result, in the 16-bit column pattern read from the graphics memory 41, the bit group that overlaps with the area within the column waveform of the corresponding column is turned OFF. The output of AND circuit 55 (16-bit column pattern) is led to the other input of OR circuit 56.

The OR circuit 56 is composed of 16 2-input OR gates (not shown), and receives the 16-bit column pattern output from the AND circuit 55, the 16-bit column pattern output in parallel from the shift register 52, and the 16-bit column pattern output from the AND circuit 55 in parallel. OR add bitwise. This creates the desired row pattern.

At this point, the graphics control device 43 switches the cycle from the read cycle to the write cycle. As a result, the 16-bit column pattern output from the OR circuit 56 is stored in the graphic memory 4.
1 is written to the original address location.

The above operation is performed by one
By repeating the graph pattern GPTN1 stored in the periodic waveform display area per row pattern, as shown in the operation explanatory diagram of FIG. All OFF
A graph pattern GPTN2 is obtained as an intermediate result, and a graph pattern GPTN3 in which a one-period waveform (OR pattern PTN1) is superimposed on the graph pattern GPTN2 is obtained as a final result. This graph pattern GPTN3 is written in the area of the graphics memory 41 where the graph pattern GPTN1 was stored. That is,
Graph pattern in graphic memory 41
GPTN1 is rewritten to graph pattern GPTN3. Note that the shift timing of the shift registers 51 and 52 and the read timing of the graphic memory 41 are determined by ANDing the AND pattern PTN2 and the graph pattern GPTN1 in the AND circuit 55.
Addition is performed between column patterns in the same column, and OR
In the circuit 56, the timing is such that the OR addition of the OR pattern PTN1 and the graph pattern GPTN2 is performed for the column patterns of the same column.

As is clear, by performing the above-mentioned processing on all the one-cycle waveform display corresponding areas constituting the abbreviated waveform display applicable area in the graphic memory 41, the graph pattern with the abbreviated waveform is stored in the graphic memory 41. can do. By displaying the screen on the CRT monitor 60 using the graph pattern with the abbreviated waveform stored in the graphic memory 41, the graph with the abbreviated waveform is displayed in a natural and easy-to-see state as shown in FIG. .

In addition, in the embodiment, the left edge/right edge detection device 5
Although the shift register 52 is assumed to be the register to be detected in No. 4, the shift register 51 may be the register to be detected. Also, shift register 5
The column pattern initialized to 1,52 is AND
The column pattern is not limited to the first column of pattern PTN2 and OR pattern PTN1. However, AND
Pattern PTN2 and OR pattern PTN1 each need to be column patterns in the same column.

Further, in the above embodiment, the case of a graph in the vertical direction has been described, but the present invention can be similarly applied to a case of a graph in the horizontal direction. However, graphic memory 4
When reading/writing from 1, so-called vertical/horizontal conversion is required. Note that in the method of storing graph patterns in the graphics memory 41 in units of row patterns, the above conversion is necessary for vertical graphs.

Further, the present invention can also be applied to color graph display. However, in this case, the above-mentioned AND addition is
It is necessary to perform this for all R, G, and B graph patterns. On the other hand, OR addition needs to be performed only on AND addition results corresponding to display colors.

〔Effect of the invention〕

As described in detail above, according to the present invention, a graph with abbreviated waveforms (wavy lines) is displayed in an easy-to-read and natural state despite having a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a graph with an abbreviated waveform drawn on a paper, FIG. 2 is a diagram showing an example of a conventional screen display of a graph with an abbreviated waveform, and FIG. 3 is information related to an embodiment of the present invention. FIG. 4 is a block diagram showing the schematic configuration of the processing equipment. FIG. 4 is a block diagram mainly showing the configuration of the main parts of the graph drawing control section and the abbreviated waveform drawing control section shown in FIG. 3. FIG. 5 and FIG. FIG. 7 is a diagram illustrating changes in the contents of the shift register, FIG. 7 is an explanatory diagram of operations related to creating a graph with omitted waveforms, and FIG. 8 is a diagram showing an example of a screen display of a graph with omitted waveforms. 30...Auto scaling control section, 40...
Graph drawing control unit, 41...Graphic memory, 50...Abbreviated waveform drawing control unit, 51, 52...
...Shift register, 53...Shift control device, 5
4...Left end/right end detection device, 55...AND circuit,
56...OR circuit.

Claims (1)

[Claims] 1 means for storing graph pattern data, means for generating a periodic waveform of omitted waveform pattern data, means for generating a periodic waveform of erasing pattern data for erasing the omitted waveform area, and a period of the generated erasing pattern data. means for sequentially erasing the graph pattern data in the abbreviated waveform area based on the waveform; and sequentially superimposing the abbreviated waveforms of the generated abbreviated waveform pattern data on the abbreviated waveform area of the erased graph pattern data. 1. A graph display device comprising: writing means.