JPH0520008Y2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a high-efficiency, low-distortion power amplifier suitable for use in audio circuits and the like.

``Prior Art'' Amplifiers are required to be more efficient in order to reduce power consumption and the amount of heat generated by output stage circuits. In particular, reducing the amount of heat generated by high-output amplifiers has become a major issue for safety and other reasons.

Pulse width modulation (PWM) and similar methods are known as means for increasing the efficiency of amplifiers. For example, the circuit shown in Fig. 4A is a power amplifier that uses the PWM method, and the comparator 20 compares the input signal Vi and the carrier signal Ca, and the result is
Get PWM square wave. This rectangular wave is supplied to the bases of the transistors 22 and 23 via the drive circuit 21, so that a PWM signal as shown in FIG. 4B is output from the common collector of the transistors 22 and 23. When this output signal is smoothed by a low-pass filter, an analog signal corresponding to the input signal is obtained as shown in FIG.

By the way, the above-mentioned PWM method and similar methods are extremely superior in terms of efficiency, but because of the procedure of converting an analog signal into a pulse signal and then converting it back to an analog signal, distortion and noise are likely to occur. In addition, since a large amplitude pulse wave is used, high frequency noise such as unnecessary radiation is generated, and it is difficult to take countermeasures against this problem. Therefore, the reality is that it is not often used in audio equipment and the like.

Next, the circuit shown in FIG. 5 is an amplifier circuit of the power supply voltage switching type, which switches the drive power supply voltage of the output stage transistor in accordance with the amplitude of the input signal. That is, the input signal Vi is supplied to the bases of the transistors 26 and 27 via the analog amplifier 25, the input level is detected by the control circuit 28, and the switches Sa ₁ to _{Sa 3} are activated according to the detected input level. one of these and a switch
It operates to turn on any one of Sb ₁ to Sb ₃ .

According to the circuit shown in FIG. 5, one of the switches _Sa1 to _Sa3 and one of the switches _Sb1 to _Sb3 are appropriately turned on in accordance with the amplitude value of the input signal, whereby the transistors 2
The drive power supply voltages of 6 and 27 change in response to the input signal, which has the advantage of improving efficiency compared to a circuit in which the power supply voltage of the output stage transistor is fixed, and since the input signal is amplified as an analog signal, there is no disadvantage as in the circuit shown in FIG.

By the way, in the circuit shown in FIG. 5 described above, it is better to perform small voltage switching as shown in FIG. 6B for the signals input to the transistors 26 and 27, as shown in FIG. It is more efficient than switching in large increments. That is, if the step of voltage switching is large, the area of the shaded portion in the figure becomes large, and the loss increases accordingly. However, in order to perform small voltage switching as shown in Figure 5, it is necessary to use the switching power supply shown in Figure 5.
Va ₁ ~ _{Va 3} , Vb ₁ ~ Vb ₃ and switch Sa ₁ ~ _{Sa 3} ,
The number of Sb ₁ to Sb ₃ had to be increased, which caused a problem of complicating the configuration and increasing costs.

This idea was made in view of the above-mentioned circumstances, and it is possible to perform small power supply voltage switching without significantly increasing the number of switching power supplies, and to significantly reduce high-frequency interference such as unnecessary radiation. The purpose is to provide a power amplifier with high efficiency and low distortion.

"Means for solving the problem" In order to solve the above problem, this invention compares the absolute value of the analog input signal with a plurality of preset reference values, and based on the comparison results, a conversion circuit that converts the analog input signal into a binary digital code; a plurality of voltage sources provided in a number corresponding to each bit of the binary digital code, and whose voltage values are weighted in accordance with each bit; A digital power amplifier includes a switching circuit that connects in series the voltage sources designated by the binary digital code and outputs the voltage sources, and a digital power amplifier that amplifies the power of the analog input signal as an analog signal and supplies it to a load. and an analog power amplifier that uses the output of the digital power amplifier as an operating power source.

"Function" Every time the input signal crosses the reference value, the output voltage of the digital power amplifier increases or decreases little by little at intervals of the power supply voltage corresponding to the minimum bit code, and the analog power amplifier The minimum required operating power supply voltage is applied accurately.
Furthermore, when the input signal changes slowly (when the frequency is low), the interval between output voltage switching of the digital amplifier becomes long, and unnecessary radiation etc. are reduced as much as possible.

"Embodiments" Hereinafter, embodiments of this invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of this invention. In this figure, 1 is an analog amplifier, and an input signal applied to an input terminal 2 is supplied via a delay line DL. The delay line DL delays the input signal by a minute amount of time, and is composed of, for example, a low-pass filter. Note that the function of this delay line DL will be described later.

Next, Qa and Qb are power transistors,
The respective emitters are commonly connected via emitter resistors re, re, and a load ZL is interposed between the connection point of the emitter resistors re, re and the ground point. Ba and Bb are base bias sources connected in series, and the bias sources Ba and Bb supply base bias currents to transistors Qa and Qb, respectively. The output signal of the analog amplifier 1 described above is generated by the bias sources Ba,
It is designed to be supplied to the connection point of Bb. Also, the connection point of the emitter resistors re and re and the deviation detection point 4
An impedance element 3 is inserted between the two and the negative feedback is applied (the feedback rate is β). The above-mentioned components constitute an analog amplifier section A.AMP, and this analog amplifier section A.AMP amplifies the input signal supplied to the input terminal 2 as an analog signal, and the emitter resistors re and re. Output from the connection point.

Next, 5 is an absolute value detection circuit which full-wave rectifies the input signal, detects the absolute value (analog value) of the input signal, and supplies the detected absolute value to the level detection comparator 6 .
The level detection comparator 6 compares the level of the output signal of the absolute value detection circuit 5 with eight reference levels set at equal intervals in advance.
As the signal level of the absolute value detection circuit 5 increases, the outputs are sequentially set to "1" starting from the output corresponding to the minimum level. Therefore, when the output level of the absolute value detection circuit 5 is the maximum, all eight outputs of the level detection comparator become "1" signals, and when the output signal of the absolute value detection circuit 5 is smaller than the minimum reference level. In this case, all outputs of the level detection comparator 8 become "0" signals.

7 is an encoder (8LINE TO 3 BCD encoder) that decodes the states of the 8 output signals of the level detection comparator 6 into 3-bit digital signals, and the ²⁰ to ²² bit output signals are sent to photocouplers PC0 to PC2, respectively. It is designed to be supplied to the gates of switching field effect transistors SWA to SWC through the switch. According to the above configuration, when any bit of the encoder 7 becomes "1", the field effect transistors SWA to SWC corresponding to that bit are turned on, and as a result, the on/off states of the field effect transistors SWA to SWC are determined by the input. It corresponds to the binary level of the peak value of the signal.
In addition, in this example, the photocoupler PC0
~PC2 is used because encoder 7 is TTL
This is because the encoder 7
Output signal level of field effect transistor SWA
~This is to interface with the gate potential of SWC.

V ₀ , V ₁ , and V ₂ are voltage sources provided corresponding to each output bit of the encoder 7, and the voltage values are weighted according to the bits, that is, E, 2E, and 4E. It is becoming. The voltage sources V ₀ , V ₁ , and V ₂ mentioned above are each inserted between points a and b in the same direction (point b side is positive), and
Field effect transistors SWA, SWB and SWC are inserted between the point and the voltage source V ₀ , between the voltage source V ₀ and the voltage source V ₁ , and between the voltage sources V ₁ and V ₂ , respectively. . D ₀ , D ₁ , and D ₂ are switching diodes connected in series in the same direction between points a and b, and the anode of diode D ₀ is connected to point a,
Anodes of diodes D ₁ and D ₂ are connected to positive electrodes of voltage sources V ₀ and V ₁ , respectively.

Next, 8 shown in FIG. 1 is a comparator that determines the polarity of the input signal, and when the input signal is positive, it supplies an output signal e of "0" level to the switching field effect transistor swe, and inputs When the signal is negative, an output signal f of "1" level is supplied to the gate of the switching field effect transistor swf. In addition, Vf is a voltage source (value is E) for guaranteeing the lowest value of the voltage applied to the collector of the power transistor Qa, and Vr is the power transistor
A voltage source (value E) that guarantees the lowest value of the voltage applied to the collector of Qb, D ₄ , D ₅ , D ₇ ,
_D8 are switching diodes.
The digital amplifier section D.AMP is configured by each of the above components.

Next, the operation of this embodiment with the above-described configuration will be explained.

First, when an input signal is supplied, the encoder 7
outputs a binary digital signal corresponding to its absolute value, and as a result, the field effect transistor SWA~
The SWC is turned on or off in response to the binary digital signal. Then, when any of the field effect transistors SWA to SWC turns on,
The diodes D ₀ to D ₂ corresponding to that bit are reverse biased and turned off, and as a result, the voltage value of the voltage source for that bit is output between points a and b shown in FIG. Therefore, the voltage output between points a and b is the sum of the voltage values of the voltage sources of the bits where the field effect transistors SWA to SWC are turned on, that is, twice the absolute value of the input signal. The voltage corresponds to the evolution code.

Then, when the input signal is positive, the field effect transistor swe is turned on, and as a result, the point a-b
The sum of the voltage corresponding to the level of the input signal obtained during this period and the voltage of the voltage source Vf is supplied to the collector of the power transistor Qa via the diode _D5 . Further, in this case, the diodes D ₄ and D ₆ are in the off state, but the diode D ₇ is in the on state, so that the voltage −E of the voltage source Vr is applied to the collector of the power transistor Qb.

When the input signal is negative, the field effect transistor
swf is turned on, and as a result, the voltage corresponding to the input signal level obtained between points a and b and the voltage source Vr
is applied to the collector of power transistor Qb through diode _D6 in the negative direction. Also, in this case, diodes D ₅ and D ₇ are off, but diode D ₄ is on, so
A voltage E from a voltage source Vf is applied to the collector of the transistor Qa.

On the other hand, the analog amplifier section A.AMP performs the operation of amplifying the input signal as an analog signal, and the power transistor Qa, which is the final stage,
Power for Qb is supplied from the digital amplifier section D.AMP. In this case, the time required for the input signal to be analog amplified and output from the analog amplifier A.AMP is such that the digital amplifier section D.AMP transmits the voltage corresponding to the peak value of the input signal to the power transistor.
Since the time required to supply Qa and Qb is slightly shorter, the delay line DL is used to compensate for this time delay.

Next, FIG. 2 shows the relationship between the output signal of the analog amplifier section A.AMP and the output signal of the digital amplifier section D.AMP. SA and SD shown in Figure 2
show the output signal waveforms of the analog amplifier section A.AMP and the digital amplifier section D.AMP, respectively. As can be seen from this figure, the power supply for the power transistors Qa and Qb, which are the power stage, is from the digital amplifier.
D.AMP switches the value according to the input signal. And the loss in this case is from the waveform SD
Since this is the part after subtracting SA, it can be seen that extremely efficient analog amplification is being performed. Further, although the number of power supply switching stages by the digital amplifier D.AMP in this case is 8 stages (3 bits), only 3 voltage sources are required for switching, which simplifies the configuration.

Furthermore, when comparing periods T ₁ and T ₂ shown in the figure, it is found that the power supply switching cycle T is short in period T ₁ ;
It can be seen that T ₂ has become longer. That is,
When the frequency of the input signal is high, the power supply switching speed is fast, and when the frequency of the input signal is low, the power supply switching speed is slow. This means that when the frequency of the input signal is low, the input signal is detected by the level detection comparator 6.
This is because the time required to change the reference value by one step becomes longer, and the change in the output signal of the encoder 7 becomes slower. In this case, the power transistor
If the power supply for Qa and Qb is switched unnecessarily many times, the problem arises that high frequency interference such as unnecessary radiation is likely to occur.On the other hand, if the power supply is switched too late, the power supply voltage supplied to the power transistors Qa and Qb may be too low or too low. A situation in which there is too much occurs, causing problems such as generation of distortion and deterioration of efficiency. In this embodiment, as shown in FIG. 2, if the input signal changes quickly, the power supply switching speed increases accordingly, and if the input signal changes slowly, the power supply switching speed also increases automatically. Become slow. Therefore, in this embodiment, an appropriate power supply voltage can be supplied to the power transistors Qa and Qb according to the peak value of the input signal, and the power supply switching speed can be made as slow as possible. Therefore, without impairing the amplification characteristics,
This has the advantage of being able to reduce high frequency interference, etc.

Next, FIG. 3 is a circuit diagram showing a more detailed configuration example of the digital amplifier section D.AMP in the above embodiment. In this figure, the same reference numerals are given to the parts corresponding to those in FIG. 1, and the explanation thereof will be omitted.

10 shown in the figure is three resistors 10a, 10b,
10c (values R, R, 2R) and two diodes
This is an absolute value detection circuit consisting of Da and Db, and the first
This corresponds to the absolute value detection circuit 5 shown in the figure. Note that this absolute value detection circuit 10 detects 1/2 of the absolute value of the input signal.
Output the value of . Next, numeral 11 is a level comparison comparator consisting of eight comparators 11a to 11g, and numeral 12 is an octal-2 comparator such as TI's SN74148.
It is a forward BCD encoder, and 13a to 13c are drive circuits for field effect transistors SWA to SWC, respectively. Further, the comparator 15, the transistor buffer 16, etc. are circuits corresponding to the polarity detection circuit 8 shown in FIG.

"Effect of the invention" As explained above, according to this invention, the absolute value of the analog input signal is compared with a plurality of preset reference values, and based on the comparison results, the analog input signal is A conversion circuit for converting into an evolutionary digital code, a plurality of voltage sources provided in a number corresponding to each bit of the binary digital code, and whose voltage value is weighted in accordance with each bit, and a plurality of voltage sources among these voltage sources. a digital power amplifier having a switching circuit for serially connecting and outputting signals specified by the binary digital code; Since we are equipped with an analog power amplifier that uses the output of the power amplifier as an operating power supply, each time the input signal crosses the reference value, the output voltage of the digital power amplifier increases or decreases in small increments at intervals of the power supply voltage corresponding to the minimum bit code, and switches. An extremely efficient power amplifier can be provided without significantly increasing the number of power supplies. In addition, each weighted power source is combined in binary, so
The number of power supply voltage stages can be set as large as 2 ⁿ for the number n of power supplies, and the number of parts, space, and cost can be reduced. Furthermore, when the input signal changes slowly (when the frequency is low), the interval between switching the output voltage of the digital amplifier becomes longer, reducing unnecessary radiation as much as possible, and high frequency interference can be significantly reduced. Benefits can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of an embodiment of this invention, and Fig. 2 is a circuit diagram showing the configuration of the analog amplifier section A shown in Fig. 1.
AMP and digital amplifier section D.A waveform diagram showing the AMP output signal, Figure 3 is a circuit diagram showing a more detailed example of the digital amplifier section in the same example, and Figure 4 A is a block diagram showing the configuration of the PWM amplifier circuit. Fig. 5, Fig. 5 is a circuit diagram of a conventional amplifier using the voltage switching method, and Fig. 6 shows the number of switching stages and power loss in the voltage switching method. FIG. 5...Absolute value detection circuit, 6...Level detection comparator, 7...Encoder (5, 6, and 7 above are conversion circuits), _V0 to _V2 ...Voltage source, SWA to SWD...
…Field effect transistor (switching circuit), D ₁ to _{D 3} …
...Diode (switching circuit), D.AMP...Digital power amplifier, A.AMP...Analog power amplifier.

Claims (1)

[Claims for Utility Model Registration] (a) Conversion that compares the absolute value of an analog input signal with a plurality of preset reference values, and sequentially converts the analog input signal into a binary digital code based on the comparison results. a circuit, a plurality of voltage sources provided in a number corresponding to each bit of the binary code, and whose voltage value is weighted corresponding to each bit; (b) a digital power amplifier that outputs the analog input signal by connecting it in series; A power amplifier characterized by comprising: an analog power amplifier used for