JPH05206457A - Mos field effect transistor semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a MOS field effect transistor semiconductor device that can be miniaturized and has a high surge withstand voltage. A polycide layer 7 is provided on a field oxide film 3 which isolates an N ⁺ activation region 2 of a MOS field effect transistor semiconductor device via an interlayer insulating film 4a, and the polycide layer 7 and a metal wiring 5c are formed. The connection is made by ohmic contact, and the ground potential is applied to the metal wiring 5c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor semiconductor device, and more particularly to a device structure of a MOS field effect transistor.

[0002]

BACKGROUND OF THE INVENTION Figure 2 is a sectional view showing a device structure of a conventional MOSFET transistor, in FIG, 1 is P ^- -type Si substrate, 2 an N ⁺ active region formed by ion implantation of N-type, Reference numeral 3 is a field oxide film, 4 is an interlayer insulating film between the N ⁺ activation region 2 and the metal wiring, and 5a and 5b are metal wirings, which are connected to the N ⁺ activation region 2 through the ohmic contact portion 6. ..

Next, the operation will be described. Now, it is assumed that the metal wiring 5a is connected to a high potential (V _CC ) and the metal wiring 5b is connected to a low potential (V _SS or ½ V _CC ). When an extremely steep positive surge is applied to the V _CC terminal from outside the chip, both potentials have been electrically separated by the field oxide film 3 until now. From the N ⁺ activation region 2 ohmic-connected to the wiring 5a, through the substrate 1, the metal wiring 5
A current flows in the N ⁺ activation region 2 which is ohmic-connected to b. If this phenomenon occurs for a relatively long time,
The ohmic contact portion 6 will be destroyed by the concentration of charges.

[0004]

Since the conventional MOSFET transistor is constructed as described above, the surge withstand voltage is low, and in order to solve the above-mentioned problem of destruction of the ohmic contact portion, the thickness of the field oxide film 3 is increased. Therefore, the thickness of the field oxide film 3 must be increased, the width of the field oxide film 3 must be increased, and the metal wiring 5a must be changed to polycide, which is a high-melting point material, which is not suitable for device miniaturization. there were.

The present invention has been made to solve the above problems, and an object thereof is to obtain a MOS type field effect transistor semiconductor device which can be miniaturized and which has a higher surge withstand voltage.

[0006]

In a MOS field effect transistor semiconductor device according to the present invention, a polycide layer made of a refractory material is placed on an element isolation field oxide film with an interlayer insulating film interposed therebetween. And a metal wiring are connected by an ohmic contact, and a ground potential is applied to the metal wiring.

[0007]

In the MOS field effect transistor semiconductor device according to the present invention, a polycide layer made of a high melting point material is placed on an element isolation field oxide film via an interlayer insulating film,
Since the polycide layer and the metal wiring are connected by ohmic contact and the ground potential is applied to the metal wiring, even if a surge is applied from the outside, a current may flow under the field oxide film. It gets harder.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a MOS field effect transistor semiconductor device according to an embodiment of the present invention, in which 1 is P ^−.
Si substrate, 2 is N ⁺ formed by N type ion implantation
The activation region 3 is a field oxide film for element isolation, 5a,
Reference numerals 5b and 5c are metal wirings, 4a and 4b are interlayer insulating films between the N ⁺ activation region 2 and the polycide layer 7, and interlayer insulating films between the polycide layer 7 and the metal wirings 5a, 5b and 5c. , 5c are metal wirings, which are connected to the N ⁺ activation region 2 and the polycide layer 7 via ohmic contact portions 6, 8.

Next, the operation will be described. Metal wiring 5a
Is connected to a high potential (V _CC ) and the metal wiring 5b is connected to a low potential (V _SS or 1/2 V _CC ).
c is connected to the ground potential (V _SS ). Metal wiring 5c
Is applied with the ground potential (V _SS ) and is connected to the polycide layer 7 through the ohmic contact portion 8, so that the ground potential is applied to the substrate 1 through the field oxide film 3 which is the base of the polycide layer 7. .. As a result, even if a sharp positive surge is applied to the V _CC terminal from the outside of the chip, the reverse potential is applied to the substrate 1 that is the base of the field isolation film 3 for element isolation, so that a high potential ( V _CC )
Prevent through the substrate 1, from the low potential _{(V SS, 1 / 2V CC} ) punchthrough current to N ⁺ active region 2 which is applied flows ^- but from N ⁺ active region 2 being applied, P be able to. As described above, according to this embodiment, it is possible to obtain a MOS type field effect transistor semiconductor device which has a high surge withstand voltage and can be miniaturized.

[0010]

As described above, according to the MOS field effect transistor of the present invention, the polycide layer of high melting point material is placed on the field oxide film for element isolation through the interlayer insulating film, and the polycide layer is formed. Since the layer and the metal wiring are connected by ohmic contact and the ground potential is applied to the metal wiring, a MOS with a small area and a high surge withstand voltage is provided.
Type field effect transistor semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a MOS field effect transistor semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional MOS field effect transistor semiconductor device.

[Explanation of symbols]

1 P ⁻ Substrate 2 N ⁺ Activation Region 3 Element Isolation Field Oxide Film 4 Interlayer Insulating Film 5 Metal Wiring 6 Ohmic Contact Part (N ⁺ − Metal Wiring) 7 Polycide 8 Ohmic Contact Part (Polycide-Metal Wiring)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H01L 29/46 D 7738-4M

Claims (1)

[Claims] 1. A MOS type field effect transistor semiconductor device having an element region and a field oxide film separating the element region, wherein a polycide layer, which is a high melting point material, is provided on the field oxide film via an interlayer insulating film. And is connected to the polycide layer by ohmic contact,
A MOS field effect transistor semiconductor device, comprising: a metal wiring to which a ground potential is applied.