JPH05218093A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a uniform threshold voltage by reliably executing the control of the threshold voltage by the wet etching which has hitherto been difficult for a field effect transistor and in its manufacture method. CONSTITUTION:In the structure of a recessed type field effect transistor, an AlAs layer 15 is formed as a recess etching suspension layer on an electron supply layer 14 in the 2DEGFET or on the operation layer in the MESFET. Hence, when a wet etching is executed, it is possible to obtain a uniform threshold voltage in a wafer without etching the electron supply layer 14 or the operation layer under a contact resistance reduction cap layer 16. Also, it is possible to easily and selectively etch the AlAs layer 15 immediately before the formation of a gate electrode 19. Therefore, the movement of electron from the gate electrode 19 to the electron supply layer 14 is not hindered, either.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recess type field effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art A two-dimensional electron gas field effect transistor (hereinafter referred to as 2DEGFET) is a field effect transistor utilizing two-dimensional electron gas accumulated at a heterojunction interface and has excellent high speed and low noise. It has been put to practical use as an amplifying element for ultra-low noise and high frequency. Further, research and development of integrated circuits and the like using 2DEGFET have been actively conducted.

FIG. 3 is a schematic structural diagram of a conventional AlGaAs / GaAs 2DEGFET as a typical example of the 2DEGFET.

In the figure, a semi-insulating GaAs substrate 31 is shown.
An undoped GaAs buffer layer 32, an undoped GaAs electron transit layer 33, an impurity-doped AlGaAs electron supply layer 34, and an impurity-doped GaAs contact resistance reducing cap layer 35 are formed on the upper surface by an epitaxial growth method.
It is sequentially laminated. A gate electrode 36 is formed on the surface of the central portion of the electron supply layer 34, and source and drain electrodes 37 and 38 are provided on the cap layer 35, respectively.

On the other hand, a metal / semiconductor field effect transistor (hereinafter referred to as MESFET) is the most general element of an ultra-high frequency / ultra-high speed device that has been studied for a long time, and is currently being put into practical use. Most of the
Research and development of large-scale integrated circuits has been reached.

FIG. 4 shows a schematic structural diagram of a conventional GaAs MESFET as a typical example of the MESFET.

In the figure, a semi-insulating GaAs substrate 41 is shown.
An undoped GaAs buffer layer 42, an impurity-doped GaAs operation layer 43, and an impurity-doped GaAs contact resistance reducing cap layer 44 are sequentially stacked on the upper surface by an epitaxial growth method. Then, the gate electrode 45 is formed on the surface of the central portion of the operating layer 43, and the cap layer 4 is formed.
4 are provided with source and drain electrodes 46 and 47, respectively.

Here, as shown in FIGS. 3 and 4, in 2DEGFET and MESFET, a recess structure is used as a method of defining the threshold voltage. The formation of the recess structure shown in FIGS. 3 and 4 is performed by removing the impurity-doped GaAs contact resistance reducing cap layers 34 and 44 in the gate electrode forming portion by etching using a photoresist pattern or the like as a mask, and recessing the gate electrode. It is formed inside.

[0009]

By the way, the recess structure in the 2DEGFET shown in FIGS. 3 and 4 is Ga
In order to remove the As contact resistance reducing cap layer, for example, H ₂ SO ₄ —H ₂ O _{2 is} used as an etching solution.
The system is used. However, the etching rate changes depending on the conditions such as the concentration of the etching solution, the temperature, and the stirring conditions.
Moreover, since the selectivity of the etching rate between GaAs and AlGaAs cannot be obtained, the AlGaAs layer which is the electron supply layer is also etched, and the operation layer is also etched in the MESFET. Due to this, there has been a problem that the threshold voltage cannot be controlled uniformly and an error of about 8% appears in the plane.

An object of the present invention is to solve the above-mentioned problems by using an AlAs layer as a recess etching stop layer in 2D.
On the electron supply layer in the EGFET, and also in the MESFET
In order to provide a semiconductor device having good controllability of the threshold voltage, the etching is surely stopped on the electron supply layer or the operation layer by providing it in the operation layer.

[0011]

The present invention comprises a semiconductor substrate, a buffer layer formed on the semiconductor substrate, an electron transit layer made of an intrinsic semiconductor adjacent to the buffer layer, and the electron transit layer. And an electron supply layer, which is made of a semiconductor doped with impurities and has an electron affinity smaller than that of the intrinsic semiconductor, and a contact resistance reduction layer that is stacked on the electron supply layer. A two-dimensional recess structure including a cap layer and having a recess structure obtained by etching away a gate electrode portion of the contact resistance reducing cap layer when forming a Schottky junction gate electrode on the electron supply layer. In an electron gas field effect transistor, AlA
The s layer is formed as a recess etching stop layer between the electron supply layer and the contact resistance reducing cap layer.

The present invention also includes a semiconductor substrate, a buffer layer formed on the semiconductor substrate, an operation layer adjacent to the buffer layer, and a contact resistance reducing cap layer laminated on the operation layer. And a metal-semiconductor field effect transistor having a recess structure obtained by etching away a gate electrode portion of the contact resistance reducing cap layer when forming a Schottky junction gate electrode on the operation layer. At Al
The As layer is formed as a recess etching stop layer between the operating layer and the contact resistance reducing cap layer.

The method of manufacturing a field effect transistor according to the present invention is characterized by including a step of selectively removing the etching stopper layer before forming the gate electrode.

[0014]

In the present invention, by using AlAs as the recess etching stop layer, for example, the in-plane error of the threshold voltage is suppressed within 3% without etching the adjacent electron supply layer or operation layer. A uniform control that can be achieved is realized. Since the AlAs layer used as the etching stopper layer has almost no difference in lattice constant from GaAs or AlGaAs, there is no problem in crystal growth. In addition, a step of selectively removing only the deliquescent AlAs layer used as the etching stop layer by thoroughly washing with ultrapure water before forming the gate electrode is provided. It can be achieved without disturbing the transfer of electrons to the layer.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Here, as an example, AlGa
An example of an As / GaAs-based 2DEGFET will be described. However, the material is not limited to this material, and by forming an AlAs layer having a thickness of, for example, about 100 Å as an etching stop layer on the electron supply layer, it is possible to reliably perform the same. By selectively etching the impurity-doped GaAs contact resistance reducing cap layer, the etching can be stopped without cutting the active layer.

FIG. 1 shows a cross section of the device of the embodiment. As shown in FIG. 1, the following layers are formed on the semi-insulating GaAs substrate 11 by epitaxial growth. 12: undoped GaAs buffer layer 13: undoped GaAs electron transit layer 14: impurity-doped Al _0.3 Ga _0.7 As electron supply layer 15: undoped AlAs etching stop layer (thickness 10
16: Impurity-doped GaAs contact resistance reducing cap layer 16 Here, the impurity-doped GaAs contact resistance reducing cap layer 16 is a layer for making good ohmic contact.

Next, the source and drain electrodes 17 and 1 made of ohmic contact metal are formed on the surface of the growth substrate.
8 is formed by a lift-off method or the like, and an undoped G is formed in which a two-dimensional electron gas is formed by an alloy method for applying heating or the like.
It is in contact with the aAs electron transit layer 13. Next, impurity doping G between the source and drain electrodes 17 and 18
The aAs contact resistance reducing cap layer 16 is partially removed by etching, and a gate electrode 19 made of a metal for Schottky junction is formed in that portion. By thoroughly washing with ultrapure water immediately before forming the gate electrode 19, only deliquescent AlAs can be selectively removed easily and surely. As a result, the gate electrode can be directly formed on the active layer as in the conventional case, so that the movement of electrons from the gate electrode to the electron supply layer is not hindered.

In the above embodiment, the Al composition ratio of AlGaAs is set to 0.3, but it goes without saying that the Al composition ratio is not limited to this. Also, the thickness of the etching stop layer can be changed appropriately.

(Embodiment 2) Here, as an example, GaAs is used.
An example of a system MESFET will be described. However, the material is not limited to this material, and an AlAs layer having a thickness equal to or less than the critical thickness is formed as an etching stop layer on the electron supply layer to ensure that the impurity-doped GaAs is doped. The contact resistance reducing cap layer can be selectively etched.

FIG. 2 shows a cross section of an element according to an embodiment of the present invention.
As shown in FIG. 2, the following layers are formed on the semi-insulating GaAs substrate 21 by epitaxial growth. 22: undoped GaAs buffer layer 23: impurity-doped GaAs operating layer 24: AlAs etching stop layer (thickness: about 100 Å) 25: impurity-doped GaAs contact resistance reduction cap layer Here, impurity-doped GaAs contact resistance reduction cap layer 25 Is a layer for making good ohmic contact.

Next, source and drain electrodes 26 and 2 made of ohmic contact metal are formed on the surface of the growth substrate.
7 is formed by a lift-off method or the like, the impurity-doped GaAs contact resistance reducing cap layer 25 between the source and drain electrodes 26 and 27 is partially removed by etching, and a gate electrode 28 made of a Schottky junction metal is formed in that portion. Has been formed.

Immediately before the gate electrode 28 is formed, it is thoroughly washed with ultrapure water to obtain a deliquescent A.
Only 1As can be easily and surely selectively removed by etching. As a result, the gate electrode can be directly formed on the active layer as in the conventional case, so that the movement of electrons to the gate electrode or the electron supply layer is not hindered.

[0024]

As described above, according to the present invention,
The selective etching, which has been a problem in wet etching when forming a recess structure, is stopped reliably on the electron supply layer by forming an AlAs layer as an etching stop layer to control the threshold voltage within the surface. Error 3
% Or less evenly. Moreover, the selective removal of the etching stopper layer does not hinder the movement of electrons from the gate electrode to the electron supply layer.

[Brief description of drawings]

FIG. 1 is a sectional view of an element structure showing an embodiment of a 2DEGFET of the present invention.

FIG. 2 is a cross-sectional view of a device structure showing an embodiment of MESFET of the present invention.

FIG. 3 is a sectional view of a device structure of a conventional 2DEGFET.

FIG. 4 is a sectional view of a device structure of a conventional MESFET.

[Explanation of symbols]

11, 21 GaAs substrate 12, 22 undoped GaAs buffer layer 13 undoped GaAs electron transit layer 14 impurity-doped Al _0.3 Ga _0.7 As electron supply layer 15 undoped AlAs etching stop layer 16 impurity-doped GaAs contact resistance reduction cap layer 17, 26 source electrode 18, 27 Drain electrode 19, 28 Gate electrode 23 Impurity-doped GaAs operating layer 24 Undoped AlAs etching stop layer 25 Impurity-doped GaAs Contact resistance reduction cap layer

Claims (3)

[Claims] 1. A semiconductor substrate, a buffer layer formed on the semiconductor substrate, an electron transit layer made of an intrinsic semiconductor adjacent to the buffer layer, and an electron affinity of the intrinsic semiconductor constituting the electron transit layer. An electron supply layer formed of a semiconductor having a small electron affinity and doped with impurities, the electron supply layer being stacked on the electron transit layer, and the contact resistance reducing cap layer being stacked on the electron supply layer. In forming a Schottky junction gate electrode on an electron supply layer, a two-dimensional electron gas field effect transistor having a recess structure obtained by etching away the gate electrode portion of the contact resistance reducing cap layer, wherein AlAs is used. A layer is formed as a recess etching stop layer between the electron supply layer and the contact resistance reducing cap layer. Field effect transistor, characterized in that the. 2. A semiconductor substrate, a buffer layer formed on the semiconductor substrate, an operation layer adjacent to the buffer layer, and a contact resistance reducing cap layer laminated on the operation layer, In a metal-semiconductor field effect transistor having a recess structure obtained by removing a gate electrode portion of the contact resistance reducing cap layer by etching when forming a Schottky junction gate electrode on the operation layer, AlAs A field effect transistor, wherein a layer is formed as a recess etching stop layer between the operating layer and the contact resistance reducing cap layer. 3. The method of manufacturing a field effect transistor according to claim 1, further comprising the step of selectively removing the etching stopper layer before forming a gate electrode. Method.