JPH0522090A - Variable delay line device - Google Patents

Abstract

(57) [Summary] [Object] To provide a variable delay line device capable of obtaining a desired delay amount even if the characteristics vary due to temperature changes or manufacturing variations. [Structure] In a training mode, a training signal TR is generated by a training signal generation circuit 13 and is supplied to a delay line 15, and the delay line 15 is set to an appropriate delay amount in advance, and then actually used. The input signal Vi to be supplied is supplied to the delay line 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay line device which is used in a digital audio signal processing circuit or the like and can vary the delay amount of an input signal. The present invention relates to a variable delay line device set to.

[0002]

2. Description of the Related Art In a delay line device in which a signal applied to an input terminal is output to an output terminal with a certain delay, a coil having a coil 1, 2 and a capacitor 3 as shown in FIG. Some are composed of. This type of delay line device uses the coils 1 and 2 which are difficult to integrate, and thus has a drawback that the circuit scale becomes large. As a solution to this problem, a delay line device in which integrated CMOS buffers are cascaded in a plurality of stages has been used. This delay line device can change the delay amount by changing the power supply voltage of the CMOS buffer.

[0003]

However, this C
In a MOS buffer delay line device, a desired delay amount can be obtained because the temperature characteristics of the M0S buffer change due to temperature changes, or variations in other various characteristics occur due to manufacturing variations of the CMOS buffer. There was a problem of not having.

The present invention has been made in view of the above circumstances, and provides a variable delay line device capable of obtaining a desired delay amount even if the characteristics vary due to temperature changes or manufacturing variations. ..

[0005]

A variable delay line device according to the present invention is a variable delay line device having a plurality of cascaded buffer circuits for delaying an input signal with a delay amount according to a change in a power supply voltage. The following measures have been taken. That is, a delay amount storage unit that stores an arbitrary delay amount, a training signal generation circuit that sends a training signal of a constant cycle to the buffer circuit side in the training mode, and a delay amount of the training signal by the buffer circuit is detected. The delay amount detecting means, the difference detecting means for detecting the difference between the delay amount detected by the delay amount detecting means and the delay amount stored in the delay amount storing means, and the difference detecting means delay amount detecting means. Hold means for holding the detected difference information and power supply voltage control means for generating the power supply voltage according to the difference information held by the hold means are provided, and the power supply voltage control means generates the power supply voltage in the training mode. The above problem is solved by driving the buffer circuit with a power supply voltage.

[0006]

In the variable delay run device according to the present invention, the training signal is used in the training mode, the buffer circuit is set to an appropriate delay amount in advance, and then the input signal to be actually used is supplied to the buffer circuit. Since this is done, even if an error occurs in the delay amount of the buffer circuit due to temperature changes or manufacturing variations, the error is corrected.
As a result, the input signal is delayed by an appropriate delay amount.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a variable delay run device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block circuit diagram showing a schematic configuration of a variable delay line device according to an embodiment of the present invention.
In FIG. 1, when the input signal Vi having the data format shown in FIG. 2 including the training area is input to the input terminal 10, the input signal Vi is supplied to the mode changeover switch 11 while the control signal is controlled. It is supplied to the circuit 12. In the control circuit 12, when a CPU (not shown) decodes the data format of the input signal Vi and detects a training area in the data format, it sends a control signal for generating the training signal TR to the training signal generation circuit 12a, and simultaneously switches. A control signal for mode switching is sent to the switch 11.

The mode changeover switch 11 receives a control signal for mode changeover and changes over to a training mode,
The training signal generation circuit 12a sends the training signal TR to the mode changeover switch 11. As shown in FIG. 3, the training signal TR is configured by a signal pattern in which N (positive integer) clock pulses and intermediate pulses are alternately repeated at a constant cycle.

In this way, the training signal TR is supplied via the input buffer 14 to the delay line 15 in which n CMOS buffers (buffer circuits) 16 are cascaded. After that, the training signal TR
Is delayed for a fixed time and is taken out as a training output signal TS from the CMOS buffer 16 at the final stage of the delay line 15. As shown in FIG. 3, the delay amount of the training output signal TS obtained through the m · n-stage CMOS buffer circuit is m × DT, which is m times the delay amount DT in the n-stage CMOS buffer circuit. Become.

On the other hand, the training signal generating circuit 13 is
An enable signal E as shown in FIG. 3 which is at a low level during the period corresponding to the intermediate pulse of the training signal TR.
N is sent to the clear terminal of the counter 17. When the enable signal EN is at the low level, the counter 17 starts counting the number of clocks in the output signal TS. When the count result is M, the delay amount DT in the n-stage CMOS buffer circuit can be expressed by the following equation. DT = (M / m) × TCK However, TCK; time of one clock Therefore, the delay amount DT in the time TCK of one clock can be expressed by increasing the above m.

The count result M of the counter 17 is given to the comparator 18 (detection means). Further, the register (delay amount storage means) 19 stores a value Ma corresponding to a desired delay amount in advance. The comparator 18 detects the difference between the count result M and the value Ma, and sends the potential corresponding to the detected difference to the changeover switch 21 of the holding means 20. On the other hand, the counter 22 of the control circuit 12 counts the number of clocks of the training signal TR, and turns on the changeover switch 21 when the count value becomes N.

As a result, the potential supplied from the comparator 18 is held in the capacitor 24 via the switch 23 and the resistor 23. Immediately after that, since the changeover switch 21 is turned off, the capacitor 2
The potential held at 4 is supplied to the power supply voltage control means 25 including the buffers 26 and 27. As a result, the power supply voltage of the CM0S buffer 16 of each stage changes according to the potential, and the delay amount of the delay line 15 is set to an appropriate value.

In this way, after the delay amount of the delay line 16 is set to an appropriate value, the mode changeover switch 11 is switched to the normal mode, and the input signal Vi is delayed by the delay line 15 via the mode changeover switch 11 and the input buffer 14. Entered in. As a result, the input signal Vi
Is delayed by an appropriate delay amount and output from the output terminal 30 via the output buffer 29 as the output signal Vo.

As described above, in the present embodiment, the training signal TR is used in advance to set the delay line 15 to an appropriate delay amount, and then the actually used input signal Vi is supplied to the delay line 15. Therefore, the delay line 15 is affected by temperature changes and manufacturing variations.
Even if an error occurs in the delay amount of, the error is corrected and the input signal Vi is delayed by an appropriate delay amount.

[0016]

As is apparent from the above description, in the variable delay line device according to the present invention, in the training mode, the training signal generating circuit sends the training signal of a constant cycle to the buffer circuit side, and the above-mentioned buffer circuit. The delay amount of the training signal is detected by the delay amount detecting means, the difference from the preset delay amount is detected by the difference detecting means, and the buffer circuit is supplied with the power supply voltage according to the difference information held by the holding means. Is driven, even if an error occurs in the delay amount of the buffer circuit due to temperature change or manufacturing variation, the error is corrected. As a result, the input signal can be delayed with an appropriate delay amount.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a variable delay line device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data format of an input signal.

3 is an operation timing chart of FIG.

FIG. 4 is a circuit diagram of a conventional delay line.

[Explanation of symbols]

 11 ... Mode change switch 13 ... Training signal generating circuit 16 ... Buffer circuit 17, 22 ... Counter 18 ... Comparator 19 ... Register 20: Hold means

Claims (1)

Claim: What is claimed is: 1. A variable delay line device having a plurality of cascaded buffer circuits for delaying an input signal with a delay amount according to a change of a power supply voltage, the delay storing an arbitrary delay amount. Quantity storing means, a training signal generating circuit for sending a training signal of a constant cycle to the buffer circuit side in the training mode, a delay amount detecting means for detecting a delay amount of the training signal by the buffer circuit, and a delay amount Difference detecting means for detecting a difference between the delay amount detected by the detecting means and the delay amount stored in the delay amount storing means, and holding means for holding the difference information detected by the difference detecting means delay amount detecting means And a power supply voltage control for generating the power supply voltage according to the difference information held by the holding means. And means is provided, the variable delay line device characterized by driving the buffer circuit in the power supply voltage generated in the training mode by the power supply voltage control means.