JPH06224705A - Oscillating circuit - Google Patents

Abstract

PURPOSE:To eliminate a delay a time when the oscillation is started by providing a forced charge circuit forcibly charging a voltage of a capacitor to be reached between a 1st reference voltage and a 2nd reference voltage when the oscillation is started. CONSTITUTION:A level of an enable signal E switches from H to L when the oscillation is started. An inverted enable signal E' being the inverse of the signal E by a NOT circuit N2 and an output of a comparator CP3 are given to a NAND circuit G1, in which the signals are logically operated and its output turns on a PMOS transistor(TR) M2, resulting in forcibly charging a capacitor C. When a voltage Vc across the capacitor C exceeds a reference voltage V2, an output of a comparator CP3 is switched to an L level and the output and the signal E' are NANDed to apply an H level signal to a gate of the PMOS TR M2, which is turned off thereby terminating the forced charging. Then the on/off state of the NMOS TRM1 is repeated and the oscillation is continued. The voltage Vc changes between the voltages V1 and V2 and the output of the comparator CP3 remains at an L level and is not inverted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit which oscillates by repeating charging and discharging of a capacitor.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram of a conventional RC oscillator circuit.
FIG. 8 is an operation waveform diagram thereof. Constant current source 3 is constant
Current I₀Is supplied to the capacitor C. Capacitor C
Two NMOS transistors M on both ends of₁, M_FourBut
It is connected in parallel. NMOS transistor M_FourHas
The enable signal E is input. NMOS transistor
Star M₁Is input to the Q output of the flip-flop FF.
Has been. The voltage Vc of the capacitor C is
P₁Negative input terminal and comparator CP₂To the positive input terminal of
Is being applied. Comparator CP₁The positive input terminal of
First reference voltage V ₁Is applied and the comparator C
P₂Has a second reference voltage V₂Is applied
There is. First reference voltage V₁And the second reference voltage V₂Is a figure
As shown in 8,₁> V₂There is a relationship. COMPA
Lator CP₁Output signal of the flip-flop FF.
Input, and comparator CP₂The output signal of
It is the reset input of the lip flop FF.

The operating principle of this RC oscillator circuit is shown in FIG.
It will be described based on. First, the capacitor C has no charge
Charging is started from the state (Vc = 0). During this time, Vc
<V ₂And the comparator CP₁, CP₂And flick
Clock output CLK is low level
The NMOS transistor M is set to₁Is OF
The state becomes F, and the capacitor C has a constant current I.₀Charged by
Be charged. The voltage Vc rises by charging the capacitor C
And Vc = V₁The clock output CLK becomes High.
The NMOS transistor M is set to the h level.₁Is ON
Then, the capacitor C is discharged. Capacitor
The voltage Vc drops due to the discharge of C, and Vc = V₂become
And the clock output CLK is set to low level again.
NMOS transistor M₁Is turned off,
Charging starts again. Hereinafter, the NMOS transistor M₁of
By repeating ON / OFF, as shown in FIG.
Continue oscillating operation.

[0004]

In the conventional RC oscillating circuit, the operation was started from the state where there is no electric charge in the capacitor C as described above.
From the time when charging is started (t = 0) to the time when the voltage Vc of the capacitor C becomes equal to the reference voltage V ₂ (t = t ₁ ).
Until then, the oscillation operation was not performed, and there was a drawback that the oscillation operation was started after a delay of C × V ₂ / I ₀ (= t ₁ ) from the start of charging to Vc = V ₂ .

The present invention has been made in view of the above circumstances, and an object thereof is to eliminate a delay at the start of oscillation in an oscillation circuit that oscillates by repeating charging and discharging of a capacitor. Especially.

[0006]

In the oscillator circuit of the present invention,
In order to solve the above problems, the method shown in FIGS.
In the steady oscillation state, the first reference voltage V
₁And the second reference voltage V ₂Between charging and discharging the capacitor C
In a circuit that oscillates by repeating
At the start, the voltage Vc of the capacitor C is set to the first reference voltage V₁
And the second reference voltage V₂Forced charging to force charging during
The electric circuit 1 is provided.

[0007]

In the present invention, with the above configuration, as shown in FIG. 2, the capacitor C is forcibly charged so that the voltage Vc becomes equal to or higher than the reference voltage V ₂ instantaneously at the start of operation, and oscillation is performed. The delay time until the start can be eliminated.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a circuit diagram showing the structure of an embodiment of the present invention. The circuit configuration will be described below. The constant current source 3 supplies a constant current I ₀ to the capacitor C.
The NMOS transistor M ₁ ,
M ₄ is connected in parallel. The non-grounded terminal of the capacitor C is connected to the line of the control power supply voltage Vdd via the PMOS transistor M ₂ . The enable signal E is input to the gate of the NMOS transistor M ₄ . The gate of the NMOS transistor M ₁ has N
The output signal of the OR circuit G ₂ is input. The NOR circuit G ₂ has the Q output of the flip-flop FF connected to the NOT circuit N.
_The signal is input via ₁ and the enable signal E is also input. At the gate of the PMOS transistor M ₂ ,
The output signal of the NAND circuit G ₁ is input. NAN
The enable signal E is input to the D circuit G ₁ via the NOT circuit N _2, and the output signal of the comparator CP ₃ is input. The voltage Vc of the capacitor C is applied to the negative input terminal of the comparator CP _{1 and} the positive input terminal of the comparator CP ₂ . The first reference voltage V ₁ is applied to the positive input terminal of the comparator CP ₁ , and the second reference voltage V ₂ is applied to the negative input terminal of the comparator CP ₂ . First reference voltage V ₁ and second reference voltage V
₂ has a relationship of V ₁ > V ₂ . Comparator CP
The output signal of ₁ serves as the set input of the flip-flop FF, and the output signal of the comparator CP ₂ serves as the reset input of the flip-flop FF.

Next, the voltage detection control circuit 2 in FIG.
That is, the voltage Vc of the capacitor C is detected and the PMO
The circuit for controlling the S transistor M ₂ is composed of a hysteresis circuit as shown in FIG. In this circuit, the voltage Vc of the capacitor C are applied to the negative input terminal of the comparator CP _3, the positive input terminal of the comparator CP _3, the reference voltage V ₂ is applied through a resistor R _1. Further, the positive input terminal of the comparator CP ₃ is connected to the resistor R
₂ and the ground via the NMOS transistor M ₃ . The output signal of the NOT circuit N ₃ is input to the gate of the NMOS transistor M ₃ . The output signal of the comparator CP ₃ is input to the input of the NOT circuit N ₃ . The output signal of the comparator CP ₃ is NA
It is input to the ND circuit G ₁ .

FIG. 5 shows the input / output characteristics of the hysteresis circuit. When the input voltage Vc is Vc <V _3, a high level is output as the output voltage Vout, which is converted to a low level by the NOT circuit N _3, so that the NMO
The S transistor M ₃ is turned off and V ₃ = V ₂
Becomes Therefore, when the voltage Vc of the capacitor C is lower than the reference voltage V ₂ , the hysteresis circuit holds this state, but the voltage Vc of the capacitor C is changed to the reference voltage V _2.
Output voltage Vout becomes Low level,
The state of the hysteresis circuit is reversed. Even if the voltage Vc of the capacitor C further rises, the output voltage Vout becomes Low.
You will be kept at the level. Output voltage Vout is Lo
When it becomes the state of w level, it becomes High by the NOT circuit N _3.
Voltage obtained by inverting the level is applied to the gate of the NMOS transistor M _3, NMOS transistor M ₃ represents a state is ON. When the NMOS transistor M ₃ is turned on, the voltage V ₃ divided by the resistors R ₁ and R ₂ is applied to the positive input terminal of the comparator CP ₃ . This voltage is
V ₃ = V ₂ × the _{R 2 / (R 1 + R} 2). While Vc of the capacitor C is Vc> V ₃ , the output voltage Vout is Lo.
When the state of w level continues and the voltage Vc of the capacitor C becomes smaller than the resistance-divided reference voltage V ₃ , the output voltage Vout is inverted and becomes a high level state. If the hysteresis width of this hysteresis circuit is ΔV, then Δ
_{V = V 2 -V 3 = V} 2 × R 1 / (R 1 + R 2) become.
If the values of the resistors R ₁ and R ₂ are selected, the desired hysteresis width Δ
V is obtained.

FIG. 6 is an operation waveform diagram of this embodiment. motion
At the start, the enable signal E changes from High level to L
Switch to ow level. Negate this enable signal E
Circuit N₂And the inversion enable signal E'inverted by
Computer CP₃Output of NAND circuit G₁Logical operation with
The PMOS transistor M₂Is ON
Then, the capacitor C is forcibly charged. For forced charging
Therefore, the voltage Vc of the capacitor C becomes the reference voltage V₂Cross over
And the comparator CP₃Output switches to low level
Instead, this and the inverted enable signal E '(= High level
(2) NAND, the PMOS transistor M₂Ge of
High level signal is added to the
Dista M₂Turns off and the capacitor C is forced
Charging ends. After that, the operation principle explained in the conventional example
Causes the NMOS transistor M ₁ON / OFF is repeated
It is returned and oscillation continues. At this time, the capacitor C
Voltage Vc is reference voltage V₁And V₂To change between
And the comparator CP₃Output is in the low level
It's still there, and it's never reversed. This was mentioned above
As shown, a comparator CP with hysteresis characteristics₃For
This was made possible by the fact that it happened. According to
During oscillation, the PMOS transistor M₂Is OFF
It remains in the state and forced charging of the capacitor C occurs.
Not. Also, the time required to forcibly charge the capacitor C
Is the constant current I₀And the time to charge the capacitor C by
In comparison, it is so small that it can be ignored. The above
The capacitor C is forcibly charged only when the operation starts from
This eliminates the delay at the start of oscillation.

[0012]

According to the present invention, in a circuit that oscillates by repeatedly charging and discharging a capacitor between a first reference voltage and a second reference voltage in a steady oscillation state, the capacitor is started at the start of oscillation. Since the forced charging circuit that forcibly charges the voltage of 1 between the first reference voltage and the second reference voltage is provided, it is possible to quickly shift to the state where oscillation is possible at the start of oscillation and eliminate the delay at the start of oscillation. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is an operation waveform diagram of the present invention.

FIG. 3 is a circuit diagram of an embodiment of the present invention.

FIG. 4 is a circuit diagram of a hysteresis circuit used in an embodiment of the present invention.

FIG. 5 is an input / output characteristic diagram of a hysteresis circuit used in an embodiment of the present invention.

FIG. 6 is an operation waveform diagram of one embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional oscillator circuit.

FIG. 8 is an operation waveform diagram of a conventional example.

[Explanation of symbols]

 1 Forced charging circuit 2 Voltage detection control circuit 3 Constant current source C Capacitor

Claims (1)

[Claims] 1. In a circuit that oscillates by repeating charging and discharging of a capacitor between a first reference voltage and a second reference voltage in a steady oscillation state, the voltage of the capacitor is set to the first voltage at the start of oscillation. An oscillator circuit comprising a forced charging circuit for forcibly charging between a reference voltage and a second reference voltage.