JPH0523081B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit, and more particularly to a transistor circuit suitable for an integrated circuit that controls the polarity of an output signal with respect to an input signal in accordance with a switching signal.

As such a transistor circuit, a double-balanced differential amplifier circuit, as shown in FIG. 1, has conventionally been used. That is, a first differential amplifier consisting of transistors 4 and 5, a second differential amplifier consisting of transistors 6 and 7, and transistors 4 and 5.
A double-balanced differential amplifier is constituted by a third differential amplifier consisting of transistors 1 and 2 whose respective collectors are connected to the common emitters of transistors 5 and 6 and 7, respectively. A current source 3 is connected to the common emitters of transistors 1 and 2 in the third differential amplifier, and the bases of transistors 1 and 2, which serve as differential inputs, are connected to input terminals 11 and 12, respectively. The bases of transistors 5 and 6 in the first and second differential amplifiers are commonly connected to a reference power supply 10, and the bases of transistors 4 and 7 are commonly connected to a switching signal input terminal 8. The collectors of transistors 4 and 6 are connected to the V _CC power supply, and the collectors of transistors 5 and 7 are commonly connected and connected to the V _CC power supply via a load resistor 20 and to the output terminal 13 .

Next, the operation of the circuit shown in FIG. 1 will be explained. A voltage higher than the reference power supply 10 is applied to the switching signal input terminal 8 so that the transistors 4 and 7 are made conductive and the transistors 5 and 6 are made non-conductive. When a signal is applied, an output signal having the same polarity as the input signal appears at the output terminal 13. Next, a reference power supply 10 is connected to the switching signal input terminal 8 so that the transistors 5 and 6 are made conductive and the transistors 4 and 7 are made non-conductive.
When a lower voltage is applied, an output signal of opposite polarity to the input signal appears at the output terminal 13. In this way, the circuit shown in FIG. 1 can control the polarity of the input signal according to the voltage level of the switching terminal 8.

However, with the configuration shown in FIG. 1, it is not possible to obtain an output signal amplitude from approximately the ground potential to the V _CC voltage. In other words, a wide output dynamic range cannot be obtained. Further, there is a drawback that the DC voltage at the output terminal 13 is also subject to restrictions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transistor circuit which provides a sufficient output dynamic range and which controls the polarity of an output signal with respect to an input signal in which circuit constants can be easily determined.

The present invention provides first and second circuits having opposite polarities that are cascade-connected and at least one of which is supplied with an input signal.
a first current mirror circuit whose input terminal is connected to the first transistor; and whose input terminal is connected to the second transistor and whose output terminal is connected to the output terminal of the first current mirror circuit. a second current mirror circuit, and a first and second current mirror circuit;
and a switch circuit for controlling the operating state of the first and second current mirror circuits, and is characterized in that an output signal is obtained from a common output terminal of the first and second current mirror circuits.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 2 shows a basic configuration diagram of the present invention. In FIG. 2, a first transistor 14 and a second transistor 15 with a common emitter resistor 16 connected between their emitters have different conductivities, and the base of the first transistor 14 is connected to a first input terminal. 11 , and the base of the second transistor 15 is connected to the second input terminal 12 . The collector of the first transistor 14 is connected to the input terminal of the first current mirror circuit 17, and the collector of the second transistor 15 is connected to the input terminal of the first current mirror circuit 17.
It is connected to the input terminal of 8. The respective output terminals of the first and second current mirror circuits 17 and 18 are connected to a common load 20 connected to a bias source 22.
and further connected to the output terminal 13. first and second current mirror circuits 17,
The operating state of 18 is controlled by switch circuits 19 and 20.

Now, apply an appropriate bias voltage to the second input terminal 12 to turn the transistor 15 into a current source, and operate the switch 21 to turn on the current mirror circuit 18.
When turned off, an output signal of the same polarity as the input signal supplied to the first input terminal 11 is obtained at the output terminal 13. On the other hand, when the switch 19 is operated to cut off the current mirror circuit 17, an output signal having the opposite polarity to the input signal is obtained. In this way, the polarity of the output signal relative to the input signal can be controlled. In addition, by setting the potential of the bias source 22 connected to one side of the load 20, a wide output dynamic range can be obtained, and by switching the potential of the bias source 22 for each output signal polarity, each operating point and dynamic range can be adjusted. It becomes possible to set the range arbitrarily. Since the switches 19 and 20 can be constructed from transistors, the circuit has a relatively simple construction and is suitable for integration.

FIG. 3 shows a specific embodiment of the present invention and will be described in detail. Elements that are the same as in FIG. 2 are designated by the same numbers. In FIG. 3, the bases of the transistors 14 and 15 are connected to the input terminals 11 and 15, respectively.
12, and a resistor 16 is connected between the emitters of each transistor 14 and 15. PNP
The transistors 23 and 24 constitute a first current mirror circuit 17, and the collector of the transistor 14 is connected to the collector (ie, input terminal) of the diode-connected transistor 23.
NPN transistors 26 and 27 constitute a second current mirror circuit 18, and the collector (input end) of diode-connected transistor 26 is connected to the collector of transistor 15. First,
The output terminals of the second current mirror circuits 17 and 18 (i.e., the collectors of the transistors 24 and 27)
are commonly connected and connected to a resistor 29 constituting the load 20 and to the output terminal 13. The opposite side of load resistor 29 is connected to the common collector of transistors 30 and 31 forming bias source 22 . The emitter of transistor 30 is the power supply
The emitter of the transistor 31, which is connected to V _CC and whose base is connected to the switching signal input terminal 36 through the resistor 32, is grounded, and whose base is connected to the resistor 33.
It is connected to the switching signal input terminal 36 through. The transistor 25 and the resistor 34 are the switch circuit 1
9, the collector of the transistor 25 is connected to the common base of the transistors 23 and 24 constituting the first current mirror circuit 17, and the emitter thereof is connected to the power supply V _CC . Transistor 28 and resistor 35 constitute switch circuit 21. The collector of transistor 28 is connected to the common base of transistors 26 and 27, which constitute a second current mirror circuit, and its emitter is grounded. resistance 3
The other ends of 4 and 35 are connected to a switching signal input terminal 36.

Next, the operation of this circuit will be explained. Note that for ease of explanation, it is assumed that V _CE (sat)=0. A suitable bias is applied to the input terminal 12 to make the transistor 15 a current source, and a power supply voltage, for example, is applied to the switching signal input terminal 36. Since the power supply voltage is applied to the switching signal input terminal 36 of the transistors 25 and 28 of the switch circuits 19 and 20, the transistor 28 becomes conductive and the transistor 25 becomes non-conductive. Therefore, the first current mirror circuit 17 consisting of transistors 23 and 24 becomes conductive, but the transistor 2
A second current mirror circuit 18 consisting of 6 and 27
becomes non-conducting. Further, since the transistor 30 is non-conductive and the transistor 31 is conductive, the potential on the opposite side of the load resistor 29 from the output terminal 13 becomes the GND potential. In this state, when an input signal is input to the input terminal 11, a current proportional to the input signal flows into the resistor 29, and as a result, the output terminal 13
An output signal with the same polarity as the input signal appears.
Next, when the switching signal input terminal 36 is grounded, the transistors 28 and 31 become non-conductive, contrary to the case where the power supply voltage was applied as described above, and the transistor 2
5 and 30 become conductive, the second current mirror circuit 18 becomes conductive, and the potential on the opposite side of the load resistor 29 from the output terminal 13 becomes V _CC . In this state, when an input signal is applied to the input terminal 11, the second current mirror circuit 18 draws a current proportional to the current flowing through the transistors 14 and 15 from the load resistor 29, and as a result, the output terminal 13
An output signal with a polarity opposite to that of the input signal will appear.

Note that the same effect can be obtained by applying the input signal to the second input terminal 12 or by applying the input signal to both input terminals 11 and 12.

In this way, the circuit shown in FIG. 3 can easily reverse the polarity of the output signal by simply changing the voltage at the switching signal input terminal 36. In addition, the dynamic range of the output allows the output signal to rise from ground potential.
Since it changes up to the V _CC voltage, it can be set over a wide range, and the DC potential of the output terminal 13 can also be set arbitrarily. Furthermore, subtraction of two input signals can be performed simultaneously, and by changing the current ratio of the first and second current mirror circuits 17 and 18, the gain of each polarity can be set separately.

Another embodiment of the invention is shown in FIG. The same parts as in FIG. 3 are indicated by the same numbers. To note only the differences with Fig. 3, the load resistor 29 in Fig. 3 is now two load resistors 37 and 38, which are connected to the collectors of the transistors 30 and 31, respectively, and the opposite sides are commonly connected. Transistor 2 of first and second current mirror circuits 17 and 18
It is connected to collectors 4 and 27 and serves as an output terminal 13. The operation in Figure 4 is similar to the third
There is no need to explain again that it will be similar to that shown in the figure. Therefore, the circuit shown in FIG. 4 has the same effect as the embodiment shown in FIG. 3, and by changing the values of the resistors 37 and 38, the gain can be changed depending on the polarity of the output signal.

As described above, according to the present invention, in an electronic circuit for inverting the polarity of an output signal, the polarity can be easily inverted, the electronic circuit can be configured with a relatively simple circuit, and it is suitable for integration into an integrated circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit connection diagram showing a conventional example, Fig. 2 is a basic circuit configuration diagram of the present invention, Fig. 3 is a circuit connection diagram showing one embodiment of the present invention, and Fig. 4 is another embodiment of the present invention. FIG. 3 is a circuit connection diagram showing an example. 17, 18...Current mirror circuit, 19, 2
1...Switch circuit, 20...Load, 1, 2, 4
~7,14,15,23~28,30,31...
Transistor, 16, 29, 32-35, 37,
38...Resistor, 11, 12...Input terminal, 13...
...Output terminal, 10, 12...Bias source, 8, 3
6...Switching signal input terminal, 3...Current source.

Claims (1)

[Claims] 1 first and second transistors whose emitters are coupled to each other and whose bases are supplied with an input signal; and a first current mirror circuit whose input end is connected to the collector of the first transistor; a second current mirror circuit whose input terminal is connected to the collector of the second transistor; and one of the first and second current mirror circuits is operated according to a required polarity of an output signal with respect to the input signal. 1. A transistor circuit comprising: a switch circuit which sets one current mirror circuit to one state and a switch circuit which sets the other one to an inactive state, and obtains an output signal by coupling respective output terminals of the first and second current mirror circuits.