JPH0523452B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a bus in which multiple bus masters are connected by a tri-state output line driver, a transient phenomenon occurs due to the capacitance present in the bus, and the logic level of the bus changes. This prevents the change in the output impedance from being delayed from the time when the output impedance of the bus master changes.

[Industrial application field]

The present invention relates to a bus control circuit that prevents delay in operation time due to capacitance existing in a bus in a circuit in which a plurality of bus masters connected to one bus by line drivers with tristate outputs is present.

In circuits where a single bus has multiple bus masters claiming exclusive rights to the bus, such as computer circuits where multiple processors use a common bus to access memory, it is possible to save logic elements. It is common to connect the bus master of each processor to the bus using a connection method called wired coupling using a tristate output line driver, which is effective for speeding up logic and reducing power consumption.

In this case, in order to increase the speed of the device, it is necessary that when one bus master relinquishes the exclusive right to the bus, another bus master can immediately acquire the exclusive right to the bus.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional bus master connection, and FIG. 4 is a diagram explaining the operation of FIG. 3.

Bus 5 includes, for example, bus masters 2 and 3 of the processor.
is connected, and a memory 4 is connected as a load. Control signals from bus masters 2 and 3 are outputted by a tri-state output line driver, and a wired connection is established on bus 5.

Tri-state output means that the output level of a normal logic element is two voltage levels, "H" and "L", which correspond to logic "1" and "0". In addition to the two voltage levels of ” and “L”,
This is an output (circuit) that can put the output line in a state in which it is substantially disconnected (high impedance: referred to as "High Z").

A tri-state output element becomes equivalent to a normal TTL logic element when "1" is input to the enable terminal, and the output is determined by the input of the logic input terminal and the logic function of the element, and the output voltage becomes "H", “L”
At any level, the output impedance is very low (0 to several tens of ohms).

When “0” is input to the enable terminal, “High”
Z'' and the output is electrically disconnected, making them electrically and logically unrelated.

Therefore, if "0" is input to the enable terminals of all line drivers, there will be nothing to output, and the bus potential will become unstable. Therefore, the voltage of the power supply Vc is applied through the pull-up resistor 1 to set the potential to "H". use. The value of this pull-up resistor 1 cannot be set very high in view of the load capacity of the line driver, and a value of several kilohms is generally used.

Note that when wire-coupling tri-state output elements, the enable input must be set to "1" only once. This is because if two or more devices are enabled at the same time, device destruction may occur.

As mentioned above, when both bus masters 2 and 3 input "0" to the enable terminals of the line drivers and do not send signals to the bus 5, the voltage of the power supply Vc is applied to the bus 5 by the pull-up resistor 1. The voltage level of is set to "H".

Since bus masters 2 and 3 are equivalent, the operation of bus master 2 will be representatively explained using FIG. 4.

The line driver 6 of the bus master 2 is a tri-state output, and when the enable signal and logic input applied from the terminal A are both "1" as shown in FIG. 4, the output impedance is lowered to the ground potential. Therefore, current is absorbed from the bus and the output voltage level is set to "L". This causes bus master 2 to claim occupancy of the bus.

Here, when the bus master 2 completes using the bus 5, the enable signal applied from the terminal A changes from "1" to "0". line driver 6
When the enable signal changes from "1" to "0", it becomes "High Z" and the output is disconnected. Therefore, there is nothing on the bus 5 to absorb the current, the current flowing through the pull-up resistor 1 decreases, the potential rises, and the level becomes "H".

Ideally, this indicates that bus master 2's right to occupy the bus has ended, as shown in FIG. 4.

However, since there is capacitance on the bus 5 due to the stray capacitance of the circuit, a transient phenomenon occurs in which this capacitance is charged through the pull-up resistor 1, and the potential of the bus 5 gradually decreases as shown in FIG. rise to Therefore, the output B of the receiver 7 of the memory 4, which is the load on the bus 5, is at the fourth output level until the input reaches the threshold value.
As shown in FIG. 4, the timing from "1" to "0" is delayed by a time T.

[Problem that the invention seeks to solve]

As described above, in the conventional circuit, a time difference T occurs from the time when the enable signal applied from the terminal A of the bus master shown in FIG. 4 changes to the time when the receiver output B of the memory changes as shown in FIG.
When designing a bus, it is necessary to take this time difference T into consideration and create a circuit that always has time margin (for example, the delay time of the line driver is assumed to be large when designing), which becomes an obstacle to speeding up the bus. There is a problem that there is.

In view of these problems, the present invention sets the voltage level of the bus 5 to "H" with low impedance while no bus master has the right to occupy the bus, that is, while the line drivers 6 of all bus masters are "High Z". A circuit is provided to determine the time difference T, thereby preventing the occurrence of transient phenomena and eliminating the time difference T.

[Means for solving problems]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

2 to 7 are the same as in FIG. 8 is a determination circuit that determines the voltage level of bus 5; 9 is a NOR circuit that takes a NOR of the enable signals of all bus masters; and 10 is a NOR circuit that determines whether all bus masters 2 to N are occupying bus 5 by the output of NOR circuit 9. When there is no
This is a line driver that lowers the output impedance and sets the potential of the bus 5 to "H".

Although not shown in the figure, N indicates the Nth bus master.

The line driver 10 of the deterministic circuit 8 receives the NOR output of the bus master enable signal from the NOR circuit 9, and when all the bus master line drivers 6 are in "High Z", the enable terminal is set to "1" to lower the output impedance. The potential of the bus 5 is set to "H", and when any of the line drivers 6 becomes low impedance and absorbs the current of the bus 5, the output is set to "High Z".

[Effect]

As in the above configuration, due to the presence of the determining circuit 8, there is always one enabled line driver on the bus 5. Therefore, the bus 5 is always connected to ground or the power supply by a low impedance circuit, eliminating the influence of the capacitance present on the bus 5, and immediately responding to a change in the bus master's enable signal. The voltage level or logic level of bus 5 can be changed.

〔Example〕

FIG. 2 is a diagram explaining the operation of FIG. 1.

In FIG. 2, an enable signal is sent to a NOR circuit 9 of a determining circuit 8 from a terminal A that provides an enable signal to each tristate 6 of bus masters 2, 3, . . .

For example, bus master 2 is using bus 5, but when this use is completed and the enable signal is changed from "1" to "0" and input to terminal A as shown in FIG. 2, line driver 6 The output impedance of is "High Z" as shown in FIG.

At this time, since the enable signals of the bus masters 2 to N are all "0", the output of the NOR circuit 9 of the determining circuit 8 changes from "0" to "1" as shown in FIG.
Changes to Therefore, the output impedance of the line driver 10 of the deterministic circuit 8 changes from "High Z" to a low impedance, as shown in FIG. Set it to “H”.

The output impedance of the line driver 10 at this time is compared to the pull-up resistor 1 shown in FIG.
is so low that any capacitance-based transients present on bus 5 are negligible and memory 4
The output B of the receiver 7 immediately changes from "1" to "0" as shown in FIG.

Note that the output of the line driver is the logic input.
Although the explanation has been made on the assumption that the signal on the bus becomes "L" when the signal is NOT and indicates the bus master's assertion of bus occupancy, this does not necessarily have to be the case. For example, if the signal on the bus becomes "H" to indicate the bus master's assertion of bus occupancy, the determination circuit 8
Conversely, the line driver 10 may be set to "L".

〔Effect of the invention〕

As explained above, in the present invention, when one bus master relinquishes bus occupancy, other bus masters can secure bus occupancy, and the delay time caused by transient phenomena on the bus is eliminated, thereby enabling high-speed operation. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, FIG. 2 is a diagram explaining the operation of FIG. 1, and FIG.
The figure is a block diagram showing an example of a conventional bus master connection, and FIG. 4 is a diagram explaining the operation of FIG. 3. In the figure, 1 is a pull-up resistor, 2 and 3 are bus masters, 4 is a memory, 5 is a bus, 6 and 10 are line drivers with tri-state outputs, 7 is a receiver, 8 is a deterministic circuit, and 9 is a NOR circuit.

Claims (1)

[Claims] 1. In a circuit in which a plurality of bus masters 2 are connected to one bus 5 by line drivers 6 with tri-state outputs, input to the enable terminal of the line driver 6 of the bus masters 2 to A confirmation circuit 8 connected to the bus 5 by a NOR circuit 9 which inputs all enable signals to be input, and a tri-state output line driver 10 which inputs the output of the NOR circuit 9 as an enable signal to an enable terminal. A bus control circuit comprising: