JPH0523552B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention displays the images of a plurality of receivable television broadcasts simultaneously as frame-drop still images on a cathode ray tube or the like using a simple configuration using a video memory. This invention relates to a television receiver having the following configuration.

[Conventional technology]

Currently, TV broadcasting is limited to VHF stations, with 6 stations in the Osaka area and 7 stations in the Tokyo area, and even more if UHF stations are included. The only way for a viewer to actually see what kind of content these TV broadcasts are currently broadcasting is to change the TV channels in order, or to have multiple TV receivers.

[Problem that the invention seeks to solve]

As described above, with conventional television receivers, it is not possible to watch television broadcasts from multiple broadcasting stations at the same time. To achieve this purpose, many television receivers must be provided, which is uneconomical and impractical.

The present invention has been made to solve the above problems, and has a simple configuration that allows broadcasts from multiple TV stations to be displayed simultaneously, albeit in a frame-by-frame manner, by using only one tuner. When channels are displayed on multiple screens in a frame-by-frame manner, channels with no signal are skipped and displayed. For example, when each broadcast channel is preset in the channel selection position and the channel is preset when receiving and selecting a broadcast. To provide a television receiver that skips and displays positions where no signal is received or positions where there is no signal even if preset.

[Means for solving problems]

The television receiver according to the present invention has a video memory having a plurality of writing areas, each area corresponding to the video of one television broadcasting station, and samples the television video on the horizontal and vertical time axes to provide information. is thinned out, written to a buffer memory provided to solve the synchronization problem, and transferred to the video memory when the video memory is not being accessed for reading, and when the transfer of one frame is completed, the TV video is displayed. Change the broadcast to the next channel, transfer this content to the next writing area of the video memory in the same way, repeat this operation sequentially to write multi-screen information to the video memory, read it out and display it at the same time. The local synchronization signal from the local synchronization signal generator is used as the synchronization signal for writing and reading video memory, and when changing TV broadcast channels in order of tuning position, even when the channel is not preset. A signal presence/absence detecting circuit is provided for displaying positions by skipping them.

[Effect]

In this invention, in order to sequentially change the images of each television broadcast channel in a multi-screen display at regular intervals, a local synchronization signal generator is provided as a synchronization signal for reading out and displaying the video memory. At the same time, in order to perform this frame-drop display naturally, the video memory is read and written at the same time, but writing and reading must be synchronized, and a buffer memory is provided for this purpose. , the television signal is once transferred thereto according to the synchronization signal of the television broadcast signal. In addition, in order to specify the transfer destination from the buffer memory to each area provided in the video memory, an address counter whose start address value can be set is provided. Initial values are set at addresses corresponding to each area of the video memory by a vertical synchronization signal) and a horizontal synchronization signal from a local synchronization signal generator for transfer, and each time a clock signal arrives, the initial values are added in order from the set value. That will happen.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this example, one field of television video is sampled to a size of 80 pixels in the horizontal direction and 80 lines in the vertical direction (160 lines in interlace), and this is stored as nine still images, each with a different broadcast channel, in the video memory. By changing each still image at regular intervals, the contents are updated and broadcast in a frame-by-frame manner as shown in Figure 8.
It displays images from two channels.

FIG. 1 is an overall block diagram of a television receiver according to an embodiment of the present invention, FIG. 3 is a detailed block diagram of the periphery of the video memory in FIG. 1, and FIG. 4 is a detailed diagram of the timing control circuit 12 in FIG. 3. It is a diagram.

In FIG. 1, a desired channel of a television signal received by an antenna 30 is selected by a tuner 1 and transmitted to a video amplification and demodulation circuit 2. Demodulated video signal output A
is led to the video output circuit 6 via the switch circuit 4, and drives the cathode ray tube 16. On the other hand, the video signal A is also supplied to the synchronization separation circuit 3, and its outputs, vertical synchronization signal SV and horizontal synchronization signal SH, are led to the deflection circuit 7 via the switch circuit 5, and are sent to the deflection circuit 7 in a sawtooth shape for driving the deflection yoke 17. Generates wave current. Then, television images are displayed on the cathode ray tube 16. This is the configuration of a general television receiver. On the other hand, the range indicated by a broken line is a circuit portion according to the present invention.

Reference numeral 8 denotes a local synchronization signal generator, which generates a local vertical synchronization signal MV and a local horizontal synchronization signal MH, which serve as a reference for the timing of the block within the dashed line and at the same time the contents of the video memory 10 are read out. This becomes a synchronizing signal for the deflection circuit 7 when the television signal converted into an analog signal G by the D/A converter 11 is displayed on the cathode ray tube 1 through the switch 4. 14 is a microprocessor for control; push button 15; vertical synchronization signal;
MV, which has the output ID of the signal presence/absence detection circuit 39 as an input, and with the signal MV as a reference, a channel reset pulse CR that sets the channel position to the initial position, and a channel shift pulse that sequentially shifts the channel position one by one. pulse CS,
Also, the mode signal M is low level in normal TV reception mode and high level in multi-screen display mode.
(Based on this signal M, the switch circuits 4 and 5 are switched to the 1 side when it is at a low level and to the 2 side when it is at a high level.), a timing pulse T that is at a high level for one field period (1V period), and a buffer memory 18 The transfer start address P when transferring the contents of to the video memory 10 is output. Reference numeral 9 denotes an A/D converter which converts the television signal A into a digital television signal E, which is sequentially written into the buffer memory 18 and whose contents are transferred to the video memory 10. 13 is an oscillator that generates clock signals necessary for the above operations, including a horizontal synchronizing signal SH, a buffer memory writing clock synchronized with the vertical synchronizing signal SV, a clock signal CL2 used as a sampling clock for the A/D converter 9, and Buffer memory readout, transfer, and video memory 1
Local horizontal sync signal used for reading 0
MH generates a clock signal CL1 synchronized with the local vertical synchronizing signal MV. 12 is a timing control circuit that controls an address counter and each memory. Further, 15 is a display control key button, which controls the normal TV display mode and the 8th
This is to alternately change the nine-screen multi-screen display mode shown in the figure each time this is pressed.

The operation will be explained in detail below. FIG. 2 shows a flowchart of the microprocessor 14.

First, to explain the case where the key button 15 is pressed in the normal TV mode, the steps in Figure 2 will be explained.
If key 15 is input in S2, it is not the multi-screen display mode (M=1), so the process moves from step S3 to step S6.
Then, the signal M is set to a high level, that is, 1, to enter the multi-screen display mode. This signal M is sent to the video memory 1 by switching switches 4 and 5 in FIG. 1 to the 2 side.
Display the video signal from 0. Next step
At S7, a channel position reset pulse CR is output to the tuner 1 to tune the television broadcast preset to position 1, and at the same time reset the position counter configured in the RAM inside the processor 14 to 1. Subsequently, in step S8, the initial destination address P for transferring the contents of the buffer memory 18 to the video memory 10 is output in accordance with the value of the position counter. The value of P is set as the initial value of the write address counter of the video memory 10, and for each location in the multi-screen display shown in FIG. 8, for example, the values are as follows.

Screen Vertical address Horizontal address position Counter Counter 1 0 0 2 0 80 3 0 160 4 80 0 5 80 80 6 80 160 7 160 0 8 160 80 9 160 160 In other words, the video memory as a whole is horizontally 0~
239, has vertical addresses from 0 to 239,
This is because the nine images included therein are composed of 80 pixels in the horizontal direction and 80 pixels in the vertical direction, as described above.

Subsequently, the microprocessor 14 counts the MV pulses input thereto and performs a wait operation for a certain period of time. This is a step
After issuing a value change command with S7, tuner 1
This is because it takes time until a stable television signal A is output due to the response speed of the TV. This time is approximately 1 second. This time is the screen update interval when implementing the multi-screen display of the present invention. For example, if it is 1 second, it will take 1 second until the video content of position 1 is updated and the content of the next position 2 is updated. Videos on the same channel will be updated every 9 seconds. Then, in step S16, the output ID of the signal presence/absence detection circuit 39 is read, and if there is a television broadcast (if the ID is at a high level), the process moves to step S10.

Next, in step S10, a timing pulse T is generated which determines the timing of writing the digital video signal obtained by digitizing the stable video signal A into the buffer memory, and the timing of transferring it to the video memory.
occurs. This pulse is a high level signal for one field period based on the signal MV.

In other words, the video memory 10 is the local synchronization signal generator 8.
It moves in synchronization with the synchronization signals MV and MH. Therefore, the video signal E, which is completely out of synchronization with this, cannot be directly written to the video memory. If you try to write directly, the synchronization system of the video memory must be temporarily switched to the synchronization signals SH and SV on the video E side at the time of writing. However, if this is done, continuous reading from the video memory is not possible, and the display screen becomes unnatural due to irregular synchronization when writing. For this purpose, the signal E is once written into the buffer memory based on the synchronization signals SH and SV on the video signal E side. In other words, in FIG. 4, the timing pulse T is synchronized with the signal MV, but the D flip-flop 27, whose clock input is SV, receives a low level signal for this one feed period.
Generates buffer memory write control pulses synchronized with SV. During this time, one field's worth of video is written to the buffer memory. Next, two D flip-flops 28 and 29 delay the timing pulse by two field periods to generate a video memory write control pulse. This pulse is located later in time and indicates a period during which the contents written in the buffer memory while is at a low level are transferred to the video memory. Since the transfer timing is synchronized with the signal MV, it is easy to transfer using the readout free time of the video memory. With this configuration, readout and transfer are performed in parallel, allowing for natural display. Become. Then, in step S16, if there is no television signal (if ID is at low level), the timing pulse T is not output, but only the CS output for shifting to the next channel is output, and the process proceeds to step S12.

Next, the microprocessor 14 executes step S11.
outputs a channel shift pulse CS to advance to the next channel position, and also increments the position counter by one. This operation is repeated to construct nine screens as shown in FIG. Next, in step S12, the position counter is 10.
This is to reset to the initial position 1 when the display changes from 1→2→3...7→8→
It operates in such a way that it becomes 9 → 1 → 2. At the same time, step S13 functions so that the video of channel position 1 is always displayed at display position 1. After step S14, the process proceeds sequentially to steps S2→S5→S8.

Next, when key input 15 is received during the multi-screen display mode, the process advances to steps S2 → S3 → S4 and then returns to step S4.
The signal M becomes low level so that the normal TV mode is established. As a result, the switch circuits 4 and 5 are switched to the 1 side and normal television images are displayed. After this, steps S2→S5→S2 are repeated.

Next, FIG. 3, which is a detailed diagram of the periphery of the video memory within the dashed line in FIG. 1, and FIG. 4, which is an internal block diagram of the timing control circuit 12 shown in FIG. 3, will be described.

Reference numeral 22 in FIG. 3 is an address counter of the buffer memory 18. When the digital video signal E is written into the buffer memory 18, the address counter 22 functions as a write address counter.
Further, when the contents of the buffer memory 18 are transferred to the video memory, the counter 22 functions as a read address counter. The clock Q of the address counter 22 during writing is S when the switch 25 is set to the 1 side. This control is performed by the above-mentioned signal; when is at a low level, the memory is in write mode and the switch 25 is switched to the 1 side.

The signal S is composed of the following three parts. In other words, a vertical synchronization signal that resets the entire address counter.
SV, horizontal address counter dot clock CL
3 (This is the same as the sampling clock of the A/D converter and counts up to 80 in one horizontal time) and the line clock of the vertical address counter, which is the frequency of the horizontal synchronization signal SH divided by 1/3,
As a result, the video part of the TV video signal excluding the return line, which consists of 240 lines, is thinned out to 1/3, to 80 lines.

Next, 23 is a read address counter for reading out the video memory 10, and its clock K is a vertical synchronization signal MV that resets the entire counter, a horizontal address counter dot clock, and a horizontal synchronization signal that is a line clock of the vertical address counter.
It consists of MH, each counting from 0 to 239. 24 is a write address counter at the time of transfer from the buffer memory 18 to the video memory 10, and its address clock R is also used as an address counter clock at the time of reading from the buffer memory 23, and like the clock K of the address counter 23 mentioned above, it is clocked vertically. Consists of synchronization signal MV, horizontal synchronization signal MH, and dot clock.

However, the initial value of the address counter 24 is 0, 80, 80, etc. according to screen positions 1 to 9 in FIG.
160, this address counter 24 is an address counter whose initial value can be set, and the initial value of the vertical address counter is set to 0 by the vertical synchronization signal MV, and the initial value of the horizontal address counter by the horizontal synchronization signal, respectively. Set it to 80, 160 and count 80 pieces from that value.

The signal W is a read/write control signal for the video memory 10, and when it is at a low level, it is in a write mode. At this time, the switch 26 is set to the 2 side by the signal W, and the address N from the address counter 24 is supplied to the video memory 10.

Next, 20 is a serial/
The parallel converter 21 is a parallel/serial converter that uses LD as a load signal and SC2 as a shift clock.These converters perform read/write modes in parallel in the video memory 10, so the read signal F is temporally It is used to convert a non-continuous signal into a continuous signal.

The above operation is shown in the timing diagram in the fifth section.
6 and 7. FIG. 5 is a timing diagram based on the vertical synchronizing signals MV, SV and the horizontal synchronizing signals MH, SH, and shows the timing of writing to the buffer memory and transferring the contents.

As mentioned above, the signal from the timing pulse T
Control signal of length 1 field by MV and SV
BW, is generated, and while BW is at low level, the vertical address counter 22 is operated by the signal Q.
Data E for 80 lines, which is obtained by thinning one field of video to 1/3, is written to the buffer memory 18. During the period when the following signal is at a low level, the contents of the buffer memory 18 that were previously written are used as the signal.
It is transferred to the video memory 10 in synchronization with MH. During this time, the video memory 10 is constantly being read out in parallel by the address signal M.

FIG. 6 shows the timing of writing the video signal E to the buffer memory in units of dot clocks. Clock of reference oscillator 13 in FIG.
A/D with signal CL3, which is 1/3 frequency division of CL2 (5MHz)
The converter 9 is operated to generate a digital video signal E, and data for one horizontal line of 80 pixels is written by the horizontal address counter 22 which operates with the same clock. FIG. 7 shows how reading from the video memory and writing by transfer from the buffer memory are performed in parallel.

SC2 is a reference clock signal of 5MHz, and signal 19 is a signal obtained by dividing the frequency by 1/3.
, the signal R which is the write clock of the video memory 10, and the parallel/serial converter 2.
It is used as the data load pulse LD of 1.
The signal SC1 is a 20/3 MHz clock and is a shift clock for temporarily inputting the data E from the video memory 10 into the shift register 20.

The data in the shift register (serial/parallel converter) 20 is loaded into the shift register (parallel/serial converter) 21 by the signal LD, and the data is loaded into the shift register (parallel/serial converter) 21 by the shift clock SC.
2 to generate a continuous signal U. This signal U is guided to the D/A converter 11.

The signal W is obtained by dividing the frequency of the signal SC1 by 1/4, and transfer data is written into the video memory 10 while this signal is at a low level.

With the above operation, you can watch one of the many TV broadcasts.
It is possible to provide a device that allows images to be combined into two screens and viewed at the same time.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to set the video memory for storing television images of each channel, the video buffer memory for temporarily storing television signals to solve the synchronization problem, and the starting address of each area of the video memory. Since the device is configured using a write address counter, a read address counter for reading the entire video memory, and a local synchronization signal generator for synchronizing the writing and reading, there is no possibility that the display may be interrupted due to image rewriting.
It is possible to provide a multi-screen display device that has good performance and can naturally update the screen in a frame-by-frame manner without disrupting synchronization, and has the effect of allowing multi-screen display by skipping channels with no signals.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a television receiver according to an embodiment of the present invention, FIG. 2 is a flowchart of a microprocessor used in the above embodiment, and FIG. 3 is a detailed diagram of FIG. 4 is a detailed diagram of the timing control circuit 12 of FIG. 3, FIGS. 5, 6, and 7 are operation timing diagrams of the above embodiment, and FIG. 8 is a diagram showing an example of multi-screen display of the above embodiment. It is. 1 is a tuner for selecting television broadcasting, 10 is a video memory, 18 is a video buffer memory, 8 is a local synchronization signal generator, 24 is a write address counter in which a leading address can be set, 14 is a microprocessor (control means), 39 is a signal presence/absence detection circuit.

Claims (1)

[Claims] 1 means for selecting a television broadcast channel, a video main memory having a plurality of write areas, a local synchronization signal generator for oscillating a local synchronization signal, and a detection circuit for detecting the presence or absence of a television video signal and outputting a presence/absence signal. , a video buffer memory for temporarily storing television signals based on the presence/absence signal; a first address counter for writing that transfers a signal to one of a plurality of write areas of the video main memory; and a second address counter for reading that reads the entire video main memory during the transfer idle time in synchronization with the local synchronization signal. an address counter, and a transfer operation in channel order from the video buffer memory to each area of the video main memory by skipping channels with no signals of television signals of different channels for each area by controlling each of the above-mentioned elements, and What is claimed is: 1. A television receiver comprising: control means for reading out a video main memory during idle time and displaying television images from a plurality of channels simultaneously on one screen.