JPH05252017A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Object] An object of the present invention is to provide a semiconductor integrated circuit having a transfer gate circuit with improved isolation characteristics. [Configuration] Transfer gate T configuring a selector circuit
G1, TG2, ..., TGn are first and second MESFETs-Q1, Q2 connected in series to the signal path, the connection point of these first and second MESFETs-Q1, Q2 and the bias power supply VBB. Third MESFET provided between
It has Q3 and MESFET-QIN for data input. The gates of the first and second MESFETs-Q1 and Q2 are respectively connected to the first control signal .phi.1 via resistors R1 and R2.
Is connected to the signal terminal of. Third MESFET-Q
The gate of 3 is connected to the signal terminal of the second control signal / φ1 via the resistor R3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to improvement of a transfer gate which constitutes a selector used for multiplexing input data.

[0002]

2. Description of the Related Art Selector circuits for multiplexing input data are widely used in various digital arithmetic processing devices as well as in the field of data communication. A selector circuit that handles 2-input (2-bit) data is generally AND, OR
It is composed of a circuit. More simply, the selector circuit can be configured by using the transfer gate.

FIG. 4 shows a basic configuration of a 2-bit selector circuit using such a transfer gate. Transfer gates each using one field effect transistor (FET) Q01 and Q02 are connected in a wired or connection to form a selector circuit. In this basic configuration, the input / output isolation of the transfer gate is not sufficient, and the input data is superimposed on the output data.
Therefore, when the transfer gate is used in the selector circuit, how to increase the isolation between the input and the output is an important issue.

FIG. 5 shows an example of the structure of a transfer gate for a selector circuit which improves the isolation characteristic. Here, two FETs that are in series with the signal path
A transfer gate is configured by using three FETs Q1 and Q2 and an FET-Q3 for giving a predetermined bias to the connection point (Japanese Patent Publication No. 3-42017 and Japanese Patent Laid-Open No. 3-94516). See the bulletin).

In this configuration, the FET-Q connected in series is used.
Input data is transferred with 1, Q2 turned on at the same time.
At this time, the FET-Q3 is kept in the off state. When the transfer gate FETs-Q1 and Q2 are turned off, the FET-Q3 is turned on at the same time. That is, FE
When T-Q1 and Q2 are off, connect the connection point to FET-Q.
By fixing the potential with 3, the crosstalk current is discharged. As a result, the isolation characteristic is improved by about 60% as compared with the case of FIG.

However, even in the configuration of FIG. 5, the isolation is not perfect, and a slight superposition of input data can be seen at the output. This is the FET as shown in FIG.
This is because the input signal leaks to the output via the control lines through the gate capacitances Cg1 and Cg2 of -Q1 and Q2. The output notch ΔV due to leakage in one transfer gate is small, but if, for example, n transfer gates of this transfer gate are connected to form an n: 1 selector, the worst Δ
A voltage amplitude of V × n occurs. This causes a circuit malfunction.

[0007]

As described above, the conventional selector circuit using the transfer gate has a problem that the isolation characteristic is not yet sufficient.
It is an object of the present invention to provide a semiconductor integrated circuit having a transfer gate circuit with greatly improved isolation characteristics.

Another object of the present invention is to provide a semiconductor integrated circuit having a selector circuit configured by using such transfer gates having improved isolation characteristics.

[0009]

A semiconductor integrated circuit according to the present invention is connected in series to a signal path and has a first gate.
And second FET controlled by the control signal of
And a third FET which is connected between a connection point of these first and second FETs and a bias power supply and whose gate is controlled by a second control signal having a phase opposite to that of the first control signal. ,
A transfer gate having a resistor inserted between the gates of the first and second FETs and the input terminal of the first control signal is provided. The semiconductor integrated circuit according to the present invention is also characterized in that it has a selector circuit configured by connecting a plurality of transfer gates as described above in a wired-OR connection.

[0010]

According to the present invention, the leakage through the gate capacitance of the first and second FETs connected in series is greatly reduced by the resistance inserted in these gates, and the input / output isolation characteristics of the transfer gate are reduced. Is greatly improved. Further, if a plurality of transfer gates according to the present invention are wired or connected to form a selector circuit, a larger number of input data can be handled as compared with the conventional case.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a selector circuit using a transfer gate according to an embodiment of the present invention. In this embodiment, n transfer gates TG1, TG2, ..., T are provided.
A selector circuit is configured by connecting Gn in a wired or.

Each transfer gate TG1, TG2,
, TGn are the first and second GaAs MESFETs for transfer gates connected in series to the signal path.
Q1 and Q2, these first and second GaAs MESFETs
It has a third GaAs MESFET-Q3 provided between the connection point of -Q1 and Q2 and the bias power supply VBB, and a GaAs MESFET-QIN for data input. First,
The gates of the second GaAs MESFETs-Q1 and Q2 are connected to the signal terminal of the first control signal .phi.1 via resistors R1 and R2, respectively. Third GaAs MESFE
The gate of T-Q3 is connected via a resistor R3 to a signal terminal to which a second control signal / φ1 having a phase opposite to that of the first control signal φ1 enters.

Thus, the MESFE for transfer gate
By inserting resistors R1 and R2 into the gates of T-Q1 and Q2, respectively, leakage of an input signal to the output terminal via the control signal line via the gate capacitance is suppressed. Therefore, it is possible to obtain a selector circuit that does not malfunction even when the number of input data n is large.

The effect will be described with reference to specific data. MESFET-Q1, Q2, and Q3 have gate lengths of 0.
A resistor having a thickness of 5 .mu.m was used, resistors R1 and R2 were 10 k.OMEGA. Figure 2
The results of measuring the output amplitude with respect to the input amplitude of 0.9 V when the transfer gate is off in the transfer gate configuration of this embodiment shown in FIG. 2C together with the conventional example shown in FIGS. Shown in 3.

In the configuration of the embodiment shown in FIG. 2 (c), the output amplitude is reduced to about 1 mV. Therefore, the isolation characteristic is about -58 dB. Figure 2 (a) (b)
, The isolation characteristics are −23d, respectively.
B, −31 dB. That is, according to this embodiment,
The configuration is the same as that of the embodiment except that the resistor is not inserted.
Compared to the case of (b), the leak is reduced to about 1/25.

A selector circuit with the number of input data n = 50 is constructed, a 0.9V pulse is input to each input terminal with the transfer gate in the OFF state, and the output amplitude at that time is examined. In the case of the embodiment, It was about 50 mV (= -25 dB). On the other hand, when a similar selector circuit was constructed with the conventional configuration of FIG. 2 (b), the output amplitude was about 1.25 V under similar test conditions. This is the same as outputting the data. Allowable output amplitude when off is 50 m
If V is set, only the 2-bit input selector circuit can be realized in the conventional configuration of FIG. On the other hand, according to this embodiment, about 25 times as much data can be input.

Although the GaAs MESFET is used in the embodiment, the present invention is not limited to this.
It is also effective when a transfer gate is formed by using another FET such as ET or JFET. The transfer gate according to the present invention can be used not only as a selector circuit but also as a signal transfer gate for various circuits.

[0019]

As described above, according to the present invention, it is possible to obtain a transfer gate having excellent isolation characteristics by inserting a resistor in the gate of the transfer gate FET. A selector circuit that can handle input data can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a selector circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a comparison between transfer gates of a conventional example and an example.

FIG. 3 is a diagram showing a comparison between transfer gate characteristics of a conventional example and an example.

FIG. 4 is a diagram showing a conventional selector circuit.

FIG. 5 is a diagram showing a conventional improved transfer gate.

[Explanation of symbols]

 TG1, TG2, ..., TGn ... Transfer gate, Q1 ... First MESFET, Q2 ... Second MESFET, Q3 ... Third MESFET, QIN ... Data input MESFET, R1, R2, R3 ... Resistor, VBB ... Bias Power supply.

Front page continued (72) Inventor Toshiki Seshita, 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa, Ltd., Toshiba Research Institute Co., Ltd. Inside the Toshiba Research Institute

Claims (2)

[Claims] 1. A first and a second field effect transistor which are connected in series to a signal path and whose gate is controlled by a first control signal; and a connection point of the first and second field effect transistors. A third field effect transistor connected between a bias power supply and having a gate controlled by a second control signal having a phase opposite to that of the first control signal; and the first and second field effect transistors. A resistor inserted between the gate and the input terminal for the first control signal, and the semiconductor integrated circuit. 2. A semiconductor integrated circuit having a selector circuit in which a plurality of transfer gates are wired-OR connected, the transfer gates are connected in series to a signal path, and the gates are controlled by a first control signal. The first and second field effect transistors are connected between a connection point of the first and second field effect transistors and a bias power supply, and the gate of the second field effect transistor has a phase opposite to that of the first control signal. A third field effect transistor controlled by a control signal, and a resistor inserted between the gates of the first and second field effect transistors and the input terminal of the first control signal. A characteristic semiconductor integrated circuit.