JPH05257510A - Programmable controller and its control method - Google Patents

Abstract

(57) [Summary] [Object] To provide a programmable controller capable of changing a program during operation (changing during RUN) by simultaneously performing scanning and block transfer, and a control method thereof. [Structure] From state (a), through states (b) to (d), C4 and C5 in program C are sequentially transferred as indicated by arrow Y, and TR is set in state (e) during block transfer.
S including address C4 to C5 specified by register 4
By jumping over without executing the program corresponding to the amount specified by the R register 5, as shown by arrow X, A →
The scanning of B → C1 → C2 → C3 → C4 ′ → C5 ′ is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly to a RUN change technique for changing a program while the programmable controller is in operation. The present invention relates to a programmable controller suitable for use in a memory that requires a long writing time.

[0002]

2. Description of the Related Art A general configuration of a programmable controller is one in which a signal from an external device is input to an input unit and a control program stored in a program memory is output to the external device via an output unit. The arithmetic processing unit) reads the program memory and
It controls the input and output sections.

It is often difficult to stop a programmable controller that is installed in a production line and is operating because it is generally operated continuously when the operation is started. Under such circumstances, if it becomes necessary to change the contents of the sequence program due to debugging, correction of so-called mistake programs, or specification changes,
A function for changing the program while the programmable controller is operating (hereinafter, referred to as RUN change function) is required.

Conventionally, the technology of the change function during RUN is as follows.
It is disclosed in JP-A-60-229106. That is, as shown in FIG. 5, when a program A → B → C is being executed and the user wants to change the portion B, the program corresponding to the changed portion B is created in advance in the buffer memory for correction with B ′. Every time, the B part on the program memory is changed to the B'part during the RUN, and then the CPU reads and executes the sequence program (hereinafter referred to as scanning) and jumps the control as A → B ′ → C. Was to do. Hereinafter, the arrow X in the figure shows the flow of scanning.

This processing control realizes the change during RUN. However, since the program of the changed portion is formed in the modification buffer memory different from the original program memory, such a change during RUN is performed. If you repeat it often, firstly, the capacity of the necessary correction buffer memory will increase, and conversely, the unused part of the program memory will gradually increase. The influence is extremely large due to the restriction. Secondly, there is a problem that the program is patched due to the combined use of the program memory and the buffer memory, which allows a plurality of bit pattern expressions for the same program. It was

In order to solve the above two problems, R
It is possible to return the contents of the correction buffer memory to the original program memory after making the change during UN. RUN
If the size of the changed program changes before and after the mid-change and before the RUN mid-change, change the program memory during the RUN before changing the contents of the correction buffer memory back to the original program. It is necessary to perform the operation to shift the program after the part marked by the amount corresponding to the step whose size has changed. This operation is normally executed by the CPU directly transferring a program (hereinafter referred to as a block transfer) via a register of the CPU or by a DMAC (Direct Memory Access Controller).

FIGS. 6A, 6B and 6C are views showing the flow of this scanning, and FIG. 6A shows the state of the program memory before the change. For the sake of explanation, the program is divided into A, B, and C parts. (B) shows the state immediately after the portion B is changed during RUN to become B '. At this stage, B'exists in the correction buffer memory. (C) is (b)
The state in which B'on the correction buffer memory is returned to the program memory from the state of FIG. Compared to the state of (b), (c) shows that the sequence programs that do not require the correction buffer memory are arranged in the order of execution of scanning. It can be said to be an arrangement on memory.

In order to change the state of (b) to the state of (c), C on the sequence program is restored before returning B'in the correction buffer memory to the original program memory.
To the corrected memory difference, that is, R by the difference between B ′ and B.
A block transfer may be performed by changing during UN.

[0009]

However, the block transfer processing as described above generally takes time, and particularly when a low-speed memory that requires time for writing as compared with reading is used, The length of time required from the start to the end is a considerable time loss that cannot be ignored compared to the scanning time. For example, if a programmable controller operating with a scanning time of 10 ms makes a change during RUN and it takes 2 seconds to transfer the block of the above program, in general, a part of the sequence program will be duplicated in the middle of the block transfer. Therefore, scanning cannot be performed from the start to the end of the block transfer. Therefore, in this example, the programmable controller, which normally operates with a scanning time of 10 ms, is in a state in which it does not perform scanning for block transfer even for 2 seconds immediately after the change during RUN. Since this is regarded as a loss time that is unacceptable in a technical field requiring a high-speed response, it is preferable to stop the change during RUN in (b) in FIG. 6 as a result.

7 (a), (b), (c), (d),
(E) is a diagram showing that a part of the sequence program is abnormal or overlaps in the middle of block transfer. In FIG. 7, C part of the sequence program is C1, C
It is composed of 2, C3 and C4. (A) shows the state immediately before the block transfer. Considering that the entire C portion is block-transferred in the direction in which the address is large by 2 addresses, when C4 is transferred in the direction in which the address is large by 2 addresses in the state of (a), it becomes (b). When C3 is transferred from the state of (b) by 2 addresses in the direction in which the address is large, it becomes (c). After that, C2 is transferred in the same manner and C is further transferred.
(E) shows a state in which the transfer is performed up to 1. In the figure, arrow Y indicates transfer.

Here, when the steps (b) to (d), which are the intermediate stages of the block transfer, are examined in detail, the sequence program may be abnormal or overlapped in the portion Z surrounded by a bold line during the intermediate stages of the block transfer. Recognize. Therefore, the Z portion is a problem, and for this reason, scanning cannot be performed during the block transfer.

According to the present invention, even if scanning is performed during the block transfer of the sequence program,
An object of the present invention is to provide a programmable controller that executes a sequence program in a normal state and a control method thereof.

[0013]

In order to achieve the above-mentioned object, a CP constituting a programmable controller
When U has a means for monitoring an address signal for accessing the program memory, and by this monitoring, it is detected that the CPU has reached the address (address L) previously set in the first register, CPU is second
Block is provided by using a programmable controller that does not execute a specified range between addresses L and L + n on the program memory by providing a means for adding the offset value n set in the register of the CPU to the program counter of the CPU. By applying the range of the sequence program that the CPU does not execute to the abnormal or overlapping portion of the sequence program that occurs in the middle of the transfer, the sequence program can be correctly executed even if scanning is performed during the block transfer. This is possible by performing both scanning and block transfer while shifting the address L where the CPU does not execute processing from the address L + n. That is, the first aspect of the present invention is
An input unit that takes in signals from an external device, an output unit that drives the external device, a program memory that stores a control program, a CPU that executes calculations according to the control program, and a control program that is sequentially read from the program memory. In a programmable controller which is repeatedly executed by a CPU, a means for monitoring an address signal output from a CPU inside the programmable controller, a means for rewriting a program counter of the CPU, and a control for executing an instruction in a designated section of a sequence program It is a programmable controller characterized by having a means. A second aspect of the invention is that a signal from an external device is input to an input unit, an external device is driven by an output unit, a control program is stored in a program memory, and a CPU is operated according to the control program.
Is a programmable program that executes arithmetic operations and sequentially reads control programs from the program memory and repeatedly executes them.
In the controller control method, the scanning of the sequence program and the so-called block transfer in which the CPU directly transfers the program are simultaneously performed, which is a control method of the programmable controller.

[0014]

1 is a block diagram of a programmable controller according to the present invention, in which a CPU 1 designates an address on a program memory 2 by an address signal placed on an address bus 7, and a sequence is performed through a data bus 8. Read the program. The address bus 7 output from the CPU 1 is also connected to the address monitoring unit 3, and the address signal output by the CPU 1 is constantly compared with the value stored in the first register 4 inside the address monitoring unit 3. be able to.

When the CPU 1 tries to read the address L on the program memory 2, the address signal L is sent to the address bus 7.
When the address is output, the address monitoring unit 3 detects that the address L matches the value L of the first register 4 designating the beginning of the range, and transmits a match signal to the CPU 1 through the match signal line 9 connected to the CPU 1. The CPU 1 interprets this coincidence signal as an addition instruction of the program counter 6 in the CPU 1, and the value n stored in the second register 5 designating the size of the range in the CPU 1 is added to the program counter 6. As a result, the CPU 1 issues the next execution instruction L +
It is carried out in order from the address n.

With the above-described mechanism, the CPU 1 can perform scanning by skipping the instruction at the address L + n from the address L designated by the first register 4. Note that these two registers can be rewritten by the CPU 1.

[0017]

FIG. 2 is a diagram showing an algorithm of one embodiment in which a sequence program is gradually transferred in blocks while scanning is performed using a programmable controller capable of skipping a designated range on a program memory for scanning. In the figure, the arrow X indicates the flow of scanning, and the CPU selects the second register from the address indicated by the first register, that is, the range head designating register 4 (hereinafter abbreviated as TR4) of the embodiment. It has a function of not executing the sequence program corresponding to the range of the address indicated by the register, that is, the range size designation register 5 (hereinafter abbreviated as SR5) of the embodiment.
Arrow Y indicates transfer. In addition, "'" is added to the transfer destination data.
Add a symbol to distinguish it from the source data. Also, in FIG.
It is a figure which shows the main flow of the Example shown in FIG. This embodiment will be described with reference to FIGS.

In FIG. 2, in the state (a), the first scanning follows the arrow X and is A → B → C1 → C2 → C.
It is executed in the order of 3 → C4 → C5. In the state (b), C5 is transferred to the address separated by the address n as shown by the arrow Y. In state (c), C5 is not executed because TR4 specifies C5, but since the content of SR5 is n, C5 'transferred to the address n apart in state (b) instead of C5 is Executed. Therefore, the execution order of the second scanning is A → B → C1 → C2 → C3 → C4 → C5 ′. In the state (d), C4 is transferred to the address n addresses away. In state (e), when the value of TR4 is decremented (decremented by 1), TR4 specifies C4.
Although C4 and C5 after C4 are not executed, since the contents of SR5 are n, C4 'and C5' at addresses n apart are executed instead of C4 and C5. After that, by repeating the same operation, the first scanning A → B → C1 → C2 → C3 → C
4 → C5 2nd scanning A → B → C1 → C2 → C3 → C
4 → C5 ′ 3rd scanning A → B → C1 → C2 → C3 → C
4 '→ C5' 4th scanning A → B → C1 → C2 → C3 '→
C4 ′ → C5 ′ 5th scanning A → B → C1 → C2 ′ → C3 ′
→ C4 '→ C5' 6th scanning A → B → C1 '→ C2' → C
Scanning is executed in the order of 3 '→ C4' → C5 ', and the scanning of the C portion is sequentially changed to execute the instructions after the block transfer.

In the description of FIG. 2, the transfer is performed once for each scanning, but generally, if the scanning cycle of the programmable controller is within a range in which the reduction of the scanning cycle is allowed, a plurality of transfers are performed for one scanning. It is possible to do it once.

In the description of FIG. 2, the C portion is block-transferred in the direction of the larger address, but in order to block-transfer the C portion in the direction of the smaller address, the transfer is started from C1 and the TR register is transferred each time. By incrementing (adding 1) the contents of 4, the same operation as in FIG. 2 can be executed.

Generally, if the CPU 1 has a function of not executing the sequence program in the designated range, this algorithm can be applied.

As a configuration of the CPU 1, there is also a programmable controller which skips an instruction from an address L designated by the first register to an address n designated by the second register for scanning. this is,
In FIG. 1, the value of SR5 is n, and when the CPU 1 receives the coincidence signal, the value n of SR5 may be transferred to the program counter 6 without being added.

FIG. 4 is a diagram showing the configuration of a programmable controller according to an embodiment of the present invention. The schematic configuration of the programmable controller in FIG.
1, the program memory 2, and the address monitoring unit 3, and the match signal line 9 extending from the address monitoring unit 3 is C
This embodiment shows one embodiment of the configuration of the CPU 1 and the address monitoring unit 3, which is connected to the PU 1.
It has the same configuration as that shown in FIG. The inside of the CPU 1 is composed of the microprocessor 10 and its peripheral circuits. The microprocessor 10 specifies an address on the program memory 2 by an address signal placed on the address bus 7, and reads out and executes the sequence program through the data bus 8. Since the data selector 11 on the data bus 8 normally selects the data bus 8 on the program memory 2 side, the microprocessor 1
0 reads out and executes the sequence program on the program memory 2 through the data bus 8. That is, scanning can be performed.

When the CPU 1 outputs the address signal L to the address bus 7 in an attempt to read the instruction at the address L on the program memory 2, the address signal is sent to the digital comparator 13 inside the address monitoring unit 3.
Since it is also input to, and is always compared with the value L of TR4, the match signal is transmitted to the CPU 1 through the match signal line 9. The match signal line 9 is connected to the selection input terminal of the data selector 11 inside the CPU 1 and only when the match signal is input, the bit pattern of the operation code of the relative jump instruction based on the current value of the program counter is stored. Jump opcode ROM 12
And the value n of SR5 are selected and loaded into the microprocessor 10. Therefore, when the microprocessor 10 tries to read the instruction at the address L on the program memory 2, it is given the instruction JUMPn instead of the instruction on the program memory 2, and as a result, the microprocessor 10 sets the program counter to L + n. To the value of. That is, it means jumping from the address L to the address L + n. TR4, SR by the above mechanism
It is possible to realize a programmable controller that does not execute the range of addresses L to L + n for the values L and n set to 5.

Further, in FIG. 4, if the bit pattern of the absolute address jump instruction is stored in the jump operation code ROM 12, it is possible to realize a programmable controller which does not execute the range from L address to n address.

If the method of alternately repeating scanning and transfer shown in FIG. 2 is applied to the programmable controller, it is possible to execute the block transfer necessary for the processing after the change during RUN while performing the scanning. It is possible.

According to the above-described embodiment, the CPU 1 that can correctly execute the program even if the block transfer is performed while performing the scanning is constructed, and the algorithm using the CPU 1 can be presented.

[0028]

According to the present invention, since the contents of the correction buffer memory can be returned to the original program memory after the change during RUN, the correction buffer memory does not increase even if the change during RUN is performed. .. Further, since scanning can be performed even during block transfer, it is extremely useful especially when performing change during RUN by a programmable controller using a low-speed memory as a program memory, which requires a long time for writing.

[Brief description of drawings]

FIG. 1 is a block diagram of a programmable controller of the present invention.

FIG. 2 is a diagram illustrating an algorithm of an embodiment of the present invention.

FIG. 3 is a diagram showing a main flow of the embodiment shown in FIG.

FIG. 4 is a diagram showing a configuration of a programmable controller according to an embodiment of the present invention.

FIG. 5 is a processing diagram showing a change in a RUN of a program in the related art and not returning the changed part of the program to the original program memory.

FIG. 6 is a processing diagram showing a change during RUN of a program in the related art and returning the changed part of the program to the original program memory.

FIG. 7 is a processing diagram showing a change during RUN of a program in the related art, and a part of the sequence program is abnormal or overlaps during block transfer.

[Explanation of symbols]

1 ... CPU 2 ... Program memory 3 ... Address monitoring unit 4 ... Range start designation register (TR) 5 ... Range size designation register (SR) 6 ... Program counter 7 ... Address bus 8 ... Data bus 9 ... Match signal line 10 ... Micro Processor 11 ... Data selector 12 ... Jump opcode ROM 13 ... Digital comparator

Claims (2)

[Claims] 1. An input unit for receiving a signal from an external device, an output unit for driving the external device, a program memory for storing a control program, a CPU for executing an operation according to the control program, and a program memory. In a programmable controller that sequentially reads out a control program and repeatedly executes the control program, means for monitoring an address signal output by a CPU inside the programmable controller, means for rewriting a program counter of the CPU, and instructions for a specified section of a sequence program A programmable controller having control means for skipping execution. 2. A signal from an external device is taken into an input part, an external device is driven at an output part, a control program is stored in a program memory, a CPU executes an operation in accordance with the control program, and the program is stored in the program memory. In a control method of a programmable controller that sequentially reads a control program and repeatedly executes the same, the scanning of a sequence program and the CPU
A method for controlling a programmable controller, characterized in that a program is directly transferred, that is, a so-called block transfer is simultaneously performed.