JPH0526360B2 - - Google Patents
Info
- Publication number
- JPH0526360B2 JPH0526360B2 JP58169874A JP16987483A JPH0526360B2 JP H0526360 B2 JPH0526360 B2 JP H0526360B2 JP 58169874 A JP58169874 A JP 58169874A JP 16987483 A JP16987483 A JP 16987483A JP H0526360 B2 JPH0526360 B2 JP H0526360B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- solder
- insulating layer
- electrode
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Die Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、ハイブリツトICの厚膜印刷基板に
係り、特に導体パターン上に半田付けされる部品
の位置精度を向上させるため等に用いられる絶縁
層に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a thick film printed circuit board for a hybrid IC, and in particular to an insulating layer used to improve the positional accuracy of components soldered onto a conductor pattern. Regarding.
厚膜印刷基板の導体パターン上にコンデンサ等
の電子部品、あるいはリード等の機構部品の半田
付けを行なう場合、部品の幅より広い幅の導体パ
ターンに半田付けする時、部品が半田の拡がりに
より動いてしまい、所望の位置に固定することが
困難である。従来、そして対策として、予め部品
が固定される位置を囲むように導体パターンの一
部又はその近傍に、ガラスあるいはエポキシ樹脂
等の絶縁層を印刷形成することにより、部品の移
動を阻止することが行われている。これにより、
所望の位置に精度良く、また再現性良く半田付け
を行なうことができるものである。第1図及び第
2図はその具体的な構成を示すものである。すな
わち、同図において、1はセラミツク基板であ
り、このセラミツク基板1上に導体パターン2が
形成されている。この導体パターン2の部品が半
田付けされる個所の近傍には直線状の絶縁層3、
あるいは枠状の絶縁層4が印刷形成されている。
そして、このセラミツク基板1上に溶接電極5、
ボンデイング電極6及び半導体ペレツト7が半田
8付けされる。このような方法で半田付けを行な
うと、絶縁層3,4により半田8の拡がりが阻止
され、部品の位置精度が向上する。
When soldering electronic components such as capacitors or mechanical components such as leads onto the conductor pattern of a thick film printed circuit board, when soldering to a conductor pattern that is wider than the width of the component, the component may move due to the spread of the solder. This makes it difficult to fix it in the desired position. Conventionally, as a countermeasure, it has been possible to prevent the movement of parts by printing an insulating layer such as glass or epoxy resin on a part of the conductor pattern or in the vicinity of the conductor pattern so as to surround the position where the part is fixed. It is being done. This results in
It is possible to perform soldering at a desired position with high precision and high reproducibility. FIG. 1 and FIG. 2 show the specific configuration thereof. That is, in the figure, 1 is a ceramic substrate, and a conductor pattern 2 is formed on this ceramic substrate 1. A linear insulating layer 3,
Alternatively, the frame-shaped insulating layer 4 is formed by printing.
Then, on this ceramic substrate 1, a welding electrode 5,
Bonding electrode 6 and semiconductor pellet 7 are soldered 8. When soldering is performed in this manner, the insulating layers 3 and 4 prevent the solder 8 from spreading, improving the positional accuracy of the components.
しかしながら、このような従来の方法にあつて
は、半田8の拡がりが阻止される結果、第3図に
示すように、半田8の裾引き角度(フイレツト角
度)θは大きくなる。このような裾引き角度の大
きな厚膜印刷基板に熱衝撃試験を行ない、例えば
温度条件を低温(−40℃)から高温(150℃)に
交互に変化させると、セラミツク基板1と半田8
との熱膨張係数の違いにより歪が生じ、第4図に
示すように絶縁層3と半田8との界面下の導体パ
ターン2にクラツク9が生じる。このようにクラ
ツク9が生じると導体パターン2の抵抗値が増大
し、さらにクラツクが進むと導体パターン2が断
線することもある。第5図は裾引き角度と熱衝撃
サイクルによるクラツクの発生状況を示すもので
ある。同図において、aは裾引き角度が大の場
合、bは裾引き角度が小の場合を示すもので、後
者の方が前者よりもクラツク発生率は低い。
However, in such a conventional method, as a result of preventing the solder 8 from spreading, the fillet angle θ of the solder 8 becomes large, as shown in FIG. When performing a thermal shock test on such a thick film printed circuit board with a large hem angle, for example, when the temperature conditions were alternately changed from low temperature (-40℃) to high temperature (150℃), the ceramic substrate 1 and solder 8
Distortion occurs due to the difference in coefficient of thermal expansion between the insulating layer 3 and the solder 8, and as shown in FIG. When the crack 9 occurs in this manner, the resistance value of the conductor pattern 2 increases, and if the crack progresses further, the conductor pattern 2 may become disconnected. FIG. 5 shows the occurrence of cracks due to the skirting angle and thermal shock cycle. In the figure, a shows a case where the hemline angle is large, and b shows a case where the hemline angle is small, and the crack occurrence rate is lower in the latter case than in the former case.
本発明は上記実情に鑑みてなされたもので、そ
の目的は、半田の裾引き角度が小さく、導体パタ
ーンのクラツク発生を低減でき、導体パターンの
抵抗値の変動および断線等の発生を防止し得る厚
膜印刷基板を提供することにある。
The present invention has been made in view of the above circumstances, and its purpose is to reduce the hem angle of the solder, reduce the occurrence of cracks in the conductor pattern, and prevent the occurrence of fluctuations in the resistance value of the conductor pattern and the occurrence of wire breaks. The purpose of the present invention is to provide a thick film printed substrate.
本発明は、基板と、この基板上に形成された抵
抗値を有する導体パターンと、この導体パターン
上に離間して半田付けされた第1の電極および第
2の電極とを具備した厚膜印刷基板において、前
記第1、第2の電極の近傍に前記導体パターン上
を横断するように第1、第2の絶縁層を設けると
ともに、これら第1、第2の絶縁層それぞれに、
半田が裾を引いて塞止される幅を有する間〓を複
数設け、第1、第2の電極相互間の導体パターン
を導体抵抗として用いることを特徴とする。
The present invention provides thick film printing comprising a substrate, a conductor pattern having a resistance value formed on the substrate, and a first electrode and a second electrode soldered to the conductor pattern in a spaced manner. In the substrate, first and second insulating layers are provided near the first and second electrodes so as to cross over the conductor pattern, and each of the first and second insulating layers includes:
The present invention is characterized in that a plurality of gaps having a width that can be closed by drawing the hem of the solder is provided, and a conductor pattern between the first and second electrodes is used as a conductor resistance.
上記構成の厚膜印刷記板によれば、絶縁層に設
けられた間〓より半田の一部を裾を引かせて逃が
すことができ、この部分において半田の裾引き角
度を小さくできる。これによつて間〓下の導体パ
ターンにあつてはクラツクの発生が低減される。 According to the thick-film printing board having the above structure, a part of the solder can be drawn and released from the gap provided in the insulating layer, and the angle of the solder in this part can be made small. This reduces the occurrence of cracks in the underlying conductor pattern.
また、上記間〓が複数設けられることにより、
導体パターンにクラツクが入り難い個所を複数設
けられる。このため、絶縁層近傍の導体パターン
にクラツクが発生した場合においても、第1の電
極および第2の電極と導体パターンとの導通が、
いわば並列接続の抵抗によつて維持される。従つ
て、第1、第2の電極どうしを接続する導体パタ
ーンの抵抗値の変動を小さくできる。また、クラ
ツクの入り難い箇所の一つに、たとえクラツクが
入つたとしても、この他の箇所が導通状態を保持
するため、装置の寿命を延長できる。 In addition, by providing multiple spaces between the above,
Multiple locations where cracks are difficult to form can be provided in the conductor pattern. Therefore, even if a crack occurs in the conductor pattern near the insulating layer, the conduction between the first electrode and the second electrode and the conductor pattern is maintained.
It is maintained, so to speak, by resistors connected in parallel. Therefore, fluctuations in the resistance value of the conductor pattern connecting the first and second electrodes can be reduced. Further, even if a crack occurs in one of the difficult-to-reach locations, the other locations remain conductive, thereby extending the life of the device.
また、第1、第2の電極相互間の導体パターン
が導体抵抗として用いられることにより、回路を
構成する部品の点数を削減でき、また極小抵抗値
の抵抗を得ることが可能となる。さらに、上記間
〓が半田が裾を引いて塞止される幅を有するた
め、間〓からの半田の流失が防止され、半田によ
る上記導体抵抗の抵抗値変動も防止できる。 Furthermore, by using the conductor pattern between the first and second electrodes as a conductor resistance, it is possible to reduce the number of parts constituting the circuit and to obtain a resistor with a minimum resistance value. Furthermore, since the gap has a width that is covered by the solder, it is possible to prevent the solder from flowing out from the gap, and also to prevent variations in the resistance value of the conductor resistor due to the solder.
以下、図面を参照して本発明の一実施例を説明
する。第6図は、本発明を低抵抗(1Ω以下)を
必要とする導体抵抗を使用した厚膜印刷基板に適
用した例を示すものである。同図において、11
はセラミツク基板であり、このセラミツク基板1
1上にはAgPdの厚膜により形成された導体パタ
ーン12が形成されている。この導体パターン1
2の部品が半田付けされる個所の近傍には、例え
ばガラスで形成され、導体パターン12を横断す
る直線状の絶縁層13,13、及び枠状の絶縁層
14がそれぞれ印刷されている。これら絶縁層1
3,13,14にはそれぞれ当該絶縁層を横切る
ような複数の間〓15,15……が設けられてい
る。しかして、導体パターン12上の所定の位置
には、溶接電極16,16、ボンデイング電極1
7及び半導体ペレツト18が半田19付けされて
いる。ボンデイング電極17と半導体ペレツト1
8の電極との間はボンデイングワイヤ20により
接続されている。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows an example in which the present invention is applied to a thick film printed board using a conductor resistor that requires low resistance (1Ω or less). In the same figure, 11
is a ceramic substrate, and this ceramic substrate 1
A conductor pattern 12 made of a thick film of AgPd is formed on the conductor pattern 1 . This conductor pattern 1
In the vicinity of the location where the second component is soldered, linear insulating layers 13, 13 and a frame-shaped insulating layer 14 made of, for example, glass and crossing the conductor pattern 12 are printed. These insulating layers 1
3, 13, 14 are provided with a plurality of gaps 15, 15, . . . that cross the insulating layer, respectively. Therefore, at predetermined positions on the conductor pattern 12, welding electrodes 16, 16, bonding electrodes 1
7 and semiconductor pellets 18 are soldered 19. Bonding electrode 17 and semiconductor pellet 1
A bonding wire 20 is used to connect the electrode 8 to the electrode 8 .
上記厚膜印刷基板においては、溶接電極16及
びボンデイング電極17の部品を半田付ける場
合、絶縁層13,14により半田19の大部分の
拡がりが阻止されるため、従来と同様に、部品の
所望の位置に精度良く固定することができる。ま
た、この半田19はその一部が絶縁層13,14
の各間〓15部に流れ込む。その結果、半田19
の裾引き角度は従来の厚膜印刷基板に比べ、大幅
に小さくなる。従つて、絶縁層13,14と半田
19との界面下の導体パターン12へのクラツク
の発生が減少し、これにより、導体パターン12
の抵抗値の変化を阻止することができ、また断線
等の事故発生を防止できる。第8図は、熱衝撃試
験(−40℃、30分←→150℃、30分)による部品間
導体抵抗の変化状態を、従来例と本発明との厚膜
印刷基板を比較して示すものである。同図におい
て、cは従来例の場合、dは本発明の場合をそれ
ぞれ示すもので、1000サイクルの時点では、前者
の抵抗変化率の変化が約3%の増加であるのに対
し、後者は約1%弱の増加と大幅に少なくなる。 In the above-mentioned thick film printed circuit board, when soldering the welding electrode 16 and bonding electrode 17, most of the solder 19 is prevented from spreading by the insulating layers 13 and 14. It can be fixed in position with high precision. Further, a part of this solder 19 is insulating layers 13 and 14.
Flows into 15 parts between each time. As a result, Handa 19
The skirting angle is significantly smaller than that of conventional thick-film printed circuit boards. Therefore, the occurrence of cracks in the conductive pattern 12 under the interface between the insulating layers 13 and 14 and the solder 19 is reduced, and as a result, the occurrence of cracks in the conductive pattern 12 is reduced.
It is possible to prevent changes in the resistance value of the wire, and also prevent accidents such as wire breakage. Figure 8 shows the changes in conductor resistance between parts during a thermal shock test (-40°C, 30 minutes ← → 150°C, 30 minutes), comparing thick film printed circuit boards of the conventional example and the present invention. It is. In the figure, c indicates the conventional example, and d indicates the present invention. At 1000 cycles, the change in resistance change rate for the former is approximately 3% increase, while for the latter. This will be a significantly smaller increase of just under 1%.
上記実施例においては、間〓15を、半田付け
する部品の位置精度を向上させるための絶縁層1
3,14に設ける場合について説明したが、隣接
する部品間を仕切るための絶縁層、例えば第9図
に示すようなコンデンサ21と溶接電極22との
間に設けられた絶縁層23に設けるようにしても
よく、この場合も上記実施例と同様の効果が得ら
れる。 In the above embodiment, the gap 15 is replaced by the insulating layer 1 for improving the positional accuracy of the parts to be soldered.
3 and 14, but it may also be provided on an insulating layer for partitioning adjacent parts, for example, an insulating layer 23 provided between a capacitor 21 and a welding electrode 22 as shown in FIG. In this case as well, the same effect as in the above embodiment can be obtained.
尚、上記間〓の幅及び数は任意であるが、導体
パターンの幅が狭い場合には、間〓の合計幅が導
体幅の30〜70%程度が望ましい。 The width and number of the gaps are arbitrary, but when the width of the conductor pattern is narrow, it is desirable that the total width of the gaps is about 30 to 70% of the conductor width.
以上のように本発明によれば、半田付けされる
部品の近傍に導体パターンを横断する絶縁層を有
する厚膜印刷基板において、部品の位置精度を低
下させることなく、半田の裾引き角度を小さくす
ることができる。従つて、導体パターンのクラツ
ク発生を防止できると共に、導体抵抗の変化を低
減でき、信頼性が著しく著しく向上する。
As described above, according to the present invention, in a thick film printed circuit board having an insulating layer that crosses a conductor pattern near the components to be soldered, the hem angle of the solder can be reduced without reducing the positional accuracy of the components. can do. Therefore, it is possible to prevent the occurrence of cracks in the conductor pattern, reduce changes in conductor resistance, and significantly improve reliability.
第1図は従来の厚膜印刷基板の構成を示す平面
図、第2図は第1図のA−A′線に沿つた断面図、
第3図は第2図の要部を拡大して示す断面図、第
4図は導体パターンへのクラツクの発生状態を示
す断面図、第5図は半田の裾引き角度と熱衝撃サ
イクルによるクラツクの発生状況を示す図、第6
図は本発明の一実施例を係る厚膜印刷基板の構成
を示す平面図、第7図は第6図のB−B′線に沿
つた断面図、第8図に熱衝撃サイクルに対する抵
抗変化率の変化状態を従来と本発明とを比較して
示す図、第9図は本発明の他の実施例に係る平面
図である。
11……セラミツク基板、12……導体パター
ン、13,14……絶縁層、15……間〓、16
……溶接電極、17……ボンデイング電極、18
……半導体ペレツト。
Fig. 1 is a plan view showing the structure of a conventional thick film printed circuit board, Fig. 2 is a cross-sectional view taken along line A-A' in Fig. 1,
Figure 3 is an enlarged cross-sectional view of the main part of Figure 2, Figure 4 is a cross-sectional view showing how cracks occur in the conductor pattern, and Figure 5 shows cracks caused by the solder skirting angle and thermal shock cycle. Diagram showing the occurrence situation, Part 6
The figure is a plan view showing the structure of a thick film printed circuit board according to an embodiment of the present invention, FIG. 7 is a sectional view taken along line B-B' in FIG. 6, and FIG. 8 is a change in resistance against thermal shock cycles. FIG. 9 is a diagram illustrating a comparison between the conventional method and the present invention in terms of rate change, and FIG. 9 is a plan view according to another embodiment of the present invention. 11... Ceramic substrate, 12... Conductor pattern, 13, 14... Insulating layer, 15... Interval, 16
... Welding electrode, 17 ... Bonding electrode, 18
...Semiconductor pellets.
Claims (1)
する導体パターンと、この導体パターン上に離間
して半田付けされた第1の電極および第2の電極
と、これら第1、第2の電極の近傍で前記導体パ
ターン上を横断するように形成された第1、第2
の絶縁層とを具備し、前記第1、第2の絶縁層そ
れぞれに、半田が裾を引いて塞止される幅を有す
る間〓を複数設け、前記第1、第2の電極相互間
の導体パターンを導体抵抗として用いることを特
徴とする厚膜印刷基板。1. A substrate, a conductor pattern having a resistance value formed on this substrate, a first electrode and a second electrode soldered to the conductor pattern in a spaced manner, and these first and second electrodes. first and second conductor patterns formed to cross over the conductor pattern in the vicinity of
an insulating layer, and each of the first and second insulating layers is provided with a plurality of gaps having a width such that the solder can be closed by pulling the hem thereof, and a gap between the first and second electrodes is provided. A thick film printed circuit board characterized by using a conductive pattern as a conductive resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169874A JPS6062190A (en) | 1983-09-14 | 1983-09-14 | Thin film printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169874A JPS6062190A (en) | 1983-09-14 | 1983-09-14 | Thin film printed board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6062190A JPS6062190A (en) | 1985-04-10 |
| JPH0526360B2 true JPH0526360B2 (en) | 1993-04-15 |
Family
ID=15894553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58169874A Granted JPS6062190A (en) | 1983-09-14 | 1983-09-14 | Thin film printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6062190A (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365973A (en) * | 1976-11-25 | 1978-06-12 | Mitsubishi Electric Corp | Method of producing hyb ic |
| JPS54101162A (en) * | 1978-01-26 | 1979-08-09 | Nippon Electric Co | Circuit board |
| JPS57192100A (en) * | 1981-05-22 | 1982-11-26 | Hitachi Ltd | Hybrid ic |
-
1983
- 1983-09-14 JP JP58169874A patent/JPS6062190A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6062190A (en) | 1985-04-10 |
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