JPS6062190A - Thin film printed board - Google Patents
Thin film printed boardInfo
- Publication number
- JPS6062190A JPS6062190A JP58169874A JP16987483A JPS6062190A JP S6062190 A JPS6062190 A JP S6062190A JP 58169874 A JP58169874 A JP 58169874A JP 16987483 A JP16987483 A JP 16987483A JP S6062190 A JPS6062190 A JP S6062190A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- film printed
- insulating layer
- thick film
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Die Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明に、ハイブリツ)IC用の厚膜印刷基板に係り、
特に導体パターン上に半田付けされる部品の位置a度乞
向上させるため弄に用いられる絶縁層に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a thick film printed substrate for hybrid IC,
In particular, the present invention relates to an insulating layer used to improve the position of components soldered onto a conductor pattern.
厚膜印刷基板の導体パターン上にコンデンサ等の電子部
品、おるいはリード等の機構部品の半田付は7行なう場
合、部品の幅より広い幅の導体パターンに半田付けする
時、部品が半田の拡が9により動いてしまい、所望の位
置に固定することが困難である。従来、その対策として
、予め部品が固定される位置を囲むように導体パターン
の一部又はその近傍に、ガラスあるいはエポキシ樹脂等
の絶縁層を印刷形成1−ることにより、部品の移動を阻
止することが行われている。これによシ、所望の位置に
精度良く、また再現性良く半田付け2行なうことができ
るものである。第1図及び第2図はその具体的な構成2
示すものである。丁なわち1.同図において、1rs、
セラミック基板でラシ、このセラミック基板1土に導体
パターン2が形成されている。Oの導体パターン2の部
品が半田付けされる個所の近傍には直線状の絶縁層3、
あるいは枠状の絶縁層4が印刷形成されている。そして
、このセラミック基板1上に溶接電極5、ボンディング
電極6及び半導体ペレット7が半田8付けされる。この
ような方法で半田付けを行なうと、絶縁層3,4によシ
半田8の拡が9が阻止され\部品の位置精度が向上する
。When soldering electronic components such as capacitors, or mechanical components such as leads, on the conductor pattern of a thick film printed circuit board, when soldering to a conductor pattern that is wider than the width of the component, the component may be soldered. The expansion moves due to 9, making it difficult to fix it at the desired position. Conventionally, as a countermeasure, an insulating layer of glass or epoxy resin is printed in advance on a part of the conductor pattern or in the vicinity of the conductor pattern so as to surround the position where the component is fixed, thereby preventing the component from moving. things are being done. This makes it possible to perform two soldering operations at desired positions with high precision and high reproducibility. Figures 1 and 2 show the specific configuration 2.
It shows. 1. In the same figure, 1rs,
A ceramic substrate is used, and a conductive pattern 2 is formed on the ceramic substrate 1. A linear insulating layer 3 is placed near the location where the O conductor pattern 2 components are soldered.
Alternatively, the frame-shaped insulating layer 4 is formed by printing. Then, a welding electrode 5, a bonding electrode 6, and a semiconductor pellet 7 are soldered 8 onto this ceramic substrate 1. When soldering is performed in this manner, the insulating layers 3 and 4 prevent the solder 8 from spreading 9, thereby improving the positional accuracy of the parts.
しかしながら、このような従来の方法にあっては、半田
8の拡が9が阻止される結果、第3図に示すように、半
田8の裾引き角度(フィレット角度)θは大きくなる。However, in such a conventional method, as a result of preventing the spread 9 of the solder 8, the skirting angle (fillet angle) θ of the solder 8 becomes large, as shown in FIG.
このような裾引き角度の大きな厚膜印刷基板に熱衝撃試
j、険乞行ない、例えば温度条件乞低温(−40℃)か
ら高温(150℃)に交互に変化させると、セラミック
基板1と半田8との熱膨張係数の違いにより歪が生じ、
第4図に示すように絶縁1@i3と半田8との界面下の
導体パターン2にクラック9が生じる。このようにクラ
ック9が生じると導体パターン2の抵抗値が増大し、さ
らにクランクが進むと導体パターン2が断線することも
ある。When such a thick film printed circuit board with a large skirting angle is subjected to a thermal shock test, for example, when the temperature condition is alternately changed from low temperature (-40℃) to high temperature (150℃), the ceramic substrate 1 and the solder Distortion occurs due to the difference in thermal expansion coefficient between
As shown in FIG. 4, cracks 9 occur in the conductor pattern 2 under the interface between the insulation 1@i3 and the solder 8. When the crack 9 occurs in this manner, the resistance value of the conductor pattern 2 increases, and if the crank advances further, the conductor pattern 2 may become disconnected.
第5図は裾引き角度と熱衝系サイクルによるクラックの
発生状況乞示すものである。同図において、al”l:
裾引き角度が大の場合、bは裾引き角度が小の場合を示
すもので、後者の方が前者よりもクラック発生率は低い
。FIG. 5 shows the occurrence of cracks due to the skirting angle and thermal shock cycle. In the same figure, al”l:
When the skirting angle is large, b indicates the case where the skirting angle is small, and the crack occurrence rate is lower in the latter than in the former.
本発明は上記実情に鑑みてなされたもので、その目的は
、半田の裾引き角度が小さく、導体パターンのクラック
発生を低減でき、断線等の発生を防止し得る厚膜印刷基
板を提供することにある。The present invention has been made in view of the above circumstances, and its purpose is to provide a thick film printed circuit board that has a small hem angle of solder, can reduce the occurrence of cracks in the conductor pattern, and can prevent the occurrence of disconnections, etc. It is in.
本発明は、基板と、この基板上に形成された導体パター
ンと、この導体パターン上に半田付けされる部品の近傍
で、前記導体パターン上を横断するように形成された絶
縁層とを具備した厚膜印刷基板において、前記絶縁層に
当該絶縁層を横切る間隙部を設け、この間隙部から半田
の一部を逃がすことにより、半田の裾引き角度を小さく
するものである。The present invention includes a substrate, a conductor pattern formed on the substrate, and an insulating layer formed so as to traverse the conductor pattern in the vicinity of a component to be soldered onto the conductor pattern. In the thick film printed circuit board, the insulating layer is provided with a gap that crosses the insulating layer, and a part of the solder escapes from this gap, thereby reducing the hem angle of the solder.
以下、図面を参照して本発明の一実施例を説明する。第
6図に、本発明を低抵抗(1Ω以下)を盛会とする導体
抵抗を使用した厚膜印刷基板に適用した例を示すもので
ある。同図において、1ノにセラミック基板であり、こ
のセラミック基板11上にはAgP’dの厚膜により形
成された導体パターン12が形成されている。この導体
パターン12の部品が半田付けされる個所の近傍には、
例えばガラスで形成され、導体パターン12を横断する
直線状の絶縁層13,13、及び枠状の絶縁層14がそ
れぞれ印刷されている。これら絶縁層13,13.14
にはそれぞれ当該絶縁層を横切るような複数の間隙15
゜15・・・が設けられている。しかして、導体パター
ン12上の所定の位置には、溶接電極16 、16、ボ
ンディング電極17及び半導体ベレット18が半田19
付けされている。ボンティング電極17と半導体ベレッ
ト18の電極との間はボンディングワイヤ2oにより接
続されている。Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows an example in which the present invention is applied to a thick film printed board using a conductor resistor with a low resistance (1Ω or less). In the figure, No. 1 is a ceramic substrate, and a conductor pattern 12 made of a thick film of AgP'd is formed on this ceramic substrate 11. In the vicinity of the parts of this conductor pattern 12 where the parts are soldered,
For example, it is made of glass, and linear insulating layers 13, 13 that cross the conductor pattern 12 and a frame-shaped insulating layer 14 are printed, respectively. These insulating layers 13, 13.14
There are a plurality of gaps 15 each crossing the insulating layer.
゜15... is provided. Thus, welding electrodes 16, 16, bonding electrodes 17, and semiconductor pellets 18 are placed at predetermined positions on conductor pattern 12 with solder 19.
It is attached. The bonding electrode 17 and the electrode of the semiconductor pellet 18 are connected by a bonding wire 2o.
上記厚膜印刷基板においては、溶接電極16及びボンデ
ィング電極17の部品を半LU付けする場合、絶縁層1
3.14によp半1:I−119の大部分の拡がシが阻
止されるため、従来と同様に、部品を所望の位置に精度
良く固定することができる。また、この半田19はその
一部が絶縁層13.14の各間隙15部に流れ込む。そ
の結果、半田19の裾引き角度は従来の厚膜印刷基板に
比べ、大幅に小さくなる。従って、絶縁層13.14と
半田19との界面下の導体パターン12へのクラックの
発生が減少し、これにより、導体パターン12の抵抗値
の変化を阻止することができ、′また断線等の事故発生
を防止できる。第8図は、熱衝撃試験(−40℃、30
分←→150℃、30分)による部品量導体抵抗の変化
状態を、従来例と本発明との厚膜印ル1j基板を比較し
て示すものでめる。同図において、Cは従来例の場合、
dは本発明の場合をそれぞれ示すもので、1000サイ
クルの時点では、前者の抵抗変化率の変化が約3%の増
加であるのに対し、後者は約1%弱の増加と大幅に少な
くなる。In the above-mentioned thick film printed circuit board, when attaching the parts of the welding electrode 16 and the bonding electrode 17 in half LU, the insulating layer 1
3.14 prevents most of the p-half 1:I-119 from expanding, so parts can be accurately fixed at desired positions as in the past. Further, a portion of this solder 19 flows into each gap 15 of the insulating layer 13.14. As a result, the skirting angle of the solder 19 is significantly smaller than that of conventional thick film printed circuit boards. Therefore, the occurrence of cracks in the conductor pattern 12 under the interface between the insulating layer 13, 14 and the solder 19 is reduced, thereby making it possible to prevent changes in the resistance value of the conductor pattern 12, and also to prevent wire breakage, etc. Accidents can be prevented. Figure 8 shows the thermal shock test (-40°C, 30°C).
The state of change in component quantity conductor resistance over time (←→150° C., 30 minutes) is shown by comparing the thick film printed circuit board 1j of the conventional example and the present invention. In the same figure, C is for the conventional example;
d shows the cases of the present invention, and at the time of 1000 cycles, the change in resistance change rate in the former increases by about 3%, while in the latter it increases by just under 1%, which is much smaller. .
上記実施例においては、間隙15を、半田付けする部品
の位置精度を同上させるための絶縁層13.14に設け
る場合について説明したが、隣接する部品間を仕切るた
めの絶縁層、例えば第9図に示すようなコンデンサ21
と溶接電極22との間に設けられた絶縁層23に設ける
ようにしてもよく、この場合も上記実施IZIJと同様
の効果が得られる。In the above embodiment, the case where the gap 15 is provided in the insulating layers 13 and 14 for improving the positional accuracy of the parts to be soldered has been described. Capacitor 21 as shown in
It may also be provided in the insulating layer 23 provided between the welding electrode 22 and the welding electrode 22, and in this case as well, the same effect as in the above-mentioned implementation IZIJ can be obtained.
尚、上記間隙の幅及び数は任意であるが、導体パターン
の幅が狭い場合には、間隙の合計輻が導体幅の30〜7
0%程度が望ましい。The width and number of the above-mentioned gaps are arbitrary, but when the width of the conductor pattern is narrow, the total convergence of the gaps is 30 to 7 times the width of the conductor.
Approximately 0% is desirable.
以上のように本発明によれば、半田付けされる部品の近
傍に導体パターンを横断する絶縁層を有する厚膜印刷基
板において、部品の位置精度を低下させることなく、半
田の裾引き角反を小さくすることができる。従って、導
体パターンのクラック発生を防止できると共に、導体抵
抗の変化を低減でき、信頼性が著しく向上する。As described above, according to the present invention, in a thick film printed circuit board that has an insulating layer that crosses a conductor pattern near the components to be soldered, the hem angle of the solder can be adjusted without reducing the positional accuracy of the components. Can be made smaller. Therefore, it is possible to prevent the occurrence of cracks in the conductor pattern, reduce changes in conductor resistance, and significantly improve reliability.
第1図は従来の厚膜印刷基板の構成を示す平面図、第2
図は第1図のA −A’線に沿ったWT面図、第3図は
第2図の要部を拡大して示す断面図、第4図は導体パタ
ーンへのクラックの発生と熱衝撃サイクルによるクラッ
クの発生状況を示す図、第6図は本発明の一笑施例に係
る厚膜印刷基板の構成を示す平面図、第7図は第6図の
B−B’線に沿った断面図、第8図は熱衝撃サイクルに
対する抵抗変化率の変化状態を従来と本発明とを比較し
て示す図、第9図fl’;C不発明の他の実施例に係る
平面図でおる。
11・・・セラミック基板、12・・・4体パターン、
13.14・・・絶縁層、15甲間隙、16・・・溶接
電極、17・・・ボンディング成極、18・・・半導体
ペレット。
出願人代理人 升埋士 鈴 江 武 彦第1図
第3図
q \、
第4図
熱衝撃サイクル数
486図Figure 1 is a plan view showing the structure of a conventional thick film printed circuit board;
The figure is a cross-sectional view of the WT taken along the line A-A' in Figure 1, Figure 3 is an enlarged cross-sectional view of the main part of Figure 2, and Figure 4 is the occurrence of cracks in the conductor pattern and thermal shock. 6 is a plan view showing the structure of a thick film printed circuit board according to an embodiment of the present invention, and FIG. 7 is a cross section taken along line BB' in FIG. 6. Figures 8 and 8 are diagrams comparing the state of change in the rate of change in resistance with respect to thermal shock cycles between the conventional and the present invention, and Figure 9 is a plan view of another embodiment of the present invention. 11...Ceramic substrate, 12...4 body pattern,
13.14... Insulating layer, 15 Gap, 16... Welding electrode, 17... Bonding polarization, 18... Semiconductor pellet. Applicant's agent Suzue Takehiko Figure 1 Figure 3 q \ Figure 4 Number of thermal shock cycles 486 Figure
Claims (1)
導体パターン上に半田伺けされる部品の近傍で、前記導
体パターン上を横断するように形成された絶縁層とを具
jifi L、 、iIJ記絶縁魅に少なくとも1個の
間隙を設けたこと乞特徴とする厚膜印刷基板。A substrate, a conductive pattern formed on the substrate, and an insulating layer formed across the conductive pattern in the vicinity of a component to be soldered onto the conductive pattern. A thick film printed circuit board characterized in that at least one gap is provided in the insulation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169874A JPS6062190A (en) | 1983-09-14 | 1983-09-14 | Thin film printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169874A JPS6062190A (en) | 1983-09-14 | 1983-09-14 | Thin film printed board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6062190A true JPS6062190A (en) | 1985-04-10 |
| JPH0526360B2 JPH0526360B2 (en) | 1993-04-15 |
Family
ID=15894553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58169874A Granted JPS6062190A (en) | 1983-09-14 | 1983-09-14 | Thin film printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6062190A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365973A (en) * | 1976-11-25 | 1978-06-12 | Mitsubishi Electric Corp | Method of producing hyb ic |
| JPS54101162A (en) * | 1978-01-26 | 1979-08-09 | Nippon Electric Co | Circuit board |
| JPS57192100A (en) * | 1981-05-22 | 1982-11-26 | Hitachi Ltd | Hybrid ic |
-
1983
- 1983-09-14 JP JP58169874A patent/JPS6062190A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365973A (en) * | 1976-11-25 | 1978-06-12 | Mitsubishi Electric Corp | Method of producing hyb ic |
| JPS54101162A (en) * | 1978-01-26 | 1979-08-09 | Nippon Electric Co | Circuit board |
| JPS57192100A (en) * | 1981-05-22 | 1982-11-26 | Hitachi Ltd | Hybrid ic |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0526360B2 (en) | 1993-04-15 |
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