JPH05281151A - Wafer pattern inspection device - Google Patents

Abstract

(57) [Abstract] [Purpose] Highly accurate pattern inspection can be performed without causing erroneous detection due to variations in surface treatment between wafers. [Structure] An inspection image of a wafer 1 is input by a visual sensor 3. The image comparison circuit 4d compares the input inspection image with the prestored master image, and the determination circuit 4e determines the quality of the wafer 1 based on the difference amount of the comparison image. When the difference amount is equal to or less than the predetermined value, the input inspection image is stored in the master storage circuit 4h as a new master image, and the wafer pass / fail judgment result is output to the judgment output processing circuit 5. Even if the surface condition of the wafer 1 changes little by little, the master image is updated in accordance with this change, so that the variation in the surface condition is canceled, and only the difference due to a circuit defect or the like is satisfactorily detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer pattern inspection device, and more particularly to an inspection device having high inspection accuracy.

[0002]

2. Description of the Related Art A wafer pattern inspection apparatus that automates the appearance inspection of a wafer having a semiconductor integrated circuit is described in, for example, Japanese Patent Application Laid-Open No. 2-170549, in which an inspection image of a wafer is input and stored in advance. The master image as a reference is compared with the standard image, and it is determined whether or not there is a defect in a portion where the comparison image is different, and the quality is determined.

[0003]

However, according to the experiments conducted by the inventor, the wafer surface varies between lots, between wafers, and between chips, and this variation slightly changes among them. .. Therefore, this variation does not cause much problem between wafers (or chips) that are close to each other to some extent, but if the reference master image is always the same as in the conventional apparatus, the variation of the wafer to be inspected is accumulated. The determination result may be negative even though the difference amount of the comparison image exceeds the allowable value and there is no defect in the circuit pattern.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a wafer pattern inspection apparatus which can always perform highly accurate pattern inspection without causing erroneous detection due to variations in surface treatment between wafers. ..

[0005]

The structure of the present invention will be described with reference to FIG. 8. In the wafer pattern inspection apparatus, the means for inputting the inspection image of the wafer is compared with the input inspection image and the master image stored in advance. Comparing means, a means for judging the quality of the wafer from the difference amount of the comparison image, a means for storing the input inspection image as a new master image when the difference amount is a predetermined value or less, And means for outputting the determination result.

[0006]

In the apparatus having the above configuration, when the difference amount of the comparison image is less than or equal to the predetermined value, the input inspection image is stored as a new master image, so that even if the surface condition of the wafer changes slightly, The master image is updated following this change, and the variation in the surface state is canceled. Therefore, in the comparison image, only a difference due to a circuit defect or the like is satisfactorily detected, and an error does not occur in the determination.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the overall structure of a wafer pattern inspection apparatus. The wafer 1 is placed on an xyθ table 2 which can be moved or rotated (θ) in the x-axis and y-axis directions, and a visual sensor 3 for obtaining an inspection image of a predetermined range on the surface of the wafer 1 is provided above it. Has been. The image output of the visual sensor 3 is input to the image processing device 4 whose details will be described later. The xyθ table 2 is driven by the control circuit 21, and the control circuit 21 receives an operation signal from the control circuit 4j of the image processing apparatus 4. The control circuit 4j outputs a determination signal to the determination output processing circuit 5, and the defective portion on the wafer 1 is stored or marked based on the determination signal.

The image processing device 4 is composed of the circuits shown in the figure. Hereinafter, each circuit will be described together with the operation of the present device with reference to FIGS.

The inspection position information and the master information are taught to the image processing apparatus 4 in advance by using the master teaching circuit 4i. That is, FIG. 2 shows a procedure for inputting inspection position information. In order to match the non-defective wafer 1 (not necessarily a non-defective wafer) with the x and y axis directions of the visual sensor, the control circuit 4j and the control circuit 21 are connected. Through xyθ
The table 2 is rotated to correct the position (step 10
1) The inspection image of the wafer 1 is input through the image input circuit 4a, and the area size of the portion and the entire area to be inspected at once by the visual sensor 3 is set (step 102).

Next, which of the plurality of inspection portions on the entire surface is to be inspected is designated (step 103), and the order of the inspection portions is set (step 104).

FIG. 3 shows a procedure for inputting master information. In step 201, the xyθ table 2 is used for the same reason as above.
Is rotated to correct the position of the non-defective wafer 1, the table 2 is moved to the inspection position taught as the master image (step 202), and the master image is input from the image input circuit 4a (step 203).

The image position detection circuit 4b detects the origin of the input master image from the image pattern by edge detection or the like and stores the coordinates thereof (step 20).
4), the master image Vm (see FIG. 5) is transferred to the master storage circuit 4
It is stored in h (step 205).

The inspection procedure of the quality of the wafer is as shown in FIG. The inspection wafer 1 is set on the xyθ table 2 and rotated as in the case of teaching to correct the position (step 301). Next, the wafer 1 is moved to the inspection start portion (1a in FIG. 6) (step 302), and the inspection image Vd (see FIG. 6) is input from the visual sensor 3 via the image input circuit 4a (step 303).

The origin of the input inspection image Vd is detected by the image position detecting circuit 4b (step 304). Subsequently, the image position correction circuit 4c corrects the positional deviation from the master image (step 305), and at the same time, the inspection image is stored in the temporary storage circuit 4f. Then, the image comparison circuit 4d compares the inspection image Vd with the master image Vm (step 305).

If the inspection wafer 1 is a good product, both images Vd,
Although there should be no difference in Vm, in reality, a slight change in the surface state causes a difference from the master image in the portion 1b in FIG. 6, and the comparison image Vc as shown in FIG.
In some cases, a mismatched portion 1c may be detected (step 3
06).

The master update determination circuit 4g determines whether or not the feature amount (shape, size, etc.) of the mismatched portion 1c is within the updatable level (step 307), and if it is within the updatable level, the master storage circuit 4h. The master image Vm therein is replaced with the temporarily stored inspection image Vd and updated (step 308).

The pass / fail judgment circuit 4e judges pass / fail depending on whether or not the feature amount at the mismatched portion between the master image Vm and the inspection image Vd exceeds the defect level, and the result is determined by the control circuit 4.
output to j (step 309). In response to this, the control circuit 4j outputs a determination signal to the determination output processing circuit 5. Here, the updatable level is equal to or lower than the defective level.

In step 310, it is checked whether the inspection area is the final portion on the wafer 1, and if it is the final portion, the inspection is finished. If it is not the final portion, the process moves to the next inspection portion on the wafer 1 (step 311).

As the visual sensor 3, a line sensor, a distance sensor or the like can be used in addition to the area sensor. Further, the control circuit may use a sequencer or the like that is separate from the image processing device.

[0020]

As described above, according to the wafer pattern inspection apparatus of the present invention, since the master image is updated successively, the difference between the detected image and the master image is canceled even if the surface condition of the wafer changes little by little. It is possible to reliably detect only pattern changes due to circuit defects and the like with high sensitivity.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a wafer pattern inspection device.

FIG. 2 is a flowchart of a procedure for inputting inspection position information.

FIG. 3 is a flowchart of a master information input procedure.

FIG. 4 is a flowchart of an inspection procedure.

FIG. 5 is a diagram showing a master image.

FIG. 6 is a diagram showing an inspection image.

FIG. 7 is a diagram showing a comparative output image.

FIG. 8 is a claim correspondence diagram.

[Explanation of symbols]

 1 Wafer 2 xyθ Table 3 Visual Sensor 4 Image Processing Device 4a Image Input Circuit 4d Image Comparison Circuit 4e Good / Fail Judgment Circuit 4g Master Update Judgment Circuit 4h Master Storage Circuit 5 Judgment Output Processing Circuit

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Claims (1)

[Claims] 1. A means for inputting an inspection image of a wafer, a means for comparing the input inspection image with a master image stored in advance, a means for judging the quality of the wafer based on the difference amount of the comparison image, and the difference. A wafer pattern inspection apparatus comprising means for storing the input inspection image as a new master image when the amount is less than or equal to a predetermined value, and means for outputting the quality determination result.