JPH05291327A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH05291327A
JPH05291327A JP4095134A JP9513492A JPH05291327A JP H05291327 A JPH05291327 A JP H05291327A JP 4095134 A JP4095134 A JP 4095134A JP 9513492 A JP9513492 A JP 9513492A JP H05291327 A JPH05291327 A JP H05291327A
Authority
JP
Japan
Prior art keywords
gate
resin
tie bar
lead frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4095134A
Other languages
Japanese (ja)
Inventor
Koji Kawakubo
孝司 川久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4095134A priority Critical patent/JPH05291327A/en
Publication of JPH05291327A publication Critical patent/JPH05291327A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent generation of crack at a gate part when sealing with resin a lead frame by the transfer mold method and gate from remaining on gate break by resin sealing a projecting protrusion which is formed at the gate while kept adhering to the side surface of a lead frame tie bar. CONSTITUTION:A gate 11 which is a port for pouring resin and is provided for sealing resin to a lead frame 1 by the transfer mold method is placed on a tie bar 2 and a placement piece 4 and a projecting protrusion 11b with a gate width of a gate 11 is stuck to a side surface 2a of the tie bar 2. Resin is poured from the gate 11 and a semiconductor element 3 and lead terminals 6 and 8 on the placement piece 4 are all resin-sealed. In this case, thermal stress accompanying curing of resin is taken care of by the protrusion 11b and is not concentrated at one point, thus preventing thermal stress from being centered only at a thin part of the gate 11 and crack from being generated and the gate from remaining on gate break.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にリードフレームを利用して樹脂封止してなる
電力用等の半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a semiconductor device for electric power or the like which is resin-sealed using a lead frame.

【0002】[0002]

【従来の技術】樹脂封止型の電力用の半導体装置は、図
4に示すように、リードフレーム1に複数個のフレーム
が形成されている。
2. Description of the Related Art In a resin-sealed power semiconductor device, a lead frame 1 is formed with a plurality of frames, as shown in FIG.

【0003】その各フレームには、図6に示すように、
載置片67に半導体素子68がダイボンドされ、その半
導体素子68とリード端子70,71の各々とはボンデ
ィングワイヤ69により、内部結線が施されて回路が形
成されている。
In each frame, as shown in FIG.
A semiconductor element 68 is die-bonded to the mounting piece 67, and the semiconductor element 68 and each of the lead terminals 70 and 71 are internally connected by a bonding wire 69 to form a circuit.

【0004】そして、この内部結線が施されたリードフ
レーム100をトランスファーモールド法により、樹脂
封止する。すなわち、注入口であるゲート60より注入
された樹脂により、載置片67上の半導体素子68およ
びリード端子70,71およびボンディングワイヤ69
は樹脂封止される。
Then, the lead frame 100 provided with the internal connection is resin-sealed by a transfer molding method. That is, the resin injected from the gate 60 serving as an injection port allows the semiconductor element 68 on the mounting piece 67, the lead terminals 70 and 71, and the bonding wire 69.
Is resin-sealed.

【0005】その後、図7に示すようにゲート60をゲ
ートブレイクし、薄バリ65および厚バリ63をレジン
カットし、タイバー64,62,66をタイバーカット
することにより図8に示す半導体装置が完成する。
After that, as shown in FIG. 7, the gate 60 is gate-broken, the thin burr 65 and the thick burr 63 are resin-cut, and the tie bars 64, 62, 66 are tie-bar cut to complete the semiconductor device shown in FIG. To do.

【0006】[0006]

【発明が解決しようとする課題】ところで、従来の技術
では、図6に示すようにリードフレームをトランスファ
ーモールド法により樹脂封止した場合、ゲート60をゲ
ートブレイクするまでにモールド樹脂の熱収縮によりゲ
ート60にクラック60aが発生し、ゲートブレイクし
てもそのクラック60aの部分で割れてしまうという問
題があった。すなわち、図7に示すように、クラック6
0aで割れてしまうと、ゲート残りが発生し、図8に示
すように、ゲート残りが付着した外観不良のデバイスと
なり、品質が低下する。また、タイバーカットする際
に、ゲート残りが付着していると、タイバーカット金型
が破損するという問題もある。
By the way, according to the conventional technique, when the lead frame is resin-sealed by the transfer molding method as shown in FIG. 6, the gate 60 is thermally contracted by the mold resin before the gate breaks. There is a problem that a crack 60a is generated in 60, and even if the gate is broken, the crack 60a is broken. That is, as shown in FIG.
If it is cracked at 0a, a gate residue is generated, and as shown in FIG. 8, the device becomes a device with poor appearance in which the gate residue is attached, and the quality deteriorates. Further, when the tie bar is cut, if the remaining gate is attached, the tie bar cutting die may be damaged.

【0007】本発明はこれらの点に鑑みてなされたもの
であり、リードフレームをトランスファーモールド法に
より樹脂封止した場合、ゲートをゲートブレイクするま
でに、ゲートクラックが発生せず、また、ゲートブレイ
クした後、ゲート残りが発生しない半導体装置の製造方
法を提供することを目的とする。
The present invention has been made in view of these points, and when a lead frame is resin-sealed by a transfer molding method, a gate crack does not occur before the gate is broken, and the gate break is generated. After that, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which no gate residue occurs.

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置の製造方法は、対向する位置
に設けた2つの支持タイバー、その支持タイバー間に設
けた載置片、リード端子、およびそのリード端子を支持
するリード端子間タイバーとを、一体に形成してなるリ
ードフレームを用い、上記載置片上に載置した半導体素
子と上記リード端子とを接続した状態で、上記一方の支
持タイバー近傍に設けたゲートから樹脂を注入して、樹
脂封止する半導体装置の製造方法において、上記ゲート
の所定位置に、凸状で、かつ、そのゲート幅と等しい幅
を有する突起を設けるとともに、その突起の端面を上記
一方の支持タイバー側面に密着させた状態で、樹脂封止
することによって特徴付けられる。
In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises two support tie bars provided at opposite positions, a mounting piece provided between the support tie bars, A lead terminal, and a lead terminal inter-tie tie bar supporting the lead terminal are used together with a lead frame, and the semiconductor element mounted on the mounting piece and the lead terminal are connected to each other, and In a method of manufacturing a semiconductor device in which a resin is injected from a gate provided in the vicinity of one of the support tie bars to perform resin sealing, a protrusion having a convex shape and a width equal to the gate width is provided at a predetermined position of the gate. It is characterized in that it is provided and is resin-sealed in a state where the end face of the protrusion is in close contact with the side face of the one support tie bar.

【0009】[0009]

【作用】樹脂が注入された後、その樹脂が硬化し、その
熱収縮により熱応力が生じても、また、特にゲートの長
手方向に熱応力が生じても、突起がその熱応力を分担す
る。従って、ゲートの細くなった部分のみに熱応力が集
中することがなく、ゲートにクラックは生じない。
After the resin is injected, the resin is hardened and the thermal contraction causes thermal stress, and particularly when the thermal stress occurs in the longitudinal direction of the gate, the protrusions share the thermal stress. .. Therefore, thermal stress does not concentrate only on the narrowed portion of the gate, and the gate does not crack.

【0010】[0010]

【実施例】図5は、図4に示すリードフレーム1の破線
で示す部分の拡大図である。載置片4上の半導体素子3
はリード端子6,8とボンディングワイヤ5により内部
結線が施され、回路形成されている。
EXAMPLE FIG. 5 is an enlarged view of a portion indicated by a broken line of the lead frame 1 shown in FIG. Semiconductor element 3 on mounting piece 4
Is internally connected by the lead terminals 6 and 8 and the bonding wire 5 to form a circuit.

【0011】図1乃至図3は本発明実施例を経時的に説
明する図である。各図の(a)図および(b)図はそれ
ぞれ平面図およびその側面図である。以下、図面に基づ
いて本発明実施例を説明する。
1 to 3 are views for explaining an embodiment of the present invention with time. The (a) figure and the (b) figure of each figure are a top view and its side view, respectively. Embodiments of the present invention will be described below with reference to the drawings.

【0012】まず、図5に示した内部結線が施されたリ
ードフレーム1をトランスファーモールド法により樹脂
封止を行う。この樹脂封止を行うために設けられる樹脂
の注入口であるゲート11は、タイバー2および載置片
4上に載置され、また、ゲート11のゲート幅を有する
凸状の突起11bがタイバー2の側面2aに密着して設
けられている。この状態でゲート11から樹脂の注入を
行うことにより、載置片4上の半導体素子3およびその
半導体素子3とボンディングワイヤ5により、結線が施
されているリード端子6,8はすべて樹脂封止され、封
止樹脂12により覆われる。また、この樹脂封止の際、
薄バリ13および厚バリ14が形成される(図1)。
First, the lead frame 1 with the internal connection shown in FIG. 5 is resin-sealed by the transfer molding method. The gate 11 which is a resin injection port provided for performing the resin sealing is mounted on the tie bar 2 and the mounting piece 4, and the protrusion 11 b having a gate width of the gate 11 has a protrusion 11 b. It is provided in close contact with the side surface 2a. By injecting resin from the gate 11 in this state, the semiconductor element 3 on the mounting piece 4 and the lead terminals 6 and 8 connected by the semiconductor element 3 and the bonding wire 5 are all resin-sealed. And is covered with the sealing resin 12. Also, at the time of this resin sealing,
A thin burr 13 and a thick burr 14 are formed (FIG. 1).

【0013】次に、封止樹脂12が硬化した後、ゲート
11をゲートブレイクする。この工程で、ゲート11は
殆どゲートを残さずにゲートブレイクがなされる(図
2)。そして、薄バリ13および厚バリ14をレジンカ
ットし、その後、タイバー2,9,10をタイバーカッ
トすることにより所望の半導体装置が完成する(図
3)。 なお、本発明実施例に示した半導体素子は1つ
のリードフレームに複数個ダイボンドされており、各半
導体素子は同時に樹脂封止がなされる。
Next, after the sealing resin 12 is cured, the gate 11 is broken. In this process, the gate 11 is gate-breaked with almost no gate left (FIG. 2). Then, the thin burr 13 and the thick burr 14 are resin-cut, and then the tie bars 2, 9 and 10 are tie-bar cut to complete a desired semiconductor device (FIG. 3). A plurality of semiconductor elements shown in the embodiments of the present invention are die-bonded to one lead frame, and each semiconductor element is simultaneously resin-sealed.

【0014】本発明実施例ではゲート11に形成した突
起11bが、タイバー2の側面2aに密着した状態で樹
脂封止を行うから、樹脂の硬化に伴う熱応力はこの突起
11bが分担し、一点に集中しない。この結果、モール
ド樹脂を成形してからゲートブレイクするまでにクラッ
クは発生せず、ゲートブレイクの際に、ゲート残りのな
い半導体装置が完成する。
In the embodiment of the present invention, since the protrusion 11b formed on the gate 11 is sealed with the resin in close contact with the side surface 2a of the tie bar 2, the thermal stress due to the curing of the resin is shared by the protrusion 11b. Don't concentrate on As a result, a crack does not occur between the molding of the molding resin and the gate break, and a semiconductor device having no gate residue at the time of the gate break is completed.

【0015】[0015]

【発明の効果】以上説明したように、本発明によれば、
ゲートにそのゲート幅を有し、凸状の突起をリードフレ
ームタイバー側面に密着した状態で樹脂封止を行うよう
にしたから、トランスファーモールド法により樹脂を成
形してからゲートブレイクするまでの間に発生する熱収
縮による熱応力を突起が分担する。従って、ゲートの所
定点にのみ熱応力が集中することがなく、クラックは生
じない。
As described above, according to the present invention,
The gate has the gate width, and the resin is sealed with the convex protrusions in close contact with the side surface of the lead frame tie bar. Therefore, between the molding of the resin by the transfer molding method and the gate break. The protrusions share the thermal stress due to the generated thermal contraction. Therefore, thermal stress does not concentrate only on a predetermined point of the gate, and cracks do not occur.

【0016】その結果、ゲートブレイクしてもゲート残
りは発生せず、半導体装置の外観を損ねることがなく、
また、品質は向上する。さらに、その製造工程におい
て、歩留りは向上し、また、タイバーカット金型を破損
する等の工程上のトラブルもなくすことができる。
As a result, no gate residue is generated even if the gate is broken, and the appearance of the semiconductor device is not damaged.
Also, the quality is improved. Further, in the manufacturing process, the yield can be improved, and troubles in the process such as damage to the tie bar cutting die can be eliminated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例を説明する図FIG. 1 is a diagram illustrating an embodiment of the present invention.

【図2】本発明実施例を説明する図FIG. 2 is a diagram illustrating an embodiment of the present invention.

【図3】本発明実施例により製造された半導体装置の平
面図
FIG. 3 is a plan view of a semiconductor device manufactured according to an embodiment of the present invention.

【図4】本発明実施例に用いられるリードフレームの平
面図
FIG. 4 is a plan view of a lead frame used in an embodiment of the present invention.

【図5】本発明実施例に用いられる樹脂封止前の半導体
装置の平面図
FIG. 5 is a plan view of a semiconductor device used in an embodiment of the present invention before resin sealing.

【図6】従来例を説明する図FIG. 6 is a diagram illustrating a conventional example.

【図7】従来例を説明する図FIG. 7 is a diagram illustrating a conventional example.

【図8】従来例により製造された半導体装置の平面図FIG. 8 is a plan view of a semiconductor device manufactured by a conventional example.

【符号の説明】[Explanation of symbols]

1・・・・リードフレーム 2,9,10・・・・タイバー 3・・・・半導体素子 4・・・・載置片 5・・・・ボンディングワイヤ 6,7,8・・・・リード端子 11・・・・ゲート 11b・・・・突起 12・・・・封止樹脂 1 ... Lead frame 2, 9, 10 ... Tie bar 3 ... Semiconductor element 4 ... Mounting piece 5 ... Bonding wire 6, 7, 8 ... Lead terminal 11 ... Gate 11b Protrusion 12 Encapsulation resin

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 B29L 31:34 4F ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location B29L 31:34 4F

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 対向する位置に設けた2つの支持タイバ
ー、その支持タイバー間に設けた載置片、リード端子、
およびそのリード端子を支持するリード端子間タイバー
とを、一体に形成してなるリードフレームを用い、上記
載置片上に載置した半導体素子と上記リード端子とを接
続した状態で、上記一方の支持タイバー近傍に設けたゲ
ートから樹脂を注入して、樹脂封止する半導体装置の製
造方法において、上記ゲートの所定位置に、凸状で、か
つ、そのゲート幅と等しい幅を有する突起を設けるとと
もに、その突起の端面を上記一方の支持タイバー側面に
密着させた状態で、樹脂封止することを特徴とする半導
体装置の製造方法。
1. Two support tie bars provided at opposing positions, a mounting piece provided between the support tie bars, a lead terminal,
And a tie bar between lead terminals for supporting the lead terminal, a lead frame formed integrally with the semiconductor element mounted on the mounting piece and the lead terminal are connected to each other to support the one side. In a method of manufacturing a semiconductor device in which a resin is injected from a gate provided in the vicinity of a tie bar to perform resin sealing, a protrusion having a convex shape and a width equal to the gate width is provided at a predetermined position of the gate, A method for manufacturing a semiconductor device, characterized by encapsulating with resin in a state where an end face of the protrusion is in close contact with a side face of the one support tie bar.
JP4095134A 1992-04-15 1992-04-15 Method for manufacturing semiconductor device Pending JPH05291327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4095134A JPH05291327A (en) 1992-04-15 1992-04-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4095134A JPH05291327A (en) 1992-04-15 1992-04-15 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH05291327A true JPH05291327A (en) 1993-11-05

Family

ID=14129354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4095134A Pending JPH05291327A (en) 1992-04-15 1992-04-15 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH05291327A (en)

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