JPH0529568A - Semiconductor storage device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a stacked capacitor type memory cell, the structure of the capacitor is simplified and the height of the capacitor portion is made lower than in the conventional case. [Structure] A concave groove is formed in one of the silicon growth layers 3 formed by growing silicon on the N ⁺ diffusion layer 5. A capacitor is formed by the silicon growth layer 3 and the cell plate 2, and the silicon growth layer 3 is used as a storage node. [Effect] The height of the capacitor portion is lowered, and the bit line 1
Since the distance between and the surface of the P-type semiconductor substrate 7 is short, it is easy to make a bit line contact. Moreover, since the structure of the capacitor unit is not complicated, the number of manufacturing steps can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory, and more particularly to a capacitor structure of a stacked capacitor type memory cell.

[0002]

2. Description of the Related Art Among dynamic random access memories (hereinafter referred to as DRAMs) used in conventional semiconductor memory devices, one-transistor-one-capacitor type DR
In the AM memory cell, the capacitor formed not between the silicon substrate but between the stacked polysilicon or the like is called a stacked capacitor type memory cell.

With the recent increase in the capacity of semiconductor memory devices, the memory cell size has been reduced and the distance between word lines has become shorter. As a result, the storage nodes and bit line-N ⁺ diffusion layer contacts arranged between them have become smaller. Placement has become difficult. Therefore, as shown in FIG. 2, the storage node and the bit line contact directly N ⁺ without forming the diffusion layer, the silicon growth layer formed on the N ⁺ diffusion layer are formed thereon.

FIG. 2 is a sectional view showing a conventional example of a stacked capacitor type memory cell. In the figure, 1 is a bit line, 2 is a cell plate, 3 is a silicon growth layer, 4 is a word line, 5 is a cell line. Is an N ⁺ diffusion layer, 6 is a storage node, 7 is a P-type semiconductor substrate, and 8 is an insulating film. An N ⁺ diffusion layer 5 is formed on one main surface of the P-type semiconductor substrate 7, and this N ⁺ diffusion layer 5 is formed along with the word line 4 and the silicon growth layer 3 formed on one main surface of the P-type semiconductor substrate 7. The transfer transistor is configured in. One silicon growth layer 3 makes contact with the bit line 1, the other silicon growth layer 3 forms a storage node 6 thereon, and the surface of the storage node 6 is insulated by an insulating film 8. Forms a capacitor with the. The blank portion between the layers is an insulating film.

[0005]

Since the conventional memory cell is constructed as described above, the depth from the bit line 1 to the N ⁺ diffusion layer 5 becomes deep and it becomes difficult to make a bit line contact. .. Further, since the silicon growth layer 3 is provided and the storage node 6 is formed on the silicon growth layer 3, there is a problem in that the number of manufacturing processes is increased.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device in which a bit line contact can be easily made and the number of manufacturing steps does not increase.

[0007]

A semiconductor device according to the present invention is a semiconductor memory device having a stacked capacitor type memory cell, wherein the stacked capacitor type memory cell is one main substrate of a semiconductor substrate of a first conductivity type. A transfer transistor having first and second diffusion regions of the second conductivity type formed on the surface, and first and second silicon growth layers formed on the first and second diffusion regions. Prepare,
The second silicon growth layer has a recess on the upper surface, and the second silicon growth layer having the recess is used as a storage node of the memory cell.

[0008]

In the semiconductor device according to the present invention, in the first and second silicon growth layers formed on the first and second diffusion regions, the second silicon growth layer has a concave portion on the upper surface, By using the second silicon growth layer having the recess as the storage node of the memory cell, it is not necessary to form the storage node so as to be stacked on the silicon growth layer, and the first and second silicon growth layers are formed. When the bit line is formed on the layer, the depth from the bit line to the semiconductor substrate surface of the first conductivity type can be formed shallow. Further, since the silicon growth layer is used as a storage node at the same time, the step of stacking another conductive layer as a storage node is unnecessary.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a stacked capacitor type memory cell according to an embodiment of the present invention. In the figure, 1
Is a bit line, 2 is a cell plate, 3 is a silicon growth layer,
Reference numeral 4 is a word line, 5 is an N ⁺ diffusion layer, and 7 is a P-type semiconductor substrate. Moreover, the blank part between each layer is an insulating layer. The N ⁺ diffusion layer 5 constitutes a drain region and a source region which are the first and second diffusion regions of the second conductivity type of the transfer transistor. The silicon growth layer 3 which is the first and second silicon growth layers is the N ⁺ diffusion layer 5 which is the first and second diffusion layers.
Silicon is grown and formed on it. The word line 4 is also the gate electrode of the transfer transistor. One of the silicon growth layers 3 is a second silicon growth layer, and a recess is formed on the upper surface of the second silicon growth layer.
Is insulated by. Therefore, the conductive cell plate 2 formed on the one silicon growth layer 3 constitutes a capacitor. That is, the one silicon growth layer 3 is also used as a storage node. Since one silicon growth layer 3 has a concave portion and is used as a storage node, the distance between the upper surface of the cell plate 2 forming the capacitor and the P-type semiconductor substrate 7 can be formed shorter than in the conventional case, and the bit line 1 To the upper surface of the N ⁺ diffusion layer 5 can be formed to be shallow, and the distance between the bit line 1 and the other silicon growth layer 3 which is the first silicon growth layer can be shortened to facilitate bit line contact. .. Further, since one silicon growth layer 3 has a recess and is used as a storage node, it is not necessary to form an insulation layer and a conductive layer on the silicon growth layer to form a storage node as in the conventional case. Therefore, the manufacturing process is reduced.

[0010]

As described above, according to the present invention,
In the first and second silicon growth layers formed on the second diffusion region, the second silicon growth layer has a recess on the upper surface, and the second silicon growth layer having the recess is used as the memory. When used as a storage node of a cell, the storage node does not have to be formed so as to be stacked on the silicon growth layer, and when the bit line is formed on the first and second silicon growth layers, the bit line It is possible to form a shallow depth from to the upper surface of the first silicon growth layer, and it is easy to make a bit line contact. Further, since the storage node is formed as in the conventional case, there is no need to further form an insulating layer and a conductive layer on the silicon growth layer, and there is an effect that the manufacturing process can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a stacked capacitor type memory cell according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional stacked capacitor type memory cell.

[Explanation of symbols]

1 bit line 2 cell plate 3 silicon growth layer 4 word line 5 N ⁺ diffusion layer 7 P-type semiconductor substrate 9 insulating film

Claims (1)

1. A semiconductor memory device having a stacked capacitor type memory cell, wherein the stacked capacitor type memory cell is formed on one main surface of a semiconductor substrate of a first conductivity type. A transfer transistor having first and second diffusion regions of the second conductivity type, and a first transistor formed on the first and second diffusion regions,
A second silicon growth layer, wherein the second silicon growth layer has a recess on the upper surface, and the second silicon growth layer having the recess is used as a storage node of the memory cell. Storage device.