JPH05299514A - Via formation method - Google Patents
Via formation methodInfo
- Publication number
- JPH05299514A JPH05299514A JP10328792A JP10328792A JPH05299514A JP H05299514 A JPH05299514 A JP H05299514A JP 10328792 A JP10328792 A JP 10328792A JP 10328792 A JP10328792 A JP 10328792A JP H05299514 A JPH05299514 A JP H05299514A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- insulating layer
- layer
- conductor
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】
【目的】 半導体チップ, 回路基板等に設けた導体パタ
ーン間を接続する、ビアの形成方法に関し、製造工程が
簡単で、且つ微細ビアを形成し得る、ビアの形成方法を
提供することを目的とする。
【構成】 中間絶縁層2-2 を介して下層導体パターン3-
1 と上層導体パターン3-2 とが、基板１の表面に形成さ
れてなる回路において、上層導体パターン3-2 を覆う上
部絶縁層2-3 の上方から、押圧体10を圧下して上層導体
パターン3-2 の所望の個所に局部荷重を印加し、上層導
体パターン3-2 と下層導体パターン3-1 間を接続する、
ビア５を設けるものとする。
(57) [Abstract] [Purpose] The present invention relates to a method of forming a via for connecting between conductor patterns provided on a semiconductor chip, a circuit board, etc., which is a simple manufacturing process and is capable of forming a fine via. The purpose is to provide. [Configuration] Lower conductor pattern 3-through the intermediate insulating layer 2-2
In a circuit in which 1 and the upper conductor pattern 3-2 are formed on the surface of the substrate 1, the pressing body 10 is pressed down from above the upper insulating layer 2-3 that covers the upper conductor pattern 3-2, and the upper conductor is pressed. Apply a local load to the desired part of pattern 3-2 to connect between upper layer conductor pattern 3-2 and lower layer conductor pattern 3-1.
The via 5 is provided.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップ, 回路基
板等に設けた導体パターン間を接続する、ビアの形成方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a via forming method for connecting conductor patterns provided on a semiconductor chip, a circuit board or the like.
【０００２】[0002]
【従来の技術】従来のビアの形成方法のエッチング法を
図３に示す。図３において、１はシリコン，またはセラ
ミックスよりなる基板である。2. Description of the Related Art FIG. 3 shows a conventional etching method for forming vias. In FIG. 3, reference numeral 1 is a substrate made of silicon or ceramics.
【０００３】従来は図３の(A) に図示したように、基板
１の全表面にSiO2の絶縁層2-1 を形成し、絶縁層2-1 の
全表面にアルミニウム等を蒸着して導体層を設けた後
に、ホトリソグラフィ手段により所望の幅の下層導体パ
ターン3-1 を設けている。Conventionally, as shown in FIG. 3A, an insulating layer 2-1 of SiO 2 is formed on the entire surface of the substrate 1, and aluminum or the like is vapor-deposited on the entire surface of the insulating layer 2-1. After the conductor layer is provided, the lower layer conductor pattern 3-1 having a desired width is provided by photolithography.
【０００４】そしてさらに、下層導体パターン3-1 を覆
うように、SiO2の中間絶縁層2-2 を設ける。次に図３の
(B) に図示したように、中間絶縁層2-2 上に、ビアに対
応する個所に孔51を有するホトレジスト膜50を設け、エ
ッチングして、ホトレジスト膜50を除去して、図３の
(C) に図示したように、中間絶縁層2-2 に孔40を設け
る。Further, an intermediate insulating layer 2-2 of SiO 2 is provided so as to cover the lower conductor pattern 3-1. Next, in FIG.
As shown in FIG. 3B, a photoresist film 50 having a hole 51 at a position corresponding to the via is provided on the intermediate insulating layer 2-2, and the photoresist film 50 is removed by etching to remove the photoresist film 50 of FIG.
As shown in (C), a hole 40 is provided in the intermediate insulating layer 2-2.
【０００５】そして、図３の(D) に図示したように、中
間絶縁層2-2 のアルミニウム等を蒸着して孔40に導体を
充填してビア35を設けるとともに、中間絶縁層2-2 の全
表面に導体層30を設ける。次に、ホトリソグラフィ手段
により導体層30を所望の形状の上層導体パターン3-2 に
した後に、図３の(E) に図示したように、上層導体パタ
ーン3-2 を上部絶縁層2-3 で被覆している。Then, as shown in FIG. 3D, aluminum or the like of the intermediate insulating layer 2-2 is vapor-deposited to fill the hole 40 with a conductor to provide a via 35, and the intermediate insulating layer 2-2 is formed. The conductor layer 30 is provided on the entire surface of the. Next, after the conductor layer 30 is formed into the upper conductor pattern 3-2 having a desired shape by photolithography, the upper conductor pattern 3-2 is connected to the upper insulating layer 2-3 as shown in FIG. It is covered with.
【０００６】なお、上層導体パターン3-2 及び下層導体
パターン3-1 の膜厚は、約１μm であり、下層導体パタ
ーン3-1 と上層導体パターン3-2 間の中間絶縁層の膜厚
は１μm 〜0.3 μm で程度ある。The upper conductor pattern 3-2 and the lower conductor pattern 3-1 have a film thickness of about 1 μm, and the intermediate insulating layer between the lower conductor pattern 3-1 and the upper conductor pattern 3-2 has a film thickness. It is about 1 μm to 0.3 μm.
【０００７】また、上述のエッチング法でなく、ビアに
対応する孔を有するホトレジスト膜を、下層導体パター
ンの表面に予め形成しておき、ホトレジスト膜上に導体
を蒸着した後に、ホトレジスト膜上の導体層をホトレジ
スト膜とともに除去して、下層導体パターン上にビア部
分のみを残すという、リフトオフ法も行われている。Further, instead of the above-mentioned etching method, a photoresist film having holes corresponding to the vias is formed in advance on the surface of the lower conductor pattern, the conductor is vapor-deposited on the photoresist film, and then the conductor on the photoresist film is formed. A lift-off method is also performed in which the layer is removed together with the photoresist film and only the via portion is left on the lower conductor pattern.
【０００８】[0008]
【発明が解決しようとする課題】近年は高密度実装化さ
れた半導体チップ、或いは基板への実装部品の高密度実
装化に伴い、幅が 0.5μm 以下の微細幅の導体パターン
が要求されている。In recent years, with the high-density mounting of semiconductor chips or substrates mounted in high density, a conductor pattern with a fine width of 0.5 μm or less is required. ..
【０００９】したがって、下層導体パターンと上層導体
パターン間を接続するビアの直径もまた、0.2 μm 〜0.
3 μm と小さくなっている。ところで、従来のリフトオ
フ法では、ビア部分を残してホトレジスト膜を剥離する
際に、ビアの外周部の導体がホトレジスト膜とともに除
去されるので、微細のビアを製造することは困難なこと
であった。Therefore, the diameter of the via connecting the lower conductor pattern and the upper conductor pattern is also 0.2 μm to 0.
It is as small as 3 μm. By the way, in the conventional lift-off method, when the photoresist film is peeled off leaving the via portion, the conductor in the outer peripheral portion of the via is removed together with the photoresist film, so that it is difficult to manufacture a fine via. ..
【００１０】一方、従来のエッチング法では、絶縁層の
孔にアルミニウム等の導体を蒸着し充填するのである
が、微細孔であるので孔の内壁或いは孔底に十分に導体
が付着しないという問題点があった。On the other hand, in the conventional etching method, the conductor of aluminum or the like is vapor-deposited and filled in the hole of the insulating layer. However, since it is a fine hole, the conductor is not sufficiently adhered to the inner wall of the hole or the bottom of the hole. was there.
【００１１】さらに何れの方法もビアを製造する工程が
複雑であるという問題点があった。本発明はこのような
点に鑑みて創作されたもので、製造工程が簡単で、且つ
微細ビアを形成し得る、ビアの形成方法を提供すること
を目的としている。Further, each of the methods has a problem that the process of manufacturing the via is complicated. The present invention has been made in view of the above circumstances, and an object thereof is to provide a via forming method which is simple in the manufacturing process and capable of forming fine vias.
【００１２】[0012]
【課題を解決するための手段】上記の目的を達成するた
めに本発明は、図１に例示したように、中間絶縁層2-2
を介して上層導体パターン3-2 と下層導体パターン3-1
とが、基板１の表面に形成されてなる回路において、上
層導体パターン3-2 を覆う上部絶縁層2-3 の上方から、
押圧体10を圧下して上層導体パターン3-2 の所望の個所
に局部荷重を印加し、上層導体パターン3-2 と下層導体
パターン3-1 間を接続する、ビア５を設けるものとす
る。In order to achieve the above object, the present invention provides an intermediate insulating layer 2-2 as shown in FIG.
Through upper layer conductor pattern 3-2 and lower layer conductor pattern 3-1
In the circuit formed on the surface of the substrate 1, from above the upper insulating layer 2-3 covering the upper conductor pattern 3-2,
A via 5 is provided to press down the pressing body 10 and apply a local load to a desired portion of the upper layer conductor pattern 3-2 to connect the upper layer conductor pattern 3-2 and the lower layer conductor pattern 3-1.
【００１３】[0013]
【作用】本発明は、押圧体を上部絶縁層或いは保護膜の
上方から圧下することで、上層導体パターンに下方に突
部が形成される。そして、この突部の先端が下層導体パ
ターンに繋がる。According to the present invention, the pressing member is pressed down from above the upper insulating layer or the protective film, so that the upper conductor pattern is formed with a projection below. Then, the tips of the protrusions are connected to the lower conductor pattern.
【００１４】したがって、上層導体パターンと下層導体
パターン間を接続するビアが形成される。また、押圧体
の先端部を円錐体して、局部的な荷重を印加するもので
あるから、形成される突部の径が小さい。即ち形成され
るビアの外径は微小である。Therefore, a via connecting the upper conductor pattern and the lower conductor pattern is formed. In addition, since the tip of the pressing body is made into a conical shape and a local load is applied, the diameter of the formed projection is small. That is, the outer diameter of the formed via is very small.
【００１５】[0015]
【実施例】以下図を参照しながら、本発明を具体的に説
明する。なお、全図を通じて同一符号は同一対象物を示
す。The present invention will be described in detail with reference to the drawings. The same reference numerals denote the same objects throughout the drawings.
【００１６】図１の(A),(B) は本発明の形成方法を示す
工程図、図２は本発明の他の実施例の図である。図１に
おいて、シリコン，またはセラミックスよりなる基板１
の全表面にSiO2の絶縁層2-1 が形成され、絶縁層2-1 の
上部に幅が約 0.5μm のアルミニウム等の下層導体パタ
ーン3-1 が形成されている。FIGS. 1A and 1B are process diagrams showing the forming method of the present invention, and FIG. 2 is a diagram of another embodiment of the present invention. In FIG. 1, a substrate 1 made of silicon or ceramics
An insulating layer 2-1 made of SiO 2 is formed on the entire surface of, and a lower conductor pattern 3-1 such as aluminum having a width of about 0.5 μm is formed on the insulating layer 2-1.
【００１７】そして、膜厚が約２μm のSiO2よりなる中
間絶縁層2-2 を介して、下層導体パターン3-1 の上方に
幅が約 0.5μm のアルミニウム等の上層導体パターン3-
2 を設け、さらに上層導体パターン3-2 の表面を、膜厚
が２μm 程度の上部絶縁層2-3 で覆うことで、所望の回
路が構成されている。Then, an upper conductor pattern 3-of aluminum or the like having a width of about 0.5 μm is formed above the lower conductor pattern 3-1 through an intermediate insulating layer 2-2 made of SiO 2 having a film thickness of about 2 μm.
2 is provided, and the surface of the upper conductor pattern 3-2 is covered with an upper insulating layer 2-3 having a film thickness of about 2 μm to form a desired circuit.
【００１８】10は、ダイヤモンド等よりなる押圧体であ
って、その先端部11は１μm 〜10μm のアールの円錐形
にしてある。このような押圧体10を上部絶縁層2-3 の上
方から圧下して、上層導体パターン3-2 の所望の個所に
局部荷重（荷重は約50g)を約15秒間印加し、上層導体パ
ターン3-2 の下方に突出する突部を設け、この突部の先
端を下層導体パターン3-1 に繋げることで、図１の(B)
に図示したように、下層導体パターン3-1 と上層導体パ
ターン3-2 とを接続するビア５を設けている。Reference numeral 10 is a pressing body made of diamond or the like, and its tip portion 11 has a conical shape with a radius of 1 μm to 10 μm. Such a pressing body 10 is pressed down from above the upper insulating layer 2-3, and a local load (load is about 50 g) is applied to a desired portion of the upper layer conductor pattern 3-2 for about 15 seconds, so that the upper layer conductor pattern 3 -2. Providing a protrusion projecting downward and connecting the tip of this protrusion to the lower layer conductor pattern 3-1.
As shown in FIG. 3, the via 5 connecting the lower layer conductor pattern 3-1 and the upper layer conductor pattern 3-2 is provided.
【００１９】また図２に図示したように、上部絶縁層2-
3 の上に、SiO2等の保護膜４を設けた回路完成体に適用
し、保護膜４の上方から押圧体10を圧下しても、上層導
体パターン3-2 と下層導体パターン3-1 間を接続するビ
ア５を設けることができる。As shown in FIG. 2, the upper insulating layer 2-
Even when applied to a circuit completed body in which a protective film 4 such as SiO 2 is provided on 3 and the pressing body 10 is pressed down from above the protective film 4, the upper layer conductor pattern 3-2 and the lower layer conductor pattern 3-1 A via 5 may be provided to connect the two.
【００２０】上述のように保護膜を押圧する手段は、図
１に図示した方法により形成されたビアの導通不良の補
償手段、或いはリフトオフ法又はエッチング法により形
成されたビアの導通不良の補償手段として、特に効果が
ある。As described above, the means for pressing the protective film is a means for compensating the conduction failure of the via formed by the method shown in FIG. 1 or a means for compensating the conduction failure of the via formed by the lift-off method or the etching method. Is especially effective as
【００２１】なお、本発明方法により得られたビアの形
成状態の確認は、ＥＢ（エレクトビーム）テスタにより
所定部のビア形成前とビア形成後の二次電子のエネルギ
ー分布により判定し得る。The formation state of the via obtained by the method of the present invention can be confirmed by an EB (elect beam) tester based on the energy distribution of secondary electrons before and after forming a predetermined portion of the via.
【００２２】[0022]
【発明の効果】以上説明したように本発明は、0.2 μm
オーダーの微細ビアを、簡単に形成することができ得ら
れる電子デバイスが低コストであるばかりでなく、電子
デバイスの高密度化が寄与するところが大きいという、
優れた効果を有する。As described above, the present invention is 0.2 μm
It is said that not only are electronic devices that can easily form fine vias of the order obtained at low cost, but the high density of electronic devices contributes greatly.
Has excellent effect.
【図１】 (A),(B) は本発明の形成方法を示す工程図1A and 1B are process drawings showing a forming method of the present invention.
【図２】 本発明の他の実施例の図FIG. 2 is a diagram of another embodiment of the present invention.
【図３】 従来の形成方法を示す工程図FIG. 3 is a process diagram showing a conventional forming method.
１ 基板 2-1 絶縁層 2-2 中間絶縁層 2-3 上部絶縁層 3-1 下層導体パターン 3-2 上層導体パターン ４ 保護膜 5,35 ビア 10 押圧体 1 Substrate 2-1 Insulating layer 2-2 Intermediate insulating layer 2-3 Upper insulating layer 3-1 Lower layer conductor pattern 3-2 Upper layer conductor pattern 4 Protective film 5,35 Via 10 Pressing body
Claims (1)
ーン(3-1) と上層導体パターン(3-2) とが、基板(1) の
表面に形成されてなる回路において、 該上層導体パターン(3-2) を覆う上部絶縁層(2-3) の上
方から、押圧体(10)を圧下して該上層導体パターン(3-
2) の所望の個所に局部荷重を印加し、該上層導体パタ
ーン(3-2) と該下層導体パターン(3-1) 間を接続する、
ビア(5) を設けることを特徴とするビアの形成方法。1. A circuit comprising a lower layer conductor pattern (3-1) and an upper layer conductor pattern (3-2) formed on the surface of a substrate (1) through an intermediate insulating layer (2-2), From above the upper insulating layer (2-3) covering the upper conductor pattern (3-2), the pressing body (10) is pressed down so that the upper conductor pattern (3-
Applying a local load to the desired location of 2), connecting the upper layer conductor pattern (3-2) and the lower layer conductor pattern (3-1),
A method for forming a via, which comprises providing a via (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10328792A JPH05299514A (en) | 1992-04-23 | 1992-04-23 | Via formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10328792A JPH05299514A (en) | 1992-04-23 | 1992-04-23 | Via formation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05299514A true JPH05299514A (en) | 1993-11-12 |
Family
ID=14350101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10328792A Withdrawn JPH05299514A (en) | 1992-04-23 | 1992-04-23 | Via formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05299514A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999010929A3 (en) * | 1997-08-22 | 1999-06-10 | Koninkl Philips Electronics Nv | A method of providing a vertical interconnect between thin film microelectronic devices |
-
1992
- 1992-04-23 JP JP10328792A patent/JPH05299514A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999010929A3 (en) * | 1997-08-22 | 1999-06-10 | Koninkl Philips Electronics Nv | A method of providing a vertical interconnect between thin film microelectronic devices |
| JP2001505003A (en) * | 1997-08-22 | 2001-04-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method of forming a longitudinal interconnect between thin film microelectronic devices |
| US6400024B1 (en) | 1997-08-22 | 2002-06-04 | Koninklijke Philips Electronics N.V. | Method of providing a vertical interconnect between thin film microelectronic devices |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990706 |