JPH053014B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a defective data storage device for identifying and storing defective data in a magnetic disk device.

[Conventional technology]

A device for processing defective data generated in a conventional magnetic disk device includes a latch circuit for one byte and a display section. The latch circuit holds the read data in synchronization with the read error pulse, and the display section latch circuit displays the held data.

[Problem that the invention seeks to solve]

The conventional defect data processing device described above is 1.
Only bytes of defective data can be held, so if defective data occurs consecutively or multiple times, the data held by the latch circuit will be the last defective data that occurred, and the defective data that occurred first and the defective data that occurred in the middle will be unreadable. Can not.

Furthermore, since this conventional device cannot retain data before and after the defective data occurs, it is not possible to know the correlation between the defective data and the data before and after the defective data. Therefore, there was a lack of accurate defect data information to know the cause of defect data occurrence.

[Means for solving problems]

The defective data storage device of the present invention includes n registers that shift read data using a reference clock that is synchronized with the read data, and when receiving a read error pulse, a first predetermined time delay from the read error pulse. a circuit for generating a write pulse and a second address update pulse delayed by a second predetermined time from the write pulse; This configuration includes n storage units that write the outputs of the n registers into addresses.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. A shift register is configured by connecting a first register 1, a second register 2, a third register 3, a fourth register 4, and a fifth register 5 in series. The first register 1 reads the read data a.
It is applied to the second register 2 in synchronization with the reference clock b, which is synchronized with the reference clock b. In synchronization with the reference clock b, the second register 2 provides the output of the first register 1 to the third register 3, and the third register 3 provides the output of the second register 3.
The output of register 2 is given to the fourth register 4,
Register 4 provides the output of third register 3 to fifth register 5. The pulse generator 6 is a reference clock b.
and a read error pulse c are input, and a write pulse d delayed by 2 bytes from the read error pulse and an address update pulse e delayed by 1/2 byte from the write pulse d are output. A write pulse d is inputted as a write timing, and an address update pulse e is inputted as an address update input to the first storage section 7, second storage section 8, third storage section 9, fourth storage section 10, and fifth storage section 11. do. As data inputs, the output of the first register 1 is given to the first storage section 7, the output of the second register 2 is given to the second storage section 8, and the output of the third register 3 is given to the third storage section 9. The output of the fourth register 4 is given to the fourth storage section 10, and the output of the fifth register 5 is given to the fifth storage section 11. The display section 12 includes a first storage section 7, a second storage section 8, a third storage section 9, and a fourth storage section 1.
0 and the contents of the fifth storage unit 11 are displayed.

In this embodiment, five registers and five storage sections are used, but these are two before and after the defective data.
This is to obtain byte data.

Now, if the number of registers is n and the number of bytes before and after the defective data to be extracted is m, then there is a relationship of n=2m+1. Here, the write pulse d of the pulse generator 6 is set at a timing delayed by m bytes from the read error pulse c.

Next, the operation of this embodiment will be explained in more detail. The read data a of the magnetic disk device is updated for each byte. Reference clock b is pulsed out when read data a is sufficiently stable,
Its period is equal to 1 byte. If the content of the read data a is x and the time point at which the reference clock b rises is T, then at time T the output of the first register 1 becomes x. first register 1, second register 2,
Since the third register 3, fourth register 4, and fifth register 5 perform a shift operation, x is output to the second register 2 by the reference clock b output when one byte has elapsed from time T. The output of the first register 1 at this point is the data (x
+1). Furthermore, when 2 bytes, 3 bytes, and 4 bytes elapse from time T, the register that outputs x becomes the third register 3 at the time when 2 bytes elapse.
Then, when 3 bytes have elapsed, it becomes the fourth register 4, and when 4 bytes have elapsed, it becomes the fifth register 5. When the output of the fifth register 5 becomes x (T+4 bytes)
The output of the fourth register 4 is (x+1), the output of the third register 3 is (x+2), the output of the second register 2 is (x+3), and the output of the first register 1 is (x+1).
+4). Here, (x+2), (x+3), and (x+4) indicate read data a after 2 bytes, 3 bytes, and 4 bytes have passed since time T.

In this embodiment, during initialization at the time of startup, the designated addresses of the first storage section 7, second storage section 8, third storage section 9, fourth storage section 10, and fifth storage section 11 are synchronized with the reference clock b. Clear to 0. Next, assume that a read error signal c is received when the read data a is _y0 . y ₀ is defective data. The pulse generator 6 is equipped with a counter circuit and a delay circuit, and the counter circuit opens a count gate in synchronization with the read error signal c, counts two pulses of the reference clock, and outputs the write pulse d. Also, the delay circuit changes the write pulse d to 1/
The address update pulse e is output with a delay of 2.

Since two bytes have elapsed before the pulse generator 6 outputs the write pulse d, the third register 3 outputs the defective data y ₀ at the time the write pulse d is output. Also, the second register 2 contains the data 1 byte after the defective data y ₀ (y ₀ +1)
, the first register 1 contains the data 2 bytes later (y ₀ +
2), the fourth register 4 outputs data one byte before (y ₀ -1), and the fifth register 5 outputs data two bytes before (y ₀ -2).

a first storage unit 7, a second storage unit 8, a third storage unit 9,
The number of addresses in the fourth storage unit 10 and the fifth storage unit is equal to or greater than the maximum allowable number of defects in the magnetic disk medium. The first specified address at the beginning of startup is cleared to 0 by initialization, so when the write pulse d is received, the first storage unit 7 is set to address 0.
is (y ₀ +2), the second storage unit 8 is (y ₀ +1),
The third storage unit 9 stores y ₀ , and the fourth storage unit 10 stores (y ₀ −
1), and the fifth storage section stores (y ₀ -2). Then, in response to the update pulse e, the designated address is incremented by one to become address 1, which becomes the address for storing the next defective data.

Since the update pulse e is delayed by only 1/2 byte from the write pulse d, even if defective data occurs continuously (at this time, the defective data is delayed by 1 byte), the specified address has already been updated. .

Thereafter, when yi is generated from y ₁ , y ₂ as defect data, the aforementioned five storage units store the defect data and 2 bytes of data before and after the defect data in addresses 1 to i, respectively.

The display unit 12 displays data (first
Five pieces of data (the storage section 7, the second storage section 8, the third storage section 9, the fourth storage section 10, and the fifth storage section 11) are displayed in binary on the horizontal axis.

FIG. 2 is a block diagram showing another embodiment of the invention. In this embodiment, compared to the embodiment shown in FIG.
A sixth storage section 13 is additionally connected in parallel to the display section 12 .

The sixth storage section 13 is a storage section using, for example, a floppy disk, and has a capacity sufficiently larger than the total storage capacity of each storage section from the first storage section 7 to the fifth storage section 11.

Here, the sixth storage unit 13 stores data from the first storage unit 7 to the fifth storage unit 7.
After storing all the storage data in the storage unit 11, storing the defective data on the first magnetic disk medium, and subsequently storing the defective data on the second magnetic disk medium, a plurality of magnetic disks are sequentially stored. Stores defective data on disk media.

〔Effect of the invention〕

The defect data storage device of the present invention can easily read all the defect data generated from the display data, and can also know the correlation between the defect data and the data of the preceding and following bytes from the horizontal axis. Furthermore, since the defect data and the data of the preceding and following bytes are held in each storage section, accurate information for quality control can be quickly obtained at any time.

It goes without saying that the specific numerical values cited in this example do not limit the scope of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing another embodiment of the invention. 1...First register, 2...Second register, 3
...3rd register, 4...4th register, 5...
5th register, 6...Pulse generator, 7...1st
Storage unit, 8...second storage unit, 9...third storage unit,
10...Fourth storage unit, 11...Fifth storage unit, 12
...Display section, 13...Sixth storage section. a... Read data of the magnetic disk device, b... Reference clock of the magnetic disk device, c... Read error pulse of the magnetic disk device, d... Write pulse, e... Address update pulse.

Claims (1)

[Claims] 1. n registers that shift read data using a reference clock that is synchronized with read data, a write pulse that is delayed by a first predetermined time from this read error pulse when receiving a read error pulse, and this write pulse. a circuit that generates an address update pulse delayed by a second predetermined time from the address update pulse; A defective data storage device consisting of n storage units into which output is written.