JPH05303345A - Display conversion device for converting display signal for LCD into display signal for LED - Google Patents

Abstract

(57) [Abstract] [Object] The present invention is an LCD / LED conversion device which is capable of converting L
It is an object to facilitate separation of the LCD / LED display conversion device and the LED display unit by serially supplying signal data indicating ON / OFF of display pixels to the ED display unit. A display conversion device 100 for converting a display signal for an LCD into a display signal for an LED includes an input unit 11, a first selection circuit 14, and a determination circuit 18. The input unit 11 is an LC
The segment signals supplied in parallel from D10 are output serially. The first selection circuit 14 is an LC
Upon receiving the common signal for D, it outputs a signal indicating the signal level of the common signal. The discrimination circuit 18 receives the segment signal from the input section 11 and the signal indicating the signal level of the common signal from the first selection circuit 14, and turns on / off the display pixel according to the signal indicating the signal level of the segment signal and the common signal. To generate the data and output the data to the output unit 20.
To be serially supplied to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display conversion device for converting a liquid crystal display signal into a display device signal composed of a light emitting element, and more particularly to a liquid crystal display signal supplied in parallel to a serial display signal. It is used in a display conversion device that converts a signal for a display device.

[0002]

2. Description of the Related Art A conventional display conversion device for converting a display signal for a liquid crystal display element (hereinafter, LCD) into a display signal for a light emitting diode (hereinafter, LED) corresponds to a segment signal with a common signal. Whether the segment is on,
It was configured to determine whether it was turned off and output data in parallel.

[0003]

As described above, the prior art is as follows.
Since the converted signals for the light emitting diodes were output in parallel, many connection cables were required to connect the conversion unit board (printed circuit board) and the LED display unit, and the wiring was complicated. ..

The present invention has been made in view of the above circumstances, and when converting a display signal for an LCD into a display signal for an LED, a display signal indicating ON / OFF of a display pixel is serialized to a display device including the LED. It is intended to be supplied by.

[0005]

A display conversion device for converting a display signal for an LCD into a display signal for an LED according to the present invention is a segment signal for serially outputting a segment signal for liquid crystal display supplied in parallel. An input circuit, a common signal input circuit that receives a common signal for liquid crystal display, and outputs a signal indicating the signal level of the common signal, a segment signal from the segment signal input circuit, and the common signal input circuit from the common signal input circuit. A circuit that receives a signal indicating the signal level of the common signal, generates a display signal indicating ON / OFF of the display pixel, and serially supplies the display signal to a display device including a plurality of light emitting elements. Characterize.

[0006]

The segment signal input circuit converts the segment signals supplied in parallel from the liquid crystal display unit into serial signals and supplies the serial signals to the signal generation circuit. Further, the common signal input circuit supplies a signal indicating the signal level of the common signal for liquid crystal display to the signal generation circuit. In response to the signal indicating the signal level of the segment signal and the common signal, the signal generation circuit generates a display signal indicating ON / OFF of the display pixel and serially supplies the display signal to a display device including a plurality of light emitting elements. To do.

As described above, since the display signal is serially supplied from the display conversion device to the display device, the number of connecting lines required for connecting the display conversion device and the display device can be reduced, and the display conversion device and the display device can be reduced. The separation from the device becomes easy, and the display device can be made compact.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A display conversion device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the electrical configuration of a display conversion device according to an embodiment of the present invention. FIG. 2 is a diagram showing a specific configuration of the display conversion device. FIG. 3 is a diagram showing a specific configuration of the input unit shown in FIG. FIG. 4 is a diagram showing details of the first selection circuit 14 and the control circuit 19 of the display conversion device shown in FIG. Figure 5
FIG. 3 is a diagram showing details of the oscillator 12, the signal generation circuit 15, the second selection circuit 13, and the discrimination circuit 18 of the display conversion device shown in FIG. 2. FIG. 6 is a diagram showing details of the output unit 20. FIG. 7 is a timing chart showing the operation of the display conversion device according to the embodiment of the present invention. Hereinafter, description will be given with reference to FIG. 2 showing the overall configuration, FIGS. 3 to 6 showing the details of each part, and a timing chart.

The display conversion device according to this embodiment converts the 32 segment signals for the liquid crystal display device and the two common signals into signals for LED display. In addition, the common signal COM1 and the common signal CO supplied to the display conversion device.
M2 is an opposite phase signal.

The display conversion device 100 of FIG. 1 is connected to an LCD (liquid crystal display element) 10 and an output section 20. Also,
The output unit 20 is connected to the LED (light emitting diode) 101.

The display conversion device 100 has an input section 11, an oscillator 12, a signal generation circuit 15, a second selection circuit 13, a first selection circuit 14, a control circuit 19 and a discrimination circuit 18. Further, the signal generation circuit 15 includes a binary counter 16 and a DIP.
It has a switch 17a and a comparator 17b.

FIG. 2 shows a specific configuration of the display conversion device shown in FIG. 1, and the input section 11 will be described first. As shown in FIG. 3, the input unit 11 includes segment signal input circuits 211 to 214. The segment signal input circuit 211 has input terminals 0 to 7 to which segment signals are supplied, control terminals INH, A, B, C, and an output terminal CO.
Equipped with M. Each segment signal input circuit 212-214
The specific configuration of is similar to that of the segment signal input circuit 211.

The segment signals S1 to S8 are supplied to the input terminals 0 to 7 of the segment signal input circuit 211, respectively. In addition, the segment signal input circuits 212-2
Similarly, the segment signals S9 ...
S32 is supplied. Segment signal input circuit 211-
When the control terminal INH is at low level, 214 outputs from the output terminal COM an input signal having a number indicated by a 3-bit signal supplied to the control terminals A to C. When the control terminal INH is at high level, the segment signal input circuits 211-2
The output terminal COM of 14 is in an open state.

Next, as shown in FIG. 4, the first selection circuit 14 has four comparators 216a to 216d, simulator trigger inverters 217a to 217f, and resistors 400a to 400a.
It has 400d, 14a to 14c, and a decoder 218.

The resistors 14a to 14c are 10 KΩ each,
It is connected in series between the power supply voltage VDD and the ground voltage GND, and divides the voltage VDD into three. Therefore, the voltage of 2 / 3V is applied to the positive input terminals of the comparators 216a and 216c.
DD is supplied to the comparators 216b, 216
The voltage 1/3 VDD is supplied to the positive input terminal of d.

The common signal COM1 is supplied to the positive input terminals of the comparators 216a and 216b. The common signal COM2 is supplied to the negative input terminals of the comparators 216c and 216d. The potentials of the common signals COM1 and COM2 are either 0, 1/2 VDD, or VDD, and the common signal COM1 and the common signal COM2 have opposite phases.

Comparators 216a, 216b, 216
The output terminals of c and 216d are connected to the input terminals of the corresponding Schmitt trigger inverters 217a, 217b, 217d and 217e and the one ends of the corresponding resistors 400a to 400d. The other ends of the resistors 400a to 400d are grounded. The output end of the Schmitt trigger inverter 217b is connected to the input end of the Schmitt trigger inverter 217c. The output end of the Schmitt trigger inverter 217e is connected to the input end of 217f. The decoder 218 changes the corresponding one of the output terminals S1_, S2_, S4_, and S8_ to low level only when there is one high-level input signal.

The control circuit 19 includes a binary counter 219.
a to 219d and NOR gates 220a to 220d. The binary counter 219a has a clear terminal CL,
It has a clock control terminal CK and an output terminal QD. The binary counters 219b to 219d are binary counters 2
It has the same configuration as 19a. Binary counter 219a-
Each clear terminal CL of 219d is connected to the output terminals S1_, S2_, S4_, and S8_ of the decoder 218.

The first input ends of the NOR gates 220a to 220d are connected to the output terminals QD of the corresponding binary counters 219a to 219d. NOR gate 220a-
The second input terminal of 220d is connected to the corresponding output terminals S1_, S2_, S4_, and S8_ of the decoder 218.

FIG. 5 shows the oscillator 12, the second selection circuit 13,
Details of the signal generation circuit 15 and the determination circuit 18 are shown. The output signal of the oscillator 12 having an oscillation frequency of 7.2 KHz is supplied to the binary counter 16 that controls the operation and operation timing of each unit via the inverter 227.

The signal generation circuit 15 includes a binary counter 1
6, an inverter 226, an AND gate 223, a comparator 17b, and a DIP switch 17a. The binary counter 16 is a 12-stage binary counter, and includes a clock input terminal CK and output terminals Q4 to Q12.

The output terminal Q11 of the binary counter 16 outputs a strobe signal STB (control signal for designating reading of data DATA). The output terminal Q11 is the input terminal of the inverter 226, and the output terminal Q4 is the AND gate 2.
23 is connected to the second input terminal. Inverter 22
The output terminal of 6 is connected to the first input terminal of the AND gate 223.

The comparator 17b is a 4-bit magnitude comparator, and compares the 4-bit signal generated by the binary counter 16 and the DIP switch 17a. That is, the comparator 17b compares the signals supplied to the input terminals A0 to A3 and the signals supplied to the input terminals B0 to B3, and as a result of the comparison, the input terminals A0 to A3.
When the value indicated by the signal supplied to the signal No. 3 is the same as or smaller than the value indicated by the signal supplied to the input terminals B0 to B3,
The enable signal ENA is output from the output terminal E1 of the comparator 17b. Also, the input terminals A3, A2, A1,
A0 is the output terminal Q8 of the corresponding binary counter 16,
It is connected to Q7, Q6, and Q5. DIP switch 1
The 7a and the comparator 17b set the ratio (duty) of the time when the LED 101 is on and the time when the LED 101 is off.

The second selection circuit 13 includes a binary counter 1
6 to receive the signal from the segment signal input circuit 211-
Any one of 214 is selected. The second selection circuit 13 has input terminals A and B and output terminals Q0 to Q3.
Is equipped with. Output terminals Q0-Q of the second selection circuit 13
3-corresponding segment signal input circuits 211-214
Is connected to the control terminal INH.

The discrimination circuit 18 includes a discrimination unit 18a, inverters 224 and 225, and NAND gates 221a to 221c.
Have. The determination unit 18a uses the input terminals KB, KA, A1,
B1, A2, B2 and output terminals D1, D2 are provided. The input terminal KB of the determination unit 18a is the segment signal input circuit 2
The output terminals COM of 11 to 214 are connected to each other, and the input terminal KA is connected to the output terminal of the inverter 224. Input terminals A1, B1, A2, B2 of the determination unit 18a
Are connected to the output terminals of the corresponding NOR gates 220a to 220d.

The output terminals D2 and D1 of the discriminator 18a are connected to the second input terminals of the NAND gates 221a and 221b, respectively. NAND gates 221a and 221b
The first input terminals of the are connected to the output terminal Q5 of the binary counter 16 and the output terminal of the inverter 225, respectively. The input terminal of the inverter 225 is the binary counter 1
6 is connected to the output terminal Q5. Nand gate 22
The output terminals of 1a and 221b are NAND gates 22 respectively.
1c is connected to the first input terminal and the second input terminal.

The output unit 20 shown in FIG. 6 will be described.
In the present embodiment, eight serial-parallel converters connected in series are used as the output section 20, but in FIG. 6, only the output circuits 31 to 35 are described, and the others are omitted.

The output circuit 31 includes control terminals STB, CK,
Output enable terminal OE, serial input terminal SIN,
It has output terminals Q1 to Q8 and an output terminal QS. The output terminals Q1 to Q8 of the output circuits 31 to 35 are LED1 respectively.
01, and the cathode of each LED 101 is grounded.

The segment signal supplied to the display conversion device 100 is 32 bits, the common signal is 2 bits, and the output signal is 64 bits of serial data. In order to output the 64-bit output signal, eight output circuits equipped with eight LEDs are connected in series.

Data indicating ON / OFF of the display pixel is serially supplied from the discrimination circuit 18 to the input terminal SIN of the output circuit 31. Strobe control terminal ST of output circuit 31
The strobe signal STB from the output terminal Q11 of the binary counter 16 is supplied to B. The clock signal CK is supplied from the AND gate 223 to the clock input terminal CK. The output control terminal OE has a comparator 17
The enable signal ENA is supplied from b. Next, the operation of the display conversion device having the above configuration will be described with reference to FIGS.

First, segment signals S1 to S32 are supplied in parallel from the LCD driving unit to the input terminals of the segment signal input circuits 211 to 214. The segment signals S1 to S32 are output to the output terminal Q6 of the binary counter 16.
~ Q10 (FIGS. 7 (c) to (g)) are used to serially capture the signals in the circuit.

More specifically, the binary counter 1
Immediately after starting the counting operation of 6, output terminals Q9 and Q1
0, that is, the input signals of the input terminals A and B of the second selection circuit 13 are both low level as shown in FIGS. 7 (f) and 7 (g). Therefore, the output Q of the second selection circuit 13
0 ￣ becomes low level, outputs Q1 ￣ to Q3 ￣ become high level, and these are segment signal input circuits 211 to 214.
Is supplied to the input terminal INH. As a result, the segment signal input circuit 211 is set to the selected state, and the segment signal input circuits 212 to 214 are set to the non-selected state.

[0033] As shown in FIG. 7 (c) ~ (e) , initially, since all the output terminals Q6~Q8 of the binary counter 16 is a low level, by which is supplied to the control terminal A~C
The null signal is “0”, and the segment signal input circuit 21
1 selects the segment signal S1 and outputs it from the output terminal COM. At this time, the output terminals COM of the segment signal input circuits 212 to 214 in the non-selected state are in the open state.

At the next timing, the binary counter 1
The output Q6 of 6 becomes high level, and the segment signal input circuit 211 selects and outputs the segment signal S2.
Thereafter, in response to the count-up of the binary counter 16, the segment signal input circuit 211 causes the segment signal S
3 ... S8 is sequentially selected and output.

When the segment signal S8 is selected, then the output terminal Q9 of the binary counter 16 becomes high level, and the second selection circuit 13 causes the segment signal input circuit 2 to operate.
Select 12. After that, the same operation is repeated, and the segment signals S9 ... S32 are sequentially selected and output.

The segment signals S1 to S output from the output terminals COM of the segment signal input circuits 211 to 214.
32 is supplied to the input terminal KB of the determination unit 18a, and the inverted signal thereof is supplied to the input terminal KA.

On the other hand, when the common signal COM1 is at the VDD level, the common signal CO is applied to the input terminal A1 of the discriminator 18a.
A high level signal is supplied to the input terminal B1 when M1 is at the GND level, a high level signal is supplied to the input terminal A2 when the common signal COM2 is at the VDD level, and a high level signal is supplied to the input terminal B2 when the common signal COM2 is at the GND level.

More specifically, for example, the comparator 216a shown in FIG.
VDD / 3 and common signal CO supplied to the second input end
The voltages of M1 are compared, and when the common signal COM1 is VDD, a low level signal is output, and as a result, the decoder 2
A high level signal is supplied to the input terminal A of 18 and the decoder 218 sets the output terminal S1 to low level.

The low level signal output from the output terminal S1 of the decoder 218 is the second signal of the NOR gate 220a.
Input terminal and the clear terminal CL of the binary counter 219a
And the binary counter 219a is supplied to the control terminal CK.
The count of the clock signal supplied to is started.

The output terminal QD is switched to the low level until the binary counter 219a counts 8 clocks after S1 is switched to "L", and the output terminal QD is switched from the output end of the NOR gate 220a to the input terminal A1 of the discriminating portion 18a to the high level. Signal is supplied. Comparators 216b to 216d, a decoder 218, binary counters 219b to 219d, and NOR gates 220b to 220 shown in FIG.
d operates similarly.

Here, the binary counters 219a to 219a
9d is used because the levels of the common signals COM1 and COM2 may change during the data set of the segment signal.

From this, the discriminator 18a determines that the input terminal K
B, KA and the signals supplied to the input terminals A1, B1, A2, B2 are used to generate data DATA indicating ON / OFF of the display pixel of the LCD.

Specifically, the discriminating unit 18a determines whether the segment signals supplied from the segment signal input circuits 211 to 214 are at a low level and the common signal COM1 is VDD (the output of the NOR gate 220a is at a high level), and Signal is high level and common signal COM1 is GN
In the case of the D level (the output of the NOR gate 220b is at the high level), the output terminal D1 outputs a high level signal indicating that the pixel is turned on. Similarly, the determination unit 18a determines whether the segment signal supplied from the segment signal input circuits 211 to 214 is low level and the common signal COM2 is VDD (the output of the NOR gate 220c is high level) and the segment signal is high level. Common signal COM2 is GN
In the case of the D level (the output of the NOR gate 220d is at the high level), the output terminal D2 outputs a high level signal indicating that the pixel is turned on.

The NAND gates 221a and 221b are connected to the output terminal Q5 of the binary counter 16 and the inverter 22.
The output signal of 5 alternately opens the gate. That is, the NAND gates 221a to 221c and the inverter 22 shown in FIG.
5 responds to the output terminal Q5 of the binary counter 16,
The output terminals D1 and D2 of the determination unit 18a, which are output in parallel, are switched to output serially.

DIP switch 17a and comparator 1
The enable signal ENA for controlling the lighting time of the LED 101 is generated by 7b. Specifically,
The comparator 17b uses the data on the A side (input terminals A0 to A).
3) signal and B side data (input terminal B0
(Signals supplied to B3 to B3) are compared, and when A ≦ B (the value on the B side is equal to or more than the value on the A side), the high-level enable signal ENA is output. The value on the A side is about 2.22μ
The value of 0 to 15 is repeated for each s. Therefore, for example, when the set value of the DIP switch 17a is set to "15", the enable signal ENA is always at the high level,
When set to "8", the enable signal ENA is about 17.77.
High or low level data is repeated every μs.

The output terminal Q11 of the binary counter 16 functions as the strobe signal STB of the output circuit 20.
Further, as shown in FIGS. 7A and 7B, the output terminal Q4 of the binary counter 16 has the strobe signal ST
It is gated by B and is supplied to the output circuit 20 as the read clock signal CK only when the strobe signal STB is at the low level. When the strobe signal STB is at the low level, the data DATA output from the determination circuit 18 and indicating the on / off state of the display pixel is sequentially shifted and fetched in accordance with the timing of the clock signal CK.
When 64 pulses of the clock signal CK are supplied to the output circuit 20, the strobe signal STB becomes high level,
The clock signal CK is fixed at low level. In this state, when the high-level enable signal ENA is supplied from the comparator 17b to the output enable terminal OE, the data DATA held by the output circuits 31 to 39 (however, the output circuits 36 to 39 are not shown) are stored. LED101
And the LED 101 lights up. On the other hand, when the enable signal ENA is low level, the output circuits 31 to 39
Since the output terminal of is in an open state, no current flows through the LED 101 and the LED 101 is extinguished.

As described above, the circuits shown in FIGS. 1 and 2 receive the segment signal supplied in parallel to the input section 11 and the common signal supplied in parallel to the first selection circuit 14 to receive the common signal. Display pixel on / off
Data DATA indicating OFF is generated, and this data DAT
A is serially supplied to the output unit 20. Therefore, the number of cables required to connect the display conversion device and the LED display unit can be reduced, and the display conversion device and the LED display unit can be easily separated (attached / detached). In addition, the number of connection cables for the display section configured by the LEDs can be reduced, and the LED display section can be made compact.

[0048]

By serially supplying a signal indicating ON / OFF of the display pixel from the LCD / LED conversion device to the LED display unit, the LCD / LED conversion device and the LED display unit can be easily separated. In addition, the LCD / LED conversion device and the LED display unit can be easily separated, and the number of connecting cables for the display unit configured by the LEDs can be reduced, so that the display unit can be reduced in weight and size.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a display conversion device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of the display conversion device shown in FIG.

FIG. 3 is a diagram showing a specific configuration of an input unit shown in FIG.

FIG. 4 is a diagram showing details of a first selection circuit and a control circuit of the display conversion device shown in FIG.

5 is a diagram showing details of an oscillator, a second selection circuit, a signal generation circuit, and a discrimination circuit of the display conversion device shown in FIG.

FIG. 6 is a diagram showing details of an output unit and LEDs shown in FIG.

FIG. 7 is a timing chart showing the operation of the display conversion device according to the embodiment of the present invention.

[Explanation of symbols]

10 ... LCD, 11, 211-214 ... Input section, 12 ...
Oscillator, 13 ... Second selection circuit, 14 ... First selection circuit, 1
4a to 14c, 400a to 400d ... Resistors, 15 ... Signal generation circuits, 16, 219a to 219d ... Binary counters, 17a ... DIP switches, 17b, 216a-21.
6d, 220a to 220d ... Comparator, 18 ... Discrimination circuit, 19 ... Control circuit, 20, 31-35 ... Output unit, 1
00 ... Display conversion device, 101 ... LED, 217a-21
7f ... Schmitt trigger inverter, 218 ... Decoder, 221a-221c ... NAND gate, 223 ... AND gate, 224-227 ... Inverter.

Claims (1)

[Claims] 1. A segment signal input means for serially outputting a segment signal for liquid crystal display supplied in parallel, and a common for receiving a common signal for liquid crystal display and outputting a signal indicating a signal level of the common signal. A signal input unit, receiving a segment signal from the segment signal input unit and a signal indicating the signal level of the common signal from the common signal input unit, and generating a display signal indicating ON / OFF of a display pixel, A display conversion device, comprising: a circuit that serially supplies a display signal to a display device including a plurality of light emitting elements.