JPH05314018A - Information processor - Google Patents

Abstract

PURPOSE:To make it unnecessary to use a special program at the time of transferring data in a main memory to an external storage device and checking whether the data was transferred correctly of not. CONSTITUTION:A buffer memory 13 which reads and stores the data from the data bus 113 when the data is transferred from the main memory 11 to the external storage device through the data bus 113 and an input/output circuit 12, and a comparison circuit 14 which compares the data stored in the buffer memory 13 with the data outputted to the data bus 113 when the data transferred once to the external storage device is read out to the data bus 113 through the input/output circuit 12 immediately after it is stored are provided. The data is read out immediately after it is transferred to the external storage device, and whether it coincides with the data stored in the buffer memory 13 or not is checked by the comparison circuit 14, and at the time of noncoincidence, an alarm signal is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus which connects an external storage device and processes data.

[0002]

2. Description of the Related Art Data stored internally from one of the conventional main memory, the input / output circuit, and the external storage device connected to the main memory and the input / output circuit described above. In the information processing device including the direct memory access control circuit that controls the input / output circuit to transfer the data, when the data stored in the main memory is written to the external storage device via the input / output circuit. In addition, no circuit is provided to check whether the data read from the main memory and the data written in the external storage device match. Therefore, when it is necessary to check whether or not the data transferred from the main memory to the external storage device is properly transferred in this way, the data once written from the main memory to the external storage device is written according to a program created in advance. An area for comparison between the original data stored in the main memory before the data transfer and the main memory according to the program described above, which is read from the external storage device and stored in the comparison storage area prepared in the main memory. It is examined whether or not these data match by comparing with the data stored in.

[0003]

In the above-described conventional information processing apparatus, the data transferred from the main memory and stored in the external storage device is transferred again to the comparison storage area in the main memory and stored therein. In order to compare the data stored in the storage area for comparison with the original data stored in the main memory before transfer by starting a pre-created program, the data is transferred from the main memory to the external storage device. Has a disadvantage that it takes a long time to complete the process of transferring the data and checking whether the transferred data is correctly stored in the external storage device.

An object of the present invention is to provide a buffer memory for temporarily storing data to be transferred at the same time when data is transferred from the main memory to the external storage device, and transfer the data from the main memory to the external storage device. In this case, the data to be transferred is also stored in the buffer memory described above at the same time, and the data is transferred to the external storage device immediately after the data is transferred to the external storage device by the separately provided comparison circuit. And the data stored in the buffer memory are compared to check for a match between these data, and if they do not match, an alarm is output to the outside and whether the data transferred to the external storage device is correct or not Information processing that shortens the time required for checking and eliminates the need to start a program for such checking. To provide an apparatus.

[0005]

According to an information processing apparatus of the present invention, data of a main memory and the main memory output to a data bus is controlled by a write signal to be output to an external storage device for writing and reading signals. An input / output circuit that is controlled to read data stored in a designated storage area of the external storage device and output the data to the data bus; and a first data transfer from the main memory to the external storage device. When the write signal and the data are read one by one, the data stored in the address of the main memory designated by the first transfer instruction is read out and the write signal and the data are read one by one. Before receiving a second transfer command for outputting and transferring the data stored in the external storage device to the main memory 1 Data outputs the read signal
A control is performed to output a synchronization signal each time the data is read individually, read the data in the external storage device by the input / output circuit, output the data to the data bus, and store the data output to the data bus in the main memory. In an information processing device having a direct memory access control circuit, a data output from the main memory is synchronized with the synchronization signal at an address corresponding to a counter value input when a storage start command is received, and the data bus is transferred to the data bus. When a comparison start signal is received through a buffer memory that reads and stores the data, the data output to the data bus and the data in the buffer memory are read and compared in synchronization with the synchronization signal. And a counter circuit that outputs a counter initial value when this counter value is received as the counter value. A counter that outputs a value obtained by adding 1 to the initial value each time the synchronization signal is input, and outputs the first and second transfer instructions and outputs the first transfer instruction. When outputting, the storage instruction and the counter initial value are output, and when the processing by the transfer instruction is completed, the second transfer instruction is continuously output, and the second transfer instruction is subsequently issued after the first transfer instruction. Is output only when outputting the comparison start signal and the counter initial value, and outputs the alarm signal to the outside when the alarm signal is received.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention.

As shown in FIG. 1, the information processing apparatus of this embodiment includes a main memory 11 and an input / output circuit 12 connected to the main memory 11 by a data bus 113 and connected to an external storage device. When a first transfer command for transferring data from the main memory 11 to the external storage device and a second transfer command for transferring data from the external storage device to the main memory are received via the signal line 107, the transfer command is designated in these transfer commands. The generated address value is output to the main memory 11 or the input / output circuit 12 via the address bus 112, and when the first transfer instruction is received, the synchronizing signal is output and the write instruction is output to the input / output circuit 12, and the second Direct memory access control circuit 1 that outputs a read command to input / output circuit 12 when a transfer command is received, and outputs a synchronization signal
5, when the counter initial value is received, the counter initial value is output as a counter value, and thereafter, each time the synchronization signal is received from the direct memory access control circuit 15, a value obtained by adding 1 to the counter initial value is counted. When the counter 16 that outputs the value and the storage start signal are received, the data bus is sent to the address corresponding to the counter value output from the counter 16 in synchronization with the synchronization signal output from the direct memory access control circuit 15 described above. 1
Buffer memory 13 for reading and storing data on 13
When the comparison start signal is received, the data output from the input / output circuit 12 to the data bus 113 is read in synchronization with the above-mentioned synchronizing signal, and the counter value output from the counter 16 from the buffer memory 13 is designated by the counter value. A comparison circuit 14 that compares the data stored in the address and outputs an alarm signal when there is a mismatch between these data.
And the above-mentioned first and second transfer instructions, a storage start signal,
An arithmetic processing circuit 1 is provided which outputs a comparison start signal and a counter initial value and, when the above alarm signal is received, transfers this signal to the outside.

When transferring data from the main memory 11 to the external storage device via the input / output circuit 12, the arithmetic processing circuit 1 specifies an address in the main memory 11 and an address of a storage area in the external storage device of the transfer destination. The number of transfers is calculated from the first transfer command and the length of the data to be transferred, and the number of transfers is output to the direct memory access control circuit 15 via the control line 107. At this time, the arithmetic processing circuit 1 outputs a storage start signal to the buffer memory 13 and also outputs a predetermined counter initial value to the counter 16.

When the direct memory access control circuit 15 receives the first transfer command, it increments the address from the designated address in the main memory 11 a designated number of times and reads the data stored at the corresponding address as read data. Output to the bus 113. Further, the direct memory access control circuit 15 outputs a write signal to the input / output circuit 12 at the same time and controls the external storage device to store the data output to the data bus 113 in synchronization with the synchronous signal output at the same time. To do. At this time, since the counter initial value is added to the counter 16 from the arithmetic processing circuit 1, the input counter initial value is output to the buffer memory 13 as the counter value, and thereafter, the synchronization output from the direct memory access control circuit 15 is performed. Every time a signal is applied, a value obtained by adding 1 to the counter initial value is output as the counter value.

Since the storage start signal is output from the arithmetic processing circuit 1 to the buffer memory 13 and the counter value is added from the counter 16, the buffer memory 13 inputs the counter in synchronization with the above-mentioned synchronization signal. The data on the data bus 113 is sequentially written to the address corresponding to the value. When the data transfer from the main memory 11 to the external storage device is completed in this way, the same data is stored in the buffer memory 13.

The arithmetic processing circuit 1 is set so as to output the first transfer instruction and, when the data transfer by this transfer instruction is completed, subsequently output the second transfer instruction.

However, when the second transfer command is output, the information processing device having such an arithmetic processing circuit 1 needs to transfer the data stored in the main memory 11 to the external storage device. The first transfer command is not continuously output unless it is present.

When the arithmetic processing circuit 1 outputs the second transfer instruction subsequent to the first transfer instruction, it also outputs the comparison start instruction and the counter initial value at the same time.

The above-mentioned second transfer instruction includes the address of the external storage device to be read, the address of the transfer destination, and the number of times of data transfer.

Upon receiving the second transfer command, the direct memory control circuit 15 applies a read signal to the input / output circuit 12 to read the data from the external storage device and output the data to the data bus 113 to cause the main memory 11 to read. This data is written into the data bus 113. At this time, the comparison start signal is output from the arithmetic processing circuit 1 to the comparison circuit 14 and the counter initial value is added to the counter 16. The above data and the data in the address corresponding to the counter value output from the counter 16 in the buffer memory 13 are read, and it is checked whether or not these data match. If they do not match, the alarm signal is processed. Output to circuit 1.

Upon receiving the alarm signal, the arithmetic processing circuit 1 transfers this signal to the outside. The data thus transferred and stored from the main memory 11 to the external storage device by the first transfer instruction is stored in the buffer memory 13, and then temporarily stored by the second transfer instruction output from the arithmetic processing circuit 1. The data stored in the external storage device is compared by the comparison circuit 14 with the data before transfer stored in the buffer memory.

The comparison signal is output from the arithmetic processing circuit 1 only when the arithmetic processing circuit 1 outputs the second transfer instruction that is output after the first transfer instruction is output. However, when the second transfer instruction alone is output, the arithmetic processing circuit 1 is set so as not to output the comparison start instruction.

[0019]

As described above, in the information processing apparatus of the present invention, when data is transferred from the main memory to the external storage device, the data to be transferred is also stored in the buffer memory and then transferred. A special program is used for the check because the data is read from the external storage device and the read data is compared with the data stored in the buffer memory by the comparison circuit to check whether the data has been transferred correctly. This makes it possible to check whether or not the data transferred to the external storage device is correct in a shorter time than the time required for such a check by the conventional information processing apparatus of this type. is doing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention.

[Explanation of symbols]

 1 arithmetic processing circuit 11 main memory 12 input / output circuit 13 buffer memory 14 comparison circuit 15 direct memory access control circuit 16 counter

Claims (1)

[Claims] 1. A main memory and data stored in the main memory output to a data bus is controlled by a write signal to be output to an external storage device for writing, and is controlled by a read signal to perform a designated storage in the external storage device. The input / output circuit for reading out the data stored in the area and outputting it to the data bus, and the first transfer when the first transfer instruction for transferring the data from the main memory to the external storage device is added. The data stored in the address of the main memory designated by an instruction is read out and output to the data bus, and when the write signal and the data are read out one by one, a sync signal is output and stored in the external storage device. When the second transfer command for transferring data to the main memory is received, the read signal is output and the data is read one by one. A control is performed to output a sync signal each time the data is read out, read the data in the external storage device by the input / output circuit, output the data to the data bus, and store the data output to the data bus in the main memory. In an information processing device having a direct memory access control circuit, data output from the main memory is synchronized with the synchronization signal at an address corresponding to a counter value input when a storage start command is received, and the data is output via the data bus. Buffer memory to read and store the data, and when the comparison start signal is received, the data output to the data bus and the data in the buffer memory are read out and compared in synchronization with the synchronization signal. When the comparator circuit that outputs and the counter initial value is received, this initial value is output as the counter value. A counter for outputting a one by one a value obtained by adding the initial value every time thereafter the synchronization signal is input as the counter value, the first and second
Of the transfer instruction and the first transfer instruction are output, the storage instruction and the counter initial value are output, and when the processing by the transfer instruction is completed, the second transfer instruction is continuously output and the first transfer instruction is output. An arithmetic processing circuit that outputs the comparison start signal and the counter initial value only when the second transfer instruction is output subsequently to the transfer instruction, and outputs the alarm signal to the outside when the alarm signal is received. An information processing apparatus comprising: