JPH0531969B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bridged tap equalizer for equalizing echo waveforms generated in a communication line having a bridged tap.

[Conventional technology]

An example of the configuration of a conventional bridged tap equalizer of this type is shown in FIG. This circuit shown in FIG. 3 is a bridged tap equalizer called a decision feedback type. Moreover, FIG. 4 shows the waveforms of various parts when the number of taps is 2. The operation of the conventional bridged tap equalizer will now be described with reference to FIGS. 3 and 4.

Assume that a signal e _i having echoes one time slot and two time slots after the main signal is applied to the first input of the two-input analog adder 10. These echoes are canceled by a two-input analog adder 10 by an echo cancel signal e _a , which will be described later.
An equalized output e ₀ is obtained from the output of the input analog adder 10. Comparators 11 to 15 use this equalized output e ₀
are compared with different reference voltages (comparators 11 to 15 respectively compare with reference voltages +V _ref , +1/2 V _ref , 0, 1/2 V _ref , -V _ref ), data identification, zero cross discrimination, and peak Perform value discrimination.

The digital control circuit 16 is a clock (CLK)
The comparators 11 to 11 are driven by
Based on the output of 15, it is determined whether the equalized waveform is over-equalized or under-equalized, that is, whether the echo cancel waveform is too large or too small, and in the case of over-equalization, the accumulation coefficient is decreased; In case of under-equalization, increase the accumulation coefficient. The digital control circuit 16 performs the above operation for the echo after one time slot and the echo after two time slots of the main signal, obtains two coefficients, and simultaneously calculates the coefficients accumulated after one time slot and two time slots after the main signal. Output the coefficients of Q ₁ to Q ₆ . The output P of the digital control circuit 16 is a signal that determines the polarity of the echo cancel signal, and is output simultaneously with _Q1 to _Q6 .

The D/A converter 17 D/A converts the outputs Q ₁ to Q ₆ and P of the digital control circuit 16, and outputs a rectangular wave.
get e _d . The output of this D/A converter 17 is resistor R
The signal is shaped into a triangular wave by a first-order low-pass filter composed of a capacitor C and a capacitor C, and as a result, an echo cancel signal e _a is obtained. This echo cancel signal is fed back to the two-input analog adder 10, and the input signal
e Cancel the echo of _i .

[Problem that the invention seeks to solve]

By the way, when attempting to implement the conventional bridged tap equalizer described above using LSI, the resistance and capacitance that constitute the first-order low-pass filter require a large area. In particular, there is a problem in that the size becomes unrealizable at low bit rates of 64 kBPS or less.

An object of the present invention is to provide a bridged tap equalizer that can be implemented in LSI and can also generate echo cancel signals at low bit rates.

[Means for solving problems]

The present invention includes a two-input analog adder whose first input is a received signal transmitted through a communication path having a bridged tap, a smoothing filter whose input is the output of the two-input analog adder, and an output of the smoothing filter. a plurality of comparators to which a common input is input to a first input terminal and different reference voltages are respectively input to a second input terminal; and a digital control circuit which outputs a coefficient signal and a control signal based on the outputs of the plurality of comparators. , a plurality of first analog switches in which a plurality of binary-weighted capacitors are connected in series, and two second analog switches to which positive and negative reference voltages are respectively input. a low-pass filter, the first analog switch being controlled by the coefficient signal, and the second analog switch being controlled by the control signal;
The bridged tap equalizer is characterized in that the output of the switched capacitor low-pass filter is fed back to the second input of the two-input analog adder to obtain an equalized waveform from the output of the smoothing filter.

〔Example〕

FIG. 1 shows an embodiment of a bridged tap equalizer according to the present invention, and shows a decision feedback type bridged tap equalizer similar to the conventional example.

Referring to FIG. 1, 1 is a two-input switch capacitor adder, 2 is a smoothing filter, 3 to
7 is a comparator, 8 is a digital control circuit, 9
is an operational amplifier, S ₁ to _{S 12} are analog switches, _Cu
is the unit capacitance, _Cs is the integral capacitance, CLK is the data rate clock, φ is the switch capacitor filter (SCF) clock, and the frequency of φ is
The frequency shall be sufficiently higher than that of CLK.

FIG. 2 shows waveforms of various parts when the number of taps is 2. In Figure 2, CLK is the data rate clock, e _i is the input waveform with echo waves,
P1, P2 and Q ₁ to _{Q 6} are digital control circuit outputs,
e _a is the echo cancellation signal, e _s is the adder output, e _O
indicates the equalized waveform.

1 and 2, one of the main signals is connected to the first input of the two-input switch capacitor adder 1.
If a signal e _i with echoes is added after the time slot and after two time slots, the echoes are processed by adder 1 as an echo cancel signal, which will be described later.
The output signal _{e s is} obtained from the output of adder 1. This output signal e _s is then smoothed by smoothing filter 2 to produce an equalized output.
e becomes _O.

The output signal e _O from the smoothing filter 2 is input to the comparators 3 to 7, and the comparator 3
Comparator 4 determines the positive side peak level (+V _ref ) of signal e _O , Comparator 5 determines the polarity of signal e _O , Comparator 6 determines the positive data of signal e O, that is, "1", Comparator 6 determines the polarity of signal e _O The comparator 7 determines the negative data of _eO , that is, "-1", and determines the negative peak level ( _-Vref ). The output of comparators 3 to 7 is the clock (CLK) shown in Figure 2.
The signal is inputted to a digital control circuit 8 driven by .

This digital control circuit 8 has functions of accumulating tap coefficients and controlling the output of a cancel signal, and determines whether the equalized waveform output (e _O ) is over-equalized or under-equalized according to the outputs of the comparators 3 to 7. Is there?
That is, it is determined whether the echo cancel waveform is too large or too small, and in the case of over-equalization, the coefficient is decreased, and in the case of under-equalization, the coefficient is increased.
The above control operation is performed for the echo after one time slot and the echo after two time slots of the main signal, and two coefficients are obtained, namely, a coefficient corresponding to the echo after one time slot and a coefficient corresponding to the echo after two time slots. get. At the same time, the digital control circuit 8 converts the respective coefficients accumulated after one time slot and two time slots of the main signal into Q ₁
~ Output to Q ₆ (coefficient signal). On the other hand, the digital control circuit 8 outputs signals P ₁ and P ₂ (control signals) that determine the polarity of the echo cancel signal.

As shown in the figure, a switched capacitor low-pass filter (hereinafter simply referred to as SCF), which is composed of analog switches S ₁ to S ₁₂ , a plurality of capacitors, and an operational amplifier 9, is controlled by outputs Q ₁ to Q ₆ of a digital control circuit 8. be done. This SCF is of variable gain type and has a function of generating an echo cancel signal. Further, this SCF corresponds to the D/A converter and low-pass filter portion used in the conventional bridged tap equalizer described above. Reference voltages +V _ref and -V _ref connected by analog switches S ₁ and S ₂ controlled by outputs P 1 and P 2 from the digital control circuit 8 serve as inputs to the variable gain SCF.

Each analog switch S ₁ and S ₂ is "on" when the signal applied thereto is high level, and "off" when the signal applied to it is low level. Now, if timings P1 and P2 as shown in Fig. 2 are applied to analog switches _S1 and _S2 , the input of the aforementioned variable gain type SCF has an amplitude of +V _ref or -V ref and a width of +V _ref . _P1 , _P2
A square wave equal to the pulse width of is added, resulting in
A waveform like the one shown in Figure 2 e _a appears in the SCF output. At this time, the amplitude of the output _ea is controlled by the outputs Q ₁ to _{Q 6} of the digital control circuit 8, and has a value proportional to each tap coefficient. After this echo cancel signal is added to the input signal in adder 1, the signal e _s
and smoothing filter 2 to obtain an equalized waveform e _O.

Note that the smoothing filter 2 is necessary because the adder and the echo cancel signal generating section are constituted by a switch capacitor circuit.

〔Effect of the invention〕

As explained above, according to the bridged tap equalizer of the present invention, by configuring the echo cancel signal generating section with a variable gain switched capacitance low pass filter, a low pass filter with low cutoff characteristics can be created without using external components.
It can be realized on LSI, and since the amplitude of the echo cancel signal can be varied by changing the gain, the D/A converter that was conventionally required is also unnecessary. Therefore, the bridged tap equalizer according to the present invention is suitable for LSI implementation, and has the effect of realizing LSI implementation with a small occupied area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a bridged tap equalizer according to the present invention, FIG. 2 is a diagram showing waveforms of various parts of FIG. 1, and FIG. 3 is a block diagram of a conventional bridged tap equalizer. FIG. 4 is a diagram showing waveforms at various parts in FIG. 3. 1...2 input switch capacitor adder, 2
...Smoothing filter, 3 to 7...Comparator, 8...Digital control circuit, 9...Operation amplifier, _S1 to _S12 ...Analog switch, Cu...Unit capacitance, _{Cs ...} Integral capacitance, CLK ...Clock, φ
... SCF clock, 10 ... 2-input analog adder, 11 to 15 ... Comparator, 16 ... Digital control circuit, 17 ... D/A converter, R ...
Resistance, C... Capacity.

Claims (1)

[Claims] 1 A two-input analog adder whose first input is a received signal transmitted through a communication path having a bridged tap; a smoothing filter whose first input is the output of the two-input analog adder; is commonly input to the input end of
a plurality of comparators each receiving a different reference voltage at a second input terminal; a digital control circuit outputting a coefficient signal and a control signal based on the outputs of the plurality of comparators; and a plurality of binary-weighted capacitors. a plurality of first
an analog switch, and a switched capacitor low-pass filter comprising two second analog switches to which positive and negative reference voltages are respectively input, the first analog switch being controlled by the coefficient signal. , the second analog switch is controlled by the control signal to feed back the switched capacitor low-pass filter output to a second input of the two-input analog adder;
A bridged tap equalizer characterized in that an equalized waveform is obtained from the output of the smoothing filter.