JPS6235722A - Bridged tap equalizer - Google Patents

Abstract

PURPOSE:To obtain a low-pass filter which has low cut-off characteristics on an LSI without any external parts by feeding the output of a switched capacitor low-pass filter to the 2nd input of a two-input analog adder and obtaining an equalized waverform from the output of a smoothing filter. CONSTITUTION:Analog switches S1 and S2 turn on when signals applied to them are at a high level and turn off when at a low level. For example, when P1 and P2 are applied to the analog switches S1 and S2, a rectangular wave which has an amplitude +Vref or -Vref equal to the pulse width of the P1 and P2 is applied to the input of a variable gain SCF, and consequently a waveform shown by ea appears at the output of the SCF. At this time, the amplitude of the output ea is controlled with outputs Q1-Q6 of a digital control circuit 8 to obtain values proportional to respective tap coefficients. This echo canceling signal is added to the input signal by an adder 1 and a signal es is passed through the smoothing filter 2 to obtain an equalized waveform e0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bridged tap equalizer that performs equalization of echo waveforms generated in a communication line that has a bridged tap.

[Conventional technology]

A configuration example of a conventional bridged tap equalizer of this type is shown in the third example.
As shown in the figure. This circuit shown in Figure 3 uses a bridged tap equalizer called a decision feedback type to chill.

Moreover, FIG. 4 shows waveforms of various parts when the number of taps is 2. Here, with reference to FIG. 3 and 1st I71, the operation of the conventional presode tap equalizer O15 will be explained.

Assume that a signal ei having echoes is added to the 10th input of the two-operated analog adder 10 one time slot and two time slots after the main signal. These echoes are processed by a two-man analog adder 10 to generate an echo cancellation signal e, which will be described later.
a, and an equalized output eo is obtained from the output of the two-man analog adder 10. Comparators 11 to 15 receive this equalized output e.

Compare each with different reference voltages,
Performs zero cross discrimination and peak value discrimination.

The digital control circuit 16 is driven by a clock (CLK) and has the functions of accumulating tap coefficients and controlling the output of a cancel signal, and superequalizes the 2-equalized waveform by the outputs of the converters 11 to 15. It is determined whether the echo cancellation waveform is too large or too small, and in the case of t-de-energization, the accumulation coefficient is completely decreased, and in the case of insufficient equalization, the accumulation coefficient is increased. Digital control circuit 1
6 performs the above operation for the echo after one time slot of the main signal and the echo after two time slots to obtain two coefficients, and at the same time calculates the respective coefficients eQt accumulated after one time slot and after two time slots of the main signal. ~Q6
Output to. The output P of the digital control circuit 16 is a signal that determines the polarity of the echo cancellation signal.
output at the same time.

The D/A converter 17 outputs the output Q1 of the digital control circuit 16.
Q6 and P'i are subjected to D/A conversion to obtain a rectangular wave output ed.

The output of this D/A converter 17 is shaped into a triangular wave by a first-order low-pass filter composed of a resistor R and a capacitor C, and as a result, an echo cancellation signal ea is obtained. This echo cancellation signal is fed back to the two-man analog adder 10 to cancel the echo of the input signal ei.

[Problem that the invention seeks to solve]

By the way, the conventional bridged tap equalizer mentioned above is
When trying to realize it with I, it is especially important to use a first-order low-i4 low-pass filter, which is characterized by a large area of resistance and capacitance.
There is a problem that the size becomes unrealizable at a low bit rate of 4 kBPS or less.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bridged tap equalizer that can be implemented in an LSI and can also generate an echo cancellation signal at a low bit rate.

[Means to solve all problems]

The present invention includes a two-input analog adder whose first input is all received signals transmitted through a communication path having bridged taps;
a smoothing filter that receives the output of the two-input analog adder; and a plurality of smoothing filters that have the output of the smoothing filter input in common to a first input terminal and different reference voltages input to second input terminals. a comparator; a digital control circuit that outputs a coefficient signal and a control signal based on the outputs of the plurality of comparators; a plurality of first analog switches each having a plurality of binary-weighted capacitors connected in series; a switched capacitor load filter comprising two second analog switches each receiving a negative reference voltage;
an analog switch is controlled by the coefficient signal, and a second analog switch is controlled by the control signal.

The bridged tap equalizer is characterized in that the output of the switched capacitor low-pass filter is returned to the second input of the two-input analog adder to obtain an equalized waveform from the output of the smoothing filter. .

〔Example〕

FIG. 1 shows an embodiment of a bridged tap equalizer according to the present invention, and shows a decision feedback type bridged tap equalizer similar to the conventional example.

Referring to FIG. 1, 1 is a two-input Swiss capacitor adder, 2 is a smoothing filter, 3 to 7 are comparators, 8 is a digital control circuit, 9 is an operational amplifier, and S! ~
S12 is an analog switch.

Cu is the unit capacitance IC, CLK is the integral capacitance, CLK is the data rate clock, φ is the switched capacitor filter (SCF) clock, and the frequency of φ is CLK.
It is assumed that the frequency is sufficiently higher than that of .

FIG. 2 shows waveforms of various parts when the number of taps is two. In FIG. 2, CLK is the data rate clock and ei is the input waveform with echo waves.

PI, P2 and Q1 to Q6 digital control circuit output t
ea is the echo cancellation signal, and e8 is the adder output.

eo indicates an equalized waveform.

Referring to Figures 1 and 2, the 2-input switched carrier
If a signal ei having echoes after one time slot and two time slots after the main signal is added to the first input of the adder 1, these echoes are canceled by the adder 1 by an echo canceling signal ea, which will be described later. , an output signal es k is obtained from the output of adder 1. This output signal e8 is smoothed by a smoothing filter 2 and is equalized as an output e. becomes.

Output signals e from the smoothing filter 2 are supplied to the controllers 3 to 7. is input, and commutator 3 receives signal e.
. Determine the positive peak level (+v, el) of .

Comparator 4 receives signal e. The converter 5 outputs a signal e to determine the positive data, that is, ``1''. polarity determination.

Comparator 6 receives signal e. The comparator 7 determines the negative data, i.e., chir-IJ, at the negative peak level "ref".
). The outputs of the controllers 3 to 7 are input to a digital control circuit 8 driven by a clock (CLK) shown in FIG.

This digital control circuit 8 has a function 2 of accumulating tap coefficients and controlling the output of a cancel signal, and has 2 comparators 3 to 3.
Based on the output of step 7, it is determined whether the 1-equalized waveform output (eo) is over-equalized or under-equalized, that is, whether the echo cancellation waveform is too large or too small. reduces the coefficients in total and increases them in case of under-equalization. The above control operation is performed for the echo after one time slot of the main signal and the echo after two time slots, and
Two coefficients are obtained, namely a coefficient corresponding to the echo after one time slot and a coefficient corresponding to the echo after two time slots. At the same time, the digital control circuit 8 outputs the respective coefficients accumulated after one time slot and two time slots after the main signal to Qr to Q6 (coefficient signals). On the other hand, the digital control circuit 8 outputs a signal P11P2 (control signal) that completely determines the polarity of the echo cancellation signal.

As shown in the figure, analog switches 81 to S1□.

A switched capacitor low pass filter (hereinafter referred to as a single SCF) is composed of a plurality of capacitors and an operational amplifier 9.

) are controlled by the outputs Q1 to Q6 of the digital control circuit 8. This SCF is of a dyne variable type and has a function of generating an echo-cancellation signal. Further, this SCF corresponds to the D/A converter and low-frequency filter portion used in the conventional bridged tap equalizer described above. The analog switch S controlled by the outputs P1 and P2 from the digital control circuit 8, and the reference voltages +V and -"ref connected by S2 become inputs of the variable scale re(SCF).

Each analog switch S and s2 turns on when the signal applied to each is high level, and turns off when the signal applied to it is low level.Now, at the timing shown in Fig. 2, Pl and P2
is applied to analog switches S1 and S2,
The input of the above-mentioned variable type SCF has an amplitude of +■
A rectangular wave whose width is equal to the i4 pulse width of P1yP2 is added to ref or -vref, and as a result, a waveform as shown in FIG. 2a appears at the output of the SCF. At this time, the amplitude of the output ea is controlled by the outputs Q1 to Q6 of the digital control circuit 8, and has a value proportional to each tap coefficient. After this echo cancellation signal is added to the input signal by an adder l, the signal e3 is passed through a smoothing filter 2 to form an equalized waveform e. Get 2.

Note that the smoothing filter 2 is necessary because the adder and the echo canceling signal generating section are constituted by a switch capacitor circuit.

〔Effect of the invention〕

As explained above, according to the bridged tap and other appliances according to the present invention, the echo canceling signal generating section is configured with a variable switched capacitor low pass filter in all keys, so that a low pass filter with a low cutoff characteristic 2 is installed without any external parts. This can be realized on an LSI using the dyne switch, and since the amplitude of the echo cancellation signal can be varied by switching the dynes, there is no need for a D/A converter, which was required in the past.

Therefore, the bridged tap equalizer according to the present invention is suitable for LSI implementation, and has the effect of realizing LSI implementation with a small occupied area.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing Embodiment 2 of a bridged tap equalizer according to the present invention, FIG. 2 is a diagram showing waveforms of each part of FIG. 1, and FIG. 3 is a block diagram of a conventional bridged tap etc. fixture. 4 are diagrams showing waveforms at various parts in FIG. 3. 1: 2-input converter or shift adder, 2: Smoothing filter, 3 to 7: Connogulator. 8: Digital control circuit, 9: Operational amplifier +81~S12
: Analog switch, C, : Unit capacitance, Cs: Integral capacitance, CLK : Clock, φ: SCF clock, 10: 2-input analog adder, 11 to 15: Connoctor, 16: Digital control circuit, 17: D/ A converter, R: resistance, C: capacitance. Fig. 1 φ: Closure clock l-06 for SCF Fig. 3

Claims (1)

[Claims] 1. A two-input analog adder whose first input is a received signal transmitted through a communication path having a bridged tap;
a smoothing filter whose input is the output of the input analog adder; a plurality of comparators whose first input terminals commonly input the output of the smoothing filter; and whose second input terminals each input a different reference voltage; a digital control circuit that outputs a coefficient signal and a control signal based on the plurality of comparator outputs; a plurality of first analog switches each having a plurality of binary-weighted capacitors connected in series; and positive and negative references. a switched capacitor low-pass filter including two second analog switches each receiving a voltage, the first analog switch being controlled by the coefficient signal, and the second analog switch being controlled by the control signal. is controlled by the switched capacitor low-pass filter output to the second
A bridged tap equalizer characterized in that an equalized waveform is obtained from the output of the smoothing filter by returning to a second input of an input analog adder.