JPH05334101A - Strength judging circuit - Google Patents

Abstract

PURPOSE:To provide a circuit superior in expandability and capable of optionally increasing the number of input signals. CONSTITUTION:A strength judging circuit for judging the strength of plural interruptions and selecting which interruption is to be received is provided with plural interruption strength judging sub-circuits 1A to 1C each of which is prepared in each interruption to receive an interruption strength input 5, an overall interruption strength input 10, interruption generation input 18, and a overall interruption generation input 22 and output interruption reception output 25 and an overall interruption generation output 27 and a common circuit 2 for receiving respective outputs 19 from respective sub-circuits 1A to 1C and returning the largest strength value to respective sub-circuits 1A to 1C as an strength input 10. In the case of increasing the number of signals by cascade-connecting respective sub-circuits 1A to 1C, the number of sub-circuits is increased in accordance with the number of signals to be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intensity determination circuit for determining the intensity of a plurality of input signals such as interrupts generated in an interrupt control device and selecting which signal is accepted.

[0002]

2. Description of the Related Art In recent years, digital signal processors (hereinafter referred to as "DSPs") have become higher in performance,
In addition to being used as a processor dedicated to high-speed numerical operation processing for performing high-speed numerical operation required for digital signal processing technology, it is increasingly used as a control processor for controlling an apparatus.

For example, a DSP used in a digital mobile telephone performs a voice input process and the like in addition to a voice encoding process which requires high-speed numerical calculation. There is an interrupt process as a method for realizing such a plurality of processes with one processor without needless processing. Also, a DSP having an interrupt processing capability is generally used. As an example of this, for example, "ADSP-2100
User's Manual ANALOG DEVICES, etc.

[0004]

By the way, in the interrupt processing capability of the conventional DSP, the number of interrupt signals normally accepted is fixed. Even in this case, until now DS
Since P was developed as a general-purpose LSI, there was no problem. However, if the DSP comes to be incorporated in a part of a large LSI as a basic part for performing arithmetic and control of an ASIC (application-specific IC), a larger number of interrupt signals will be connected to the DSP. For this reason, the fixed number of interrupt signals, which has not been a problem in the past, is a serious problem.

That is, if the DSP is designed so that a large number of interrupt signals can be connected from the beginning, wasteful circuits will occur if the number of interrupt signals to be connected is small, which will increase the cost of the DSP. On the contrary, in the case of a design in which the connectable number is small, the number and types of peripheral circuits to be incorporated are limited.

The present invention has been made in view of the above problems, and provides a strength determination circuit with excellent expandability that can arbitrarily expand the number of input signals without fixing the number of input signals such as the number of interrupt signals to be accepted. The purpose is to do.

[0007]

In order to solve the above-mentioned problems, the present invention provides a strength judgment circuit for judging the strength of a plurality of input signals and selecting which of them is to be received. A plurality of sub-strength judgments that are provided and receive the acceptance enable input enable signal, the overall input strength signal, the individual input enable signal and the individual input strength signal, and output the acceptance permission output enable signal, the overall output strength signal and the individual acceptance signal A circuit and a common circuit that receives the overall output intensity signal from each sub-intensity determination circuit and returns a value with the highest intensity as the overall input intensity signal of each sub-intensity determination circuit, each sub-intensity determination circuit, Connect in series so that the acceptance enable output enable signal output from one circuit becomes the acceptance enable input enable signal of the other circuit. Characterized by only the enable state any one of the sub-intensity determination circuit.

[0008]

With the above configuration, in each sub-strength determination circuit, the overall input intensity signal is compared with the individual input intensity signal, and when the individual input intensity signal is large, the acceptance enable input enable signal and the individual input enable signal are input. The input signal is accepted under the condition of, and this individual input intensity signal is output as the overall output intensity signal. At the same time, the reception permission output enable signal is output as a non-permission signal to another sub-strength determination circuit, and an individual acceptance signal for accepting the input is output. If the sizes are opposite, nothing is output.

The overall output intensity signal of each sub-strength determination circuit is input to the common circuit, and the overall output intensity signal of the highest intensity is input to each sub-strength determination circuit as the overall input intensity signal by this common circuit.

As a result, each sub-strength determination circuit can accept only an individual input strength signal having a magnitude larger than the total input strength signal from the common circuit. Therefore, when an individual input intensity signal larger than the overall input intensity signal is input to the other sub-intensity determination circuits, it is input to the common circuit as the overall output intensity signal and is input to each sub-intensity determination circuit as the overall input intensity signal. Due to the input of this overall input intensity signal, the input signal that has been accepted until then is no longer accepted, and instead the large individual input intensity signal is accepted.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, an interrupt strength determination circuit that determines the strength of interrupt processing will be described as an example of the strength determination circuit. FIG. 1 is a block diagram showing an interrupt strength judgment circuit of this embodiment, and FIG. 2 is a logic circuit diagram showing an example of a configuration of a sub-interruption strength judgment circuit.

As shown in FIG. 1, the interrupt strength judging circuit of this embodiment has sub-interrupt strength judging circuits (hereinafter referred to as "sub-circuits") 1A, 1B, ... Provided for each interrupt signal as an input signal. , Each of these sub-circuits 1
, A, 1B, ... Are connected in parallel, respectively, and are composed of a common circuit 2 for comparing the intensities of a plurality of interrupts.

The sub-circuits 1A, 1B, ... Are provided for each interrupt signal one by one, and the number of interrupt signals can be increased according to the number of interrupt signals. In the common circuit 2, regardless of the number of sub-circuits 1A, 1B, ... Connected, the interrupt strength determination circuit is a determination circuit that has the number of connected interrupt signals. As the common circuit 2 in this case, for example, an OR circuit having a large number of input terminals is used, and the terminals which are not connected to the sub-circuits 1A, 1B, ... Are always fixed at H level.

Each of the sub-circuits 1A, 1B, ... Has a common structure and operates by being divided into an interrupt strength calculation block and an interrupt acceptance calculation block.

In the interrupt strength calculation block, the subcircuit 1
When an interrupt corresponding to A, 1B, ... Is generated, the individual interrupt strength of the generated interrupt is compared with the total interrupt strength. By this comparison, when the generated interrupt has a higher interrupt strength, the interrupt strength of the generated interrupt is output with respect to the overall interrupt strength output. Also,
If the interrupt strength of the generated interrupt is less than or equal to the overall interrupt strength input, nothing is output.

The interrupt acceptance calculation block enables interrupt acceptance when the overall interrupt generation input is disabled and the interrupt strength calculation block outputs the interrupt strength. When the general interrupt generation input is disabled, the interrupt acceptance is enabled and the general interrupt generation output is enabled. In other cases, interrupt acceptance is disabled and the same signal as the overall interrupt generation input is sent to the overall interrupt generation output.

A specific configuration example of the sub-circuits 1A, 1B, ... Will be described with reference to FIG. In addition, each sub-circuit 1A,
1B, ... Have the same configuration.

The interrupt strength input 5 as an individual input strength signal is a plurality of strength signals (in this embodiment, three strengths 1, 2,
3). Input signal of each intensity 1, 2, 3 is 3
It is input to each of the AND circuits 6, 7 and 8. The total interrupt strength input 10 as a total input strength signal is composed of three strength 2, 3 and 4 signals corresponding to the interrupt strength input 5. The input signals of the intensities 2, 3 and 4 are passed through the inversion circuits 11, 12 and 13 to the AND circuits 6, 7, 8 respectively.
Are input respectively. Specifically, the first AND circuit 6
For interrupt strength input 5 strength 1 and overall interrupt strength input 1
The respective intensities 2, 3, and 4 of 0 are input. The strength 2 of the interrupt strength input 5 and the strengths 3 and 4 of the overall interrupt strength input 10 are input to the second AND circuit 7. Third AND circuit 8
For interrupt strength input 5 strength 3 and overall interrupt strength input 1
An intensity of 4 and 0 is entered.

In the overall interrupt strength input 10, for example, when the strength 1 or more of the interrupt strength input 5 is accepted, all the strengths 2, 3 and 4 of the overall interrupt strength input 10 are set to "L". As a result, "H" inverted by the inverting circuits 11, 12, 13 is input to the AND circuits 6, 7, 8 and any of the intensities 1, 2, 3 of the interrupt intensity input 5 is input. The input AND circuits 6, 7, and 8 output "H". For example, if the strength 2 of the interrupt strength input 5 or more is accepted, the strength 2 of the overall interrupt strength input 10 is set to “H”.
Then, the strengths 3 and 4 are set to "L". As a result, the first AN
"L" is input to the D circuit 6 by the strength 2 of the overall interrupt strength input 10, and "H" is input to the other AND circuits 7 and 8. The strength 1 of the interrupt strength input 5 is the first AN.
Even if input to the D circuit 6, since "L" is input to the AND circuit 6 due to the strength 2 of the overall interrupt strength input 10, "L" is output and cannot be accepted. When the strengths 2 and 3 of the interrupt strength input 5 are input to the AND circuits 7 and 8, "H" is input to both of the strengths 3 and 4 of the overall interrupt strength input 10, so that the strength 2 of the interrupt strength input 5 is 2. The AND circuits 7 and 8 output "H" regardless of which of the three is input. The above configuration constitutes the interrupt strength calculation block.

The outputs of the first to third AND circuits 6, 7 and 8 are input to the fourth to sixth AND circuits 15, 16 and 17, respectively. Further, an interrupt generation 18 as an individual input enable signal is input to each AND circuit 15, 16 and 17. As a result, when the interrupt generation 18 is "H", each A
When any of the ND circuits 6, 7, and 8 outputs "H",
The output is output to the common circuit 2 as the overall interrupt strength output 19 as the overall output strength signal. Furthermore, each AN
The outputs of the D circuits 15, 16 and 17 are input to the first OR circuit 20, and when any one of the AND circuits 15, 16 and 17 outputs "H", the first OR circuit 20 outputs "H". It has become. The output of the first OR circuit 20 is input to the seventh AND circuit 21. Furthermore, the common circuit 2
The entire interrupt generation input 22 as an acceptance enable input enable signal output from the
It is input to the ND circuit 21. The output of the seventh AND circuit 21 serves as an interrupt acceptance 25 as an individual acceptance signal and is input to the second OR circuit 26. Further, the overall interrupt generation input 22 is input to the second OR circuit 26. The output from the second OR circuit 26 becomes the overall interrupt generation output 27 as the reception enable output enable signal.

An interrupt acceptance calculation block is configured as described above.

When "H" indicating non-permission is input as the overall interrupt generation input 22, it is inverted by the inversion circuit 23 and becomes "L".
Is input to the seventh AND circuit 21 as
Even if "H" is output from any one of 5, 16, and 17, "L" is output as the interrupt acceptance 25. "L" as the interrupt acceptance 25 indicates that the entire interrupt generation input 22 is "H" and thus cannot be accepted or that there is no interrupt process currently accepted. At the same time, since "H" is input to one of the second OR circuits 26, the overall interrupt generation output 27 remains "H" indicating non-permission.

Here, the total interrupt generation input 22 is particularly input to the first sub-circuit 1A, and three sub-circuits 1 connected to each other are input.
A signal for controlling the enable state of the entire A, 1B, ... Is given the same name for convenience in each of the sub-circuits 1A, 1B ,. The overall interrupt generation output 27 output from the first sub circuit 1A becomes the overall interrupt generation input 22 of the next second sub circuit 1B. The same applies to the third sub circuit 1C. As described above, each of the sub-circuits 1A, 1B, ... Is connected in series to the overall interrupt generation input 22. The sub-circuits 1A, 1B, ... Are connected in parallel to the common circuit 2 while being connected in series. As a result, when the total interrupt generation input 22 input to the first sub-circuit 1A becomes "H", all the total interrupt generation inputs 22 of the other sub-circuits 1B and 1C become "H", and the entire interrupt strength judgment circuit becomes ineffective. It will be a permit. Similarly, when there is no interrupt accepted by the third sub-circuit 1A and an interrupt occurs in the second sub-circuit 1B, the overall interrupt generation input 22 of the third sub-circuit 1C becomes "H". That is, only one of the sub-circuits 1A, 1B, ... Is enabled.

On the other hand, when "L" indicating permission is input as the overall interrupt generation input 22, "H" is input to the seventh AND circuit 21, and "H" is output from any one of the AND circuits 15, 16 and 17. If so, "H" indicating that the interrupt is accepted is output as the interrupt acceptance 25, and "H" indicating non-permission is output as the overall interrupt generation output 27 so that the following sub-circuits 1B and 1C are not simultaneously operated. To do. Reference numeral 30 in FIG. 1 is an output for informing whether or not an interrupt has occurred in any of the sub-circuits 1A, 1B, ....

The common circuit 2 is composed of, for example, three OR circuits. The intensities 1, 2 and 3 from the AND circuits 15, 16 and 17 are input to the three OR circuits, respectively. That is, one OR circuit includes each sub circuit 1A, 1B,
The strength 1 of the total interrupt strength outputs 19 from ... is input respectively. All of the strengths 2 and 3 are input to the other OR circuits. And
When one of the intensities 1, 2 and 3 of the overall interrupt intensity output 19 of any one of the sub-circuits 1A, 1B, ... Becomes "H", the OR circuit in the common circuit 2 corresponding to that becomes "H". Then, the strength is input to each sub-circuit 1A, 1B, ...

For example, when the strength 2 is output as the overall interrupt strength output 19 in any of the sub-circuits 1A, 1B, ..., The corresponding OR circuit in the common circuit 2 outputs "H". This allows the overall interrupt strength input 1
For 0, the intensity 2 becomes “H”, and the intensity 2 or more of the interrupt intensity input 5 is accepted by the same operation as described above. Further, when interrupts having the same intensity are generated, the interrupt close to the first sub circuit 1A is prioritized.

The overall interrupt generation input 22 input to the first sub-circuit 1A is normally "L" (permitted). The overall interrupt generation input 22 becomes "H" when the interrupt processing device (not shown) is in a state in which it cannot accept the interrupt processing, for example, when interrupt processing is impossible or when the interrupt processing is performed by the device. It is when there is no ability. Furthermore, even if the interrupt processing function is not used, the entire interrupt generation input 2
Set 2 to "H". The interrupt intensity input 5 is always selected regardless of whether the overall interrupt generation input 22 is "H" or "L".

The operation of the whole interrupt strength judgment circuit is as follows.

Total interrupt strength input 10 strengths 2, 3,
When all 4 are "L", for example, the strength 1 of the interrupt strength input 5 of any one of the sub-circuits 1A, 1B, ... Becomes "H" and the strength 1 of the overall interrupt strength output 19
Outputs "H" and the input signal is accepted. At this time, for example, when the strength 3 of the interrupt strength input 5 becomes "H" in the other sub-circuits 1A, 1B, ..., The strength 3 is accepted and the sixth AND circuit 17 outputs "H". By the "H" of the strength 3, the strength 3 of the whole interrupt strength input 10 becomes "H" in the common circuit 2,
The first AND circuit 6 and the second AND circuit via the inverting circuit 12
“L” is input to the circuit 7. As a result, the strength 1 of the interrupt strength input 5 that has been accepted until then is not accepted, and instead, the interrupt request of the strength 3 is accepted. At the same time, "H" indicating that an interrupt is accepted from the sub-circuits 1A, 1B, ... Is output as the interrupt acceptance 25 and "H" is output as the overall interrupt generation output 27.
The other sub-circuits 1A, 1B, ... Are put in the disable state.

In this way, the interrupt request is always selected, and if there is an interrupt request having a stronger intensity than the interrupt process currently being processed, the interrupt process accepted each time is replaced. Then, when the processing is completed, the processing interrupted until then is restarted.

Here, the strength of the total interrupt strength input 10 is 4
Is an input for not accepting all the intensities 1, 2, and 3 of the interrupt intensity input 5. When the intensity 4 becomes "H", the inverting circuit 13 makes it "L" and each AND circuit 6 ,. Input to 7 and 8 and stop accepting all interrupt strength inputs 5.

In the interrupt strength judgment circuit of the present embodiment which operates as described above, when the interrupt strength input 5 is increased, the sub-circuits 1A, 1B, ... Are added according to the increasing number of interrupts.

This makes it possible to realize an interrupt strength judgment circuit having excellent expandability.

Further, the sub-circuits 1A, 1B, ... Must be prepared in the same number as the required number of interrupt signals, and are optimal for the DSP developed for ASIC.

In the above embodiment, the coded numerical value is not a problem for the interrupt strength, but the decoded signal is used in order to simplify the common circuit.
Therefore, for example, if the intensity is 2, the signal written as the intensity 2 becomes "1". At this time, the common circuit 2 is composed of three 3-input OR circuits.

The common circuit 2 is a wired OR.
Can also be used. By using this wired OR, the common circuit 2 only has wiring connections, and a theoretical element is not required.

Although the number of the interrupt strength inputs 5 is three, it may be four or more, and in this case, the number of OR circuits built in the common circuit 2 is increased according to the number. .. The strength of the interrupt strength input 5 is not limited to the strengths 1, 2 and 3 as in the above embodiment, but can be set to another strength.

[0038]

As described in detail above, according to the interrupt strength judgment circuit of the present invention, the sub strength judgment circuit is added and expanded in accordance with the number of input signals, so that it has excellent expandability. The interrupt strength judgment circuit can be realized.

Since it is necessary to prepare the same number of sub-strength determination circuits as the number of required interrupt signals, it is most suitable for the DSP developed for ASIC.

[Brief description of drawings]

FIG. 1 is a block diagram showing an interrupt strength determination circuit according to the present invention.

FIG. 2 is a logic circuit diagram showing an example of a configuration of a sub-interruption strength determination circuit.

[Explanation of symbols]

 1A, 1B, 1C Sub-circuit 2 Common circuit 5 Interrupt strength input 10 Overall interrupt strength input 19 Overall interrupt strength output 22 Overall interrupt generation input 25 Interrupt acceptance 27 Overall interrupt generation output

Claims (1)

[Claims] 1. An intensity determination circuit for determining the intensities of a plurality of input signals and selecting which is to be accepted, which is provided for each input signal, and has an acceptance enable input enable signal, an overall input intensity signal, Receives the individual input enable signal and the individual input strength signal and outputs the acceptance enable output enable signal, the overall output strength signal and the individual acceptance signal, and the sub strength judgment circuits and the total output strength signal from each sub strength judgment circuit. And a common circuit that receives the largest value and returns as a whole input strength signal of each sub-strength judgment circuit, each sub-strength judgment circuit outputs an acceptance enable output enable signal from one of the circuits. Connect in series so as to be the input enable signal for acceptance permission of other circuits,
A strength judgment circuit characterized in that only one of the sub strength judgment circuits is enabled.