JPH01304564A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To effectively use terminals and interruption request flags by using function terminals of a serial interface as external interruption input terminals. CONSTITUTION:A single chip microcomputer 1 incorporates an edge detecting circuit 2, an UART 3, an interruption signal selector 10, and request flags 20 and 21. The UART 3 is a block having the asynchronous serial interface function and is provided with a transmission part 4, a reception part 5, and a mode register 6 which controls the whole of the UART 3. Since the interruption signal selector 10 is provided, a transmission terminal 7 and a reception terminal 8 are used as function terminals of the UART 3 when the UART 3 is operated, and the transmission terminal 7 and the reception terminal 8 are used as external interruption input terminals when the UART 3 is stopped.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a single-chip microcomputer,
In particular, the present invention relates to a single-chip microcomputer with a built-in serial interface having external function terminals.

[Conventional technology]

In recent years, single-chip microcomputers have come to incorporate a wide variety of peripheral hardware, the number of external pins has increased, and the number of interrupt signals processed internally by each peripheral hardware has also increased significantly. .

Conventionally, in a single-chip microcomputer that has a built-in serial interface with an external function terminal and an interrupt request flag, when the serial interface is stopped, the function terminal and the interrupt request flag of the serial interface do not function at all. It has become useless.

For example, as shown in Figure 3, UART (Universal
Asynchronous receiver Tran
smitter: asynchronous serial interface)
In the single-chip microcomputer 1 that incorporates the transmitting terminal 7, the receiving terminal 8, the interrupt request flag 20 that is set when the transmission of the transmitting section 4 is completed, and the receiving section 5.
It has an interrupt request flag 21 that is set upon completion of reception.

However, in the past, when the UART function was stopped, the transmitting terminal 7 and the receiving terminal 8 had no more than a port function.

Furthermore, the interrupt request flags 20 and 21 are not used at all when the UART function is stopped, making them useless.

[Problem to be solved by the invention]

In the conventional single-chip microcomputer described above, when the serial interface is stopped, the functional terminals such as the transmitting terminal and the receiving terminal and the interrupt request flag of the serial interface are never used and are useless. Ta.

In this way, the presence of unused pins and unused interrupt request flags in a single-chip microcomputer that incorporates a wide variety of peripheral functions means that it has unnecessary circuit parts, making it very economical. It has the disadvantage of being bad. For example, if the interrupt request flag corresponding to each peripheral hardware is a register with a predetermined bit length, the number of registers will increase.

[Means to solve the problem]

In the case where the single-chip microcomputer of the present invention has a built-in serial interface having a functional terminal and an interrupt request flag for the serial interface, the single-chip microcomputer has a control register for controlling operation and stop of the serial interface, and a control register for controlling operation and stop of the serial interface. switching means for setting the interrupt request flag by an interrupt signal of the serial interface when the serial interface is being used; and for setting the interrupt request flag by a change in the input level to the function terminal when the serial interface is not being used; It is characterized by having a built-in

〔Example〕

Next, an embodiment of the present invention will be described using FIG. In the embodiment of the present invention, an example will be described in which a single terminal is used in common as a UART transmitting/receiving terminal and an external interrupt input terminal.

FIG. 1 is a block diagram of a single-chip microcomputer in an embodiment of the present invention.

The single-chip microcomputer 1 includes an edge detection circuit 2, a UART 3, an interrupt signal selector 10, and interrupt request flags 20 and 21.

UART3 is a block having an asynchronous serial interface function, and includes a transmitter 4, a receiver 5, and a UART
It has a mode register 6 that controls the entire 3.

When the transmitter 4 finishes transmitting data from the transmitter terminal 7,
A transmission completion interrupt signal 13 is output.

When the receiving unit 5 finishes receiving predetermined data from the receiving terminal 8, it outputs a reception completion interrupt signal 14.

The transmitting terminal 7 and the receiving terminal 8 also have the function of external interrupt signal input terminals, and the signals inputted to the two terminals are outputted as they are to the interrupt signal selector 10 as external interrupt input signals 11 and 12.

The interrupt signal selector 10 switches and selects an external interrupt input signal 11 . 2
This is a circuit that sets and turns 1.

When the mode register 6 specifies transmission permission, the interrupt signal selector 10 sets the interrupt request flag 20 in response to the transmission completion interrupt signal 13. Further, when the mode register 6 specifies that transmission is prohibited, the interrupt signal selector 10 sets the interrupt request flag 20 in response to the external interrupt input signal 12.

The above operation is the same for the interrupt request flag 21.
When the mode register 6 specifies reception permission, the reception completion interrupt signal 14 sets the interrupt request flag 21, and when reception prohibition is specified, the external interrupt input signal 12 sets the interrupt request flag 21.

The edge detection circuit 2 is a circuit that detects predetermined edges of the transmission completion interrupt signal 13, the reception completion interrupt signal 14, and the external interrupt input signal 11.12, and sets an interrupt request flag 20.21.

As described above, in the single-chip microcomputer of the present invention, by providing the interrupt signal selector 10,
When the UART 3 is operating, the transmitting terminal 7 and the receiving terminal 8 can be used as functional terminals of the UART, and when the UART 3 is stopped, the two terminals can be used as external interrupt input terminals.

Furthermore, the interrupt request flags 20 and 21 can be switched to be used exclusively for the UART when the UART3 is operating, and used for external interrupt input signals when the UART3 is stopped. External interrupts and serial interface interrupt request flags can be shared.

Next, an example will be described using FIGS. 1 and 2 in which, in a single-chip microcomputer incorporating the means of the present invention, standby release and reception operations are performed through one external terminal.

FIG. 2 is a sequence diagram when the single-chip microcomputer shown in FIG. 1 of the present invention successively performs standby release and reception operations.

First, assume that the single-chip microcomputer 1 is in a standby state with the UART 3 stopped and the reception terminal 8 operated as an external interrupt function terminal. A high level signal is input to the receiving terminal 8 from the outside. In the single-chip microcomputer 1, the standby mode can be canceled by inputting a valid edge to an external interrupt terminal.

When the single-chip microcomputer 1 is in the standby state as described above, first, a negative polarity pulse (see (2) in FIG. 2) is inputted from the receiving terminal 8. Then, the single-chip microcomputer 1 detects a valid edge input to the external interrupt input terminal, cancels the standby state, and executes an interrupt processing routine for canceling standby (external interrupt input). Therefore, if the UART3 is enabled to receive data in the interrupt processing routine, the receiving terminal 8 will function as the receiving terminal of the UART3, and from then on the UART
3 can receive the reception take input to the reception terminal 8.

As described above, when the means of the present invention is used, standby release and reception operations were performed using separate terminals, whereas in the past, standby release and reception operations were performed using separate terminals.
You will be able to do it using the terminal of the book.

In the single-chip microcomputer of the present invention, an example has been described in which standby release and reception operations are performed continuously using one external terminal, but the transmission terminal can also be set to a high impedance state (input state) similar to the transmission terminal. It goes without saying that the same operation is possible if you do the same.

〔Effect of the invention〕

As described above, the single-chip microcomputer of the present invention uses the functional terminal of the serial interface as an external interrupt input terminal even when the serial interface is not used. By providing an interrupt signal selector, even when the function of the serial interface is stopped, the interrupt request flag corresponding to the serial interface is used as the interrupt request flag for external interrupts.

Therefore, even when the serial interface is stopped, the functional terminals and interrupt request flags are used for other functions, so that the terminals and interrupt request flags of the single-chip microcomputer can be effectively utilized.

Furthermore, in general, in an interrupt processing circuit, the area occupied by the control register/control circuit associated with one interrupt request flag on the chip is relatively large. However, according to the present invention, since two types of interrupt request signals that are not used simultaneously are processed as one interrupt request signal, there is also the effect that the size of the control register/control circuit portion can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the single-chip microcomputer of the present invention, Fig. 2 is a sequence diagram when standby release and reception operations are performed continuously in the single-chip microcomputer of the present invention, and Fig. 3 is a block diagram of the single-chip microcomputer of the present invention. FIG. 2 is a block diagram of a computer. 1...Single-chip microcomputer,
2...Edge detection circuit, 3...UAR
T, 4...Transmitter section, 5...Receiver section, 6
...Mode register, 7...Transmission terminal, 8...Reception terminal, 10...Interrupt signal selector, 11.12...External Interrupt input signal, 13... Transmission completion interrupt signal, 14...
...Reception completion interrupt signal, 20.21...Interrupt request flag. Agent Patent Attorney Uchihara Oto 3rd

Claims (1)

[Scope of Claims] A single-chip microcomputer that includes a serial interface having a functional terminal and an interrupt request flag for the serial interface, further comprising a control register that controls operation and stop of the serial interface, and a control register that controls operation and stop of the serial interface. When the serial interface is stopped, the interrupt request flag is set by the interrupt signal of the serial interface, and when the serial interface is stopped, the interrupt request flag is set by a change in the input level to the function terminal. A single-chip microcomputer characterized by having built-in means.