JPH0535593A - Cache memory control system - Google Patents

Abstract

PURPOSE:To shorten the write cycle of a central processor as to an information processor equipped with a central processing unit and a cache memory. CONSTITUTION:When the central processing unit 101 is in a write cycle, a cache control part 107 updates the contents of a tag memory 104 according to an address on an address control bus 108 while indicating the writing of data on a data bus 109 to a write buffer 102 without waiting for the cache hit/mishit decision result of a comparator 106, thereby updating the contents of a data memory 105 according to the data on the data bus 109. Therefore, the cache hit/mishit decision result of the comparator 10 need not be waited for, so the write cycle can be made short.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system, and more particularly to a cache memory control system capable of performing a write cycle of a central processing unit at high speed.

[0002]

2. Description of the Related Art Conventionally, this type of cache memory control system determines a cache hit / miss hit during a write cycle of a central processing unit, and if a cache hit occurs, updates the data in the corresponding cache memory and writes it to the write buffer. Data is written, and in the case of a cache miss hit, the data is written to the write buffer or main memory without updating the cache memory.

[0003]

In the above-mentioned conventional cache memory control method, it is not decided whether or not to write data into the cache memory until a cache hit / miss hit is determined, so that the data memory in the cache memory is not determined. Generation of the write signal for
There is a problem that the write cycle of the central processing unit becomes long.

An object of the present invention is to provide a cache memory control system capable of accelerating the write cycle of the central processing unit.

[0005]

In order to achieve the above object, the present invention provides an information processing apparatus including a central processing unit and a cache memory, wherein a cache hit, a cache, or a cache hit occurs during a write cycle of the central processing unit. The cache memory is updated at the same time when the write data is written in the write buffer regardless of the mishit.

[0006]

In the write cycle of the central processing unit, the write data is written in the write buffer and the cache memory is updated at the same time according to the write data and the write address regardless of the cache hit or cache miss hit. That is, it is not necessary to wait for the judgment of cache hit or cache miss hit, so the write cycle can be speeded up.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The information processing apparatus shown in the figure includes a central processing unit 101,
It includes a write buffer 102 and a cache memory 103, which are connected by an address control bus 108 including an address bus and a control bus and a data bus 109.

The cache memory 103 is the tag memory 1
04, the data memory 105, and the comparator 106
And a cache control unit 107.

The data memory 105 stores a copy of a part of the main memory.

The tag memory 104 includes a data memory 105.
The address of the data stored in and the flag indicating valid / invalid are stored.

The comparator 106 operates according to the address output by the central processing unit 101 to the address control bus 108 during the cache access and the address output by the central processing unit 101 to the address control bus 108.
The address read from 4 is compared, and if there is a comparison match, the cache hit signal HIT is output.

The cache control unit 107 controls each unit of the cache memory 103 and also controls the write buffer 10.
Control 2 is also performed. Further, the cache control unit 107 also responds to the central processing unit 101.

Next, the operation of this embodiment will be described in detail in comparison with the conventional system.

FIG. 2 is a time chart showing the operation of this embodiment, and FIG. 3 is a time chart showing the operation of the conventional system. 2 and 3, CLOCK is the basic clock of the central processing unit 101, and Axx is the central processing unit 101.
From the address output to the address control bus 108, W
R is a read / write identification signal output from the central processing unit 101 to the address control bus 108, TS is a data transfer start signal output from the central processing unit 101 to the address control bus 108, and TA is address control from the cache control unit 107. The data transfer end signal output to the bus 108 is shown.

Dxx represents data, which is output from the central processing unit 101 during the write cycle of the central processing unit 101. Furthermore, HIT is a cache hit signal,
RAM / CS is a tag memory 104 and a data memory 105.
RAM · WE indicates a write signal for the tag memory 104 and the data memory 105. Further, T1 to T4 represent phases in the data transfer cycle of the central processing unit 101.

First, the operation of this embodiment will be described with reference to FIG.

When the central processing unit 101 performs write access, the address Ax is sent to the address control bus 108 at the falling edge of the clock signal CLOCK in cycle T1.
x, a read / write identification signal WR, a data transfer start signal TS, and data Dxx on the data bus 109.

When the address Axx is output from the central processing unit 101, the address is read from the tag memory 104 and compared with the address Axx in the comparator 106. In the case of comparison match, that is, in the case of cache hit, the comparator 106 activates the cache hit signal HIT at the rising edge of the clock signal CLOCK in the cycle T2.

The cache control unit 107 is the central processing unit 1.
When 01 is a write cycle (when the read / write identification signal WR indicates write), the comparator 10
Instead of waiting for the cache hit signal HIT from 6, the write buffer 102 is instructed to write the data on the data bus 109 at the rising edge of the clock signal CLOCK in the cycle T2. As a result, the data Dxx on the data bus 109 is written in the write buffer 102. This data Dxx is reflected on the main memory.

At the same time as the cache control unit 107 issues a write instruction to the write buffer 102, that is,
At the rising edge of the clock signal CLOCK in the cycle T2, the write signals RAM · WE for the tag memory 104 and the data memory 105 are activated. As a result, the data memory 105 replaces one piece of data stored in the same tag as the data Dxx on the data bus 109 with the data Dxx, and the tag memory 104 stores the above-mentioned data among the held addresses. The address corresponding to is replaced with the address Axx on the address control bus 108.

After that, the cache controller 107 activates the data transfer end signal TA at the falling edge of the clock signal CLOCK in the cycle T2. As a result, the central processing unit 101 ends the data transfer cycle at cycle T3. Thus, according to this embodiment, T
The write cycle can be completed in three cycles of 1 to T3. Regarding the read cycle, the same operation as the conventional one is performed.

Next, the operation of the conventional system will be described with reference to FIG.

When the central processing unit 101 makes a write access, the operation similar to that of the present embodiment is performed in cycle T1 even in the conventional system.

In the case of a cache hit, the clock signal CLOC of the cycle T2 is output from the comparator 106.
At the falling edge of K, the cache hit signal HIT is output.

The cache controller 107 determines whether or not the cache hit signal HIT is active at the rising edge of the clock signal CLOCK in cycle T3. If it is determined that the write signal RAM.WE is activated in cycle T3, the data Dxx to the data memory 105 is activated.
The write buffer 102 is instructed to write the data Dxx. When it is determined that the cache hit signal HIT is not active, the write buffer 102 is instructed to write the data on the data bus 109.

After that, the cache control unit 107 activates the data transfer end signal TA at the falling edge of the clock signal CLOCK in the cycle T3, whereby the data transfer end signal TA is activated.
The central processing unit 101 ends the data transfer cycle at cycle T4. As described above, the conventional method requires four write cycles, T1 to T4.

[0028]

As described above, according to the present invention, during the write cycle of the central processing unit, the write data is written into the write buffer and the cache memory is updated at the same time regardless of the cache hit or the cache miss hit. Since there is no need to wait for the cache hit / cache miss hit determination result, there is an effect that the write cycle of the central processing unit can be accelerated as compared with the conventional example.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart of an example.

FIG. 3 is a time chart of a conventional method.

[Explanation of symbols]

101 ... Central processing unit 102 ... write buffer 103 ... Cache memory 104 ... Tag memory 105 ... Data memory 106 ... Comparator 107 ... Cache control unit 108 ... Address control bus 109 ... data bus

Claims (3)

[Claims] 1. An information processing device comprising a central processing unit and a cache memory, wherein write data is written to a write buffer regardless of cache hit or cache miss hit during a write cycle of the central processing unit. A cache memory control method characterized in that the cache memory is updated at the same time. 2. The cache memory includes a data memory and a tag memory, and the write data is written into the write buffer at the same time as the write data is written in the write buffer regardless of cache hit or cache miss hit during a write cycle of the central processing unit. Update according to the write data,
2. The cache memory control method according to claim 1, wherein the tag memory is updated according to a write address. 3. A write cycle of the central processing unit,
3. The cache memory control method according to claim 2, wherein the data in the same tag as the write data in the data in the data memory is updated.