JPH0535664A - Multi-processor system - Google Patents

Abstract

PURPOSE:To sufficiently exhibit the performance of a system by making the acquisition ratio of a common bus constant for each processor in a multi- processor system. CONSTITUTION:A data input bus 1 is assigned by time division by data input bus use permitting signals 41-4n outputted from a time division bus assigning circuit 4 for a data input bus for respective micro-processors 31-3n. A data output bus 2 is assigned by time division by data output bus use permitting signals 51-5n outputted from a time division bus assigning circuit 5 for a data input bus for respective micro-processors 31-3n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to controlling the data input bus and data output bus of a multiprocessor.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional multiprocessor system, in which 1 is a common data input bus, 2 is a common data output bus, and 31-3n are data input buses 1.
And a microprocessor connected to the data output bus 2, 6 is a data input bus contention arbitration circuit that arbitrates access to the data input bus 1 of the microprocessors 31 to 3n, and 7 is a data output bus 2 of the microprocessors 31 to 3n. Is a data output bus contention arbitration circuit that arbitrates the access of.

Next, the operation will be described with reference to FIG. When accessing the data input bus 1, the microprocessors 31 and 3n send data input bus use request signals 611 and 6n1 to the data input bus contention arbitration circuit 6. When the use requests compete, the data input bus contention arbitration circuit 6 sends the data input bus use permission signal 612 to the microprocessor 31 with a predetermined priority, and the microprocessor 31 which has acquired the bus use right first receives the data input bus. Access 1. When this access is completed, the data input bus contention arbitration circuit 6 sends the data input bus use permission signal 6n2 to the microprocessor 3n, which causes the microprocessor 3n to access the data input bus 1. On the other hand, also for the data output bus 2, the data output bus contention arbitration circuit 7 performs the same arbitration operation by the signal in the parentheses shown in FIG.

[0004]

Since the conventional multiprocessor system is configured as described above, it is determined by a predetermined algorithm for a bus use request asynchronously generated from each of the microprocessors 31 to 3n. The bus right is given to the processor specified according to the priority order. Therefore, if the arbitration methods are not harmonized to suit the system, there is a problem that the bus acquisition rate for each processor significantly varies and the system cannot exhibit sufficient performance.

[0005]

The present invention provides a multiprocessor system in which a plurality of processors each having a data input bus and a data output bus are connected to a common data input bus and a common data output bus. A time-division bus allocation circuit that distributes the right to use the data input bus and the data output bus to each processor in a time-division manner is provided.

[0006]

According to the present invention, the bus is time-divided and the bus is periodically assigned to each processor from the time-division bus allocation circuit, so that the bus acquisition rate is constant in each processor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a multiprocessor system according to the present invention, in which 1 is a common data input bus, 2 is a common data output bus, and 31 to 3n are a data input bus 1 and a data output bus 2. A time-division bus allocation circuit for a data input bus 4 which gives time-divisional use permission signals 41-4n of the data input bus 1 to the microprocessors 31-3n. It is a time division bus allocation circuit for the data output bus which gives use permission signals 41 to 4n of the data output bus 2 by division.

Next, the operation will be described with reference to FIG. The time-division bus allocation circuit 4 for the data input bus is provided to each of the microprocessors 31 to 3n with respect to each of the microprocessors 31 to 3n.
Data input bus use permission signal 4 in which n has a sufficient width for data input and does not overlap in time
Outputs 1 to 4n. Each microprocessor 31 to 3n
Takes in data from the data input bus 1 as necessary while receiving this signal. That is, the data input bus 1 is time-divisionally assigned to each of the microprocessors 31 to 3n by the data input bus time division bus assignment circuit 4. Therefore, competition does not occur, and the microprocessors 31 to 3n are always given an opportunity to acquire the data input bus 1 in a constant cycle.
The acquisition rate of the data input bus 1 is constant.

On the other hand, the time division bus allocation circuit 5 for the data output bus also sends the data output bus permission signals 51 to 5n to the respective microprocessors 31 to 3n in a time division manner and performs the same operation.

[0010]

As described above, according to the present invention, each processor gives a bus use right for a sufficient time for data input / output to each processor in a time-sharing manner. There is an effect that it can be kept constant and the system performance can be sufficiently brought out.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system according to the present invention.

FIG. 2 is a diagram showing the timing of FIG.

FIG. 3 is a block diagram of a conventional multiprocessor system.

FIG. 4 is a diagram showing timing in FIG.

[Explanation of symbols]

 1 data input bus 2 data output bus 31 to 3n microprocessor 4 data input bus time division bus allocation circuit 41 to 4n data input bus use permission signal 5 data output bus time division bus allocation circuit 51 to 5n data output bus use permission signal

Claims (1)

[Claims] 1. In a multiprocessor system in which a plurality of processors each having a data input bus and a data output bus are connected to a common data input bus and a data output bus, the common data input bus and the data output bus A multiprocessor system comprising a time-division bus allocation circuit for time-divisionally distributing the usage right to each processor.