JPH0537005A - Light receiving element and manufacturing method thereof - Google Patents
Light receiving element and manufacturing method thereofInfo
- Publication number
- JPH0537005A JPH0537005A JP3187884A JP18788491A JPH0537005A JP H0537005 A JPH0537005 A JP H0537005A JP 3187884 A JP3187884 A JP 3187884A JP 18788491 A JP18788491 A JP 18788491A JP H0537005 A JPH0537005 A JP H0537005A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- layer
- light receiving
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000000605 extraction Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は受光素子及びその製造方
法に関し、特に詳細には、フリップチップボンディング
可能なＰＩＮ型受光素子及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving element and a manufacturing method thereof, and more particularly to a PIN type light receiving element capable of flip chip bonding and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】近年、ギガビットレベルでの光通信を行
うため、高速応答性及び高い光感度を有する受光素子が
求められてきている。そして、高速な応答性を実現する
ためには、入力容量を低減することが求められ、これを
達成するためにプリアンプを形成した基板上に直接ダイ
ボンディングするフリップチップボンディング技術が開
発されてきた。このようなフリップチップボンディング
を可能にした受光素子としてエレクトロニクスレターの
第２４巻、第１６号の１９８８年８月４日号の第９９５
頁に示されるものがある。この文献に開示される受光素
子の構造を図４に示す。そして、この受光素子のＰＩＮ
構造は、ｎ+ −ＩｎＰ基板１上に、ｎ−ＩｎＰのバッフ
ァ層２、ｎ−ＧａＩｎＡｓの光吸収層３、ｎ−ＩｎＰの
キャップ層４より構成され、ｐｎ接合は、キャップ層４
内にＺｎ拡散（図３において点線で囲まれた領域）を行
うことにより形成し、図３に示すように、化学的エッチ
ングによりメサ構造５を作成し、そのメサ構造５のキャ
ップ層４の上部にはＰ型電極６が、また、その周辺の領
域にはＮ型電極７が形成されている。そして、このＰ型
電極とＮ型電極は、図３に点線で示す基板８にフリップ
チップボンディングできるようにように実質的に同一平
面上に位置するように形成されている。2. Description of the Related Art In recent years, in order to perform optical communication at a gigabit level, a light receiving element having a high speed response and a high optical sensitivity has been demanded. Then, in order to realize high-speed response, it is required to reduce the input capacitance, and in order to achieve this, a flip chip bonding technique has been developed in which die bonding is directly performed on a substrate on which a preamplifier is formed. As a light receiving element capable of such flip chip bonding, Electronics Letter, Volume 24, No. 16, August 4, 1988, No. 995.
Some are shown on the page. The structure of the light receiving element disclosed in this document is shown in FIG. Then, the PIN of this light receiving element
The structure is composed of a buffer layer 2 of n-InP, a light absorption layer 3 of n-GaInAs, and a cap layer 4 of n-InP on an n + -InP substrate 1, and a pn junction is a cap layer 4.
It is formed by performing Zn diffusion (region surrounded by a dotted line in FIG. 3) inside, and as shown in FIG. 3, a mesa structure 5 is formed by chemical etching, and an upper portion of the cap layer 4 of the mesa structure 5 is formed. Is formed with a P-type electrode 6, and an N-type electrode 7 is formed in the peripheral region. The P-type electrode and the N-type electrode are formed so as to be located substantially on the same plane so that flip-chip bonding can be performed on the substrate 8 shown by a dotted line in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記文献に開
示される受光素子は、図３に示すように、Ｎ型電極７を
取り出すためにｎ+ 基板を用いている。その為、ｎ+ 基
板による寄生容量が大きく、高速応答性を得ることが難
しかった。However, the light receiving element disclosed in the above-mentioned document uses an n + substrate for taking out the N-type electrode 7 as shown in FIG. Therefore, the parasitic capacitance of the n + substrate is large and it is difficult to obtain high-speed response.
【０００４】本願発明は上記課題を解決し、寄生容量が
小さく非常に高速な応答性を有するフリップチップダイ
ボンデイング用の受光素子及びそれの製造方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a light receiving element for flip-chip die bonding having a small parasitic capacitance and a very fast response, and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明の受光素子は、一
対の基板側電極を設けた支持基板上に、素子搭載面が対
向するよう搭載されることにより一対の引出し電極が前
記基板側電極に接続される裏面入射型受光素子であっ
て、半絶縁性半導体基板上に形成した凹部内に、一方の
素子電極が凹部底面側に位置し、他方の素子電極が頂部
に位置するようＰＩＮ型受光部が配設され、一対の引出
し電極の一方は凹部側面に沿って設けられた引出しリー
ドを介して一方の素子電極に接続されて、他方の引出し
電極が他方の素子電極に接続されているを特徴とする。In the light receiving element of the present invention, a pair of extraction electrodes are mounted on a supporting substrate provided with a pair of substrate side electrodes so that element mounting surfaces face each other. Is a back-illuminated type light receiving element connected to a PIN type so that one element electrode is located on the bottom surface side of the recess and the other element electrode is located on the top portion in the recess formed on the semi-insulating semiconductor substrate. A light receiving portion is provided, one of the pair of extraction electrodes is connected to one of the element electrodes through an extraction lead provided along the side surface of the recess, and the other of the extraction electrodes is connected to the other element electrode. Is characterized by.
【０００６】また、本発明の受光素子の製造方法は、電
極を設けた基板上に素子搭載面を対向させて搭載される
受光素子の製造方法であって、半絶縁性半導体基板に凹
部を形成する第１の工程と、第１工程で形成した半絶縁
性半導体基板の凹部が形成されている面上に下側が一方
の電極となり、上側が他方の電極となるようなｐｉｎ型
受光素子を構成する半導体結晶層を順次形成する第２工
程と、前記第２工程で形成した半導体結晶層の凹部内の
不要部分を除去しＰＩＮ型受光部の一方の電極となる層
を露出させる第３工程と、第３工程で露出させた層から
一方の電極を凹部の外部の前記半絶縁性半導体基板上面
に前記凹部側面に沿って引出す引出しリードを形成する
第４工程とを含むことを特徴とする。A method of manufacturing a light receiving element of the present invention is a method of manufacturing a light receiving element mounted on a substrate provided with electrodes with element mounting surfaces facing each other, in which a recess is formed in a semi-insulating semiconductor substrate. And a pin type light receiving element in which the lower side is one electrode and the upper side is the other electrode on the surface of the semi-insulating semiconductor substrate formed in the first step in which the concave portion is formed. A second step of sequentially forming a semiconductor crystal layer to be formed, and a third step of removing an unnecessary portion in the concave portion of the semiconductor crystal layer formed in the second step to expose a layer to be one electrode of the PIN type light receiving portion. And a fourth step of forming an extraction lead for extracting one electrode from the layer exposed in the third step on the upper surface of the semi-insulating semiconductor substrate outside the recess along the side surface of the recess.
【０００７】[0007]
【作用】本発明は、上記のように、半絶縁性基板に設け
た凹部内に設けたＰＩＮ型の受光素子の一方の電極とな
る層から直接、半絶縁性基板に設けた凹部側面に沿って
設けた引出し電極を介してｎ型電極を基板上面に引出し
ている。そのため、基板が電気的に関与せずＮ型電極で
の寄生容量が小さい。According to the present invention, as described above, the side surface of the recess provided on the semi-insulating substrate is directly extended from the layer serving as one electrode of the PIN type light receiving element provided in the recess provided on the semi-insulating substrate. The n-type electrode is led out to the upper surface of the substrate through the lead electrode provided as above. Therefore, the substrate is not electrically involved and the parasitic capacitance at the N-type electrode is small.
【０００８】また、半導体基板に設けた凹部内に受光素
子を形成することにより、受光素子の高さを調節でき、
その結果、受光素子の基板側の電極を基板表面に引出
し、受光素子の２つの電極を実質的に同一平面内に形成
することにより、フリップチップボンディング可能な受
光素子の製造が可能になる。Further, the height of the light receiving element can be adjusted by forming the light receiving element in the recess provided in the semiconductor substrate,
As a result, the electrode on the substrate side of the light receiving element is drawn out to the surface of the substrate, and the two electrodes of the light receiving element are formed substantially in the same plane, whereby a light receiving element capable of flip chip bonding can be manufactured.
【０００９】[0009]
【実施例】以下、図面を参照しつつ本発明に従う一実施
例である受光素子及びその製造方法について説明してい
く。尚、図面中の寸法比率は必ずしも実際の寸法比率と
は一致していない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A light receiving element and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. The dimensional ratios in the drawings do not always match the actual dimensional ratios.
【００１０】図１に本発明の受光素子の一実施例の断面
構造を示す。FIG. 1 shows a sectional structure of an embodiment of the light receiving element of the present invention.
【００１１】図１に示すように、半絶縁性ＩｎＰ基板１
０に形成された凹部１０ａ内にＰＩＮ型ホトダイオード
を構成する半導体層が形成されている。そして、このＰ
ＩＮ型ホトダイオードは基板１０側から、Ｎ層となるｎ
ーＩｎＰ層１１と、Ｉ層であって光吸収層となるｉ−Ｇ
ａＩｎＡｓ層１２の半導体多層構造を有しており、その
ｉ−ＧａＩｎＡｓ層１２の上部にはＺｎが拡散された領
域１３が設けられており、ｐｎ接合が形成され、領域１
３がＰ層として機能する。その上に基板１０全体には、
ＳｉＮの絶縁膜１４が形成されており、ｎ−ＩｎＰ層１
１の端部にはＮ型電極を引き出すための電極１５が、ま
たｉ−ＧａＩｎＡｓ層の１２の頂部にはＰ型電極１６が
設けられており、このＰ型電極１６上には、引出し電極
１８が設けられている。更に、電極１５上には、Ｎ型電
極を基板１０上面に引き出すための引出しリード１７が
設けられている。このリード７は、凹部の側面に沿って
伸び基板１０の上面に設けた引出し電極１８に接続され
ている。そして、この引出し電極１８と引出し電極１９
の上面は、フリップチップボンディング可能とするた
め、実質的に同一平面上に位置している。そして半導体
層、電極等の厚さ及び凹部の深さは、引出し電極１８と
引出し電極１９との上面が実質的に同一平面となるよう
選択されている。一方、基板１０の裏面側には反射防止
膜２０が設けられている。As shown in FIG. 1, a semi-insulating InP substrate 1
A semiconductor layer forming a PIN photodiode is formed in the recess 10a formed in 0. And this P
The IN-type photodiode is an N layer from the substrate 10 side.
-InP layer 11 and i-G which is an I layer and serves as a light absorption layer
The semiconductor multilayer structure of the aInAs layer 12 is provided, and the Zn-diffused region 13 is provided on the i-GaInAs layer 12 to form a pn junction, and the region 1 is formed.
3 functions as a P layer. On top of that, the entire substrate 10
The insulating film 14 of SiN is formed, and the n-InP layer 1 is formed.
An electrode 15 for drawing out an N-type electrode is provided at one end of the electrode 1, and a P-type electrode 16 is provided on the top of the i-GaInAs layer 12, and a lead-out electrode 18 is provided on the P-type electrode 16. Is provided. Further, on the electrode 15, a lead lead 17 for leading the N-type electrode to the upper surface of the substrate 10 is provided. The lead 7 extends along the side surface of the recess and is connected to the extraction electrode 18 provided on the upper surface of the substrate 10. Then, the extraction electrode 18 and the extraction electrode 19
The upper surface of the is substantially coplanar so that flip chip bonding is possible. The thickness of the semiconductor layers, electrodes, etc. and the depth of the recesses are selected so that the upper surfaces of the extraction electrode 18 and the extraction electrode 19 are substantially coplanar. On the other hand, an antireflection film 20 is provided on the back surface side of the substrate 10.
【００１２】このように構成したことによりＰＩＮ型ホ
トダイオードのＮ型電極での寄生容量を従来のｎ+ Ｉｎ
Ｐ基板を用いたものに比較して小さくすることができ
る。また、基板内に設けた凹部内にＰＩＮ型の受光素子
を設けているため、その受光素子の光吸収層の厚くする
ことができる。これにより、光感度の高い受光素子が実
現できる。With this structure, the parasitic capacitance at the N-type electrode of the PIN photodiode is reduced to that of the conventional n + In
It can be made smaller than that using a P substrate. Further, since the PIN type light receiving element is provided in the recess provided in the substrate, the light absorption layer of the light receiving element can be made thick. As a result, a light receiving element having high photosensitivity can be realized.
【００１３】また、この受光素子を使用する場合には、
支持基板にフリップチップボンディングして使用する
が、この支持基板８側には、この引出し電極１８と引出
し電極１９が接続される一対の電極１８ａ、１９ａが設
けられ、これらとフリップチップボンディングにより互
いに接続できるようになっている。そして、上記実施例
の受光素子は、矢印で示す方向からの光を受光するよう
に用いられる。When using this light receiving element,
The support substrate 8 is used by flip-chip bonding. A pair of electrodes 18a, 19a to which the extraction electrode 18 and the extraction electrode 19 are connected are provided on the support substrate 8 side and are connected to each other by flip-chip bonding. You can do it. Then, the light receiving element of the above embodiment is used to receive light from the direction indicated by the arrow.
【００１４】以下、上記実施例の受光素子の製造方法に
ついて、図２及び図３を用いて説明する。A method of manufacturing the light receiving element of the above embodiment will be described below with reference to FIGS.
【００１５】まず、半絶縁性ＩｎＰ基板１０を準備し
（図２（ａ）参照）、この基板１０に所定の深さ、例え
ば２〜３μｍの深さの凹部１０ａを形成する。この凹部
の深さは、その凹部に形成するＰＩＮホトダイオードの
全体の厚さによって選択される。この凹部１０ａの形成
はウエットエッチング又はドライエッチングにより行
い、その側面１０ｂが出来るだけ傾斜するようにしてお
くことが好ましい。この状態を図１（ｂ）に示す。First, a semi-insulating InP substrate 10 is prepared (see FIG. 2A), and a recess 10a having a predetermined depth, for example, a depth of 2 to 3 μm, is formed in the substrate 10. The depth of the recess is selected according to the total thickness of the PIN photodiode formed in the recess. The recess 10a is preferably formed by wet etching or dry etching so that the side surface 10b thereof is inclined as much as possible. This state is shown in FIG.
【００１６】次に、ＰＩＮホトダイオードを構成する半
導体層となるｎ−ＩｎＰ層２１、ｉ−ＧａＩｎＡｓ層２
２をＯＭＶＰＥ法の結晶成長法により、凹部１０ａを形
成した基板１０上に順次成長させる。この状態を図１
（ｃ）に示す。Next, the n-InP layer 21 and the i-GaInAs layer 2 which will be the semiconductor layers forming the PIN photodiode are formed.
2 is sequentially grown on the substrate 10 in which the recess 10a is formed by the crystal growth method of OMVPE method. This state is shown in Figure 1.
It shows in (c).
【００１７】次に、ＳｉＮ膜を形成し、この膜をマスク
としてＺｎ拡散を行い、図１（ｃ）に示すようにＰＩＮ
ホトダイオードのｐ型層となるｐ−ＧａＩｎＡｓ領域２
３を形成する。Next, a SiN film is formed, Zn diffusion is performed using this film as a mask, and a PIN is formed as shown in FIG. 1 (c).
P-GaInAs region 2 serving as p-type layer of photodiode
3 is formed.
【００１８】その後、凹部１０ａ内及び基板上面の半導
体層の不要部分を除去し、図３（ｅ）に示すような構造
にする。これにより、図３（ｅ）に示すように、Ｐ層の
頂部とＮ層の一部が露出される。After that, unnecessary portions of the semiconductor layer in the recess 10a and on the upper surface of the substrate are removed to obtain a structure as shown in FIG. 3 (e). As a result, as shown in FIG. 3E, the top of the P layer and a part of the N layer are exposed.
【００１９】次に、ＳｉＮ膜２４を形成し、Ｎ型電極２
５とＰ型電極２６を形成する。この状態を図３（ｆ）に
示す。Next, the SiN film 24 is formed, and the N-type electrode 2 is formed.
5 and the P-type electrode 26 are formed. This state is shown in FIG.
【００２０】そして、金属膜を基板１０全面に形成し、
パターンニングして、図３（ｇ）に示すように、Ｎ型電
極２５から基板１０の上面に伸びる引出しリード２７
と、Ｐ型電極２６上には電極２８を形成する。上記製造
方法での各層の厚さは、基板上面の引出しリード２７の
上面が電極２８の上面と実質的に同一平面に位置するよ
うに選択する。また、この受光素子では、光は基板裏面
側から入射する。そこで光結合効率をあげるため、ＰＩ
Ｎホトダイオード形成後、基板を薄くし、反射防止膜２
９を形成する。この状態を図３（ｇ）に示す。Then, a metal film is formed on the entire surface of the substrate 10,
After patterning, as shown in FIG. 3G, the extraction lead 27 extending from the N-type electrode 25 to the upper surface of the substrate 10.
Then, an electrode 28 is formed on the P-type electrode 26. The thickness of each layer in the above manufacturing method is selected so that the upper surface of the extraction lead 27 on the upper surface of the substrate is located substantially flush with the upper surface of the electrode 28. Further, in this light receiving element, light is incident from the back surface side of the substrate. Therefore, in order to increase the optical coupling efficiency, PI
After forming the N photodiode, the substrate is thinned to form the antireflection film 2
9 is formed. This state is shown in FIG.
【００２１】本発明は上記実施例に限定されず、種々の
変形例が考えられ得る。The present invention is not limited to the above embodiment, and various modifications can be considered.
【００２２】具体的には、上記実施例では、ｎ型電極と
引出し電極を別々に形成しているが、同時に形成しても
よい。またＰＩＮホトダイオードのｐ型層の形成をＺｎ
拡散で行っているが、この代わりにｐ−ＧａＩｎＡｓ層
を成長させるようにしてもよSpecifically, in the above embodiment, the n-type electrode and the extraction electrode are formed separately, but they may be formed simultaneously. In addition, the formation of the p-type layer of the PIN photodiode is
Although diffusion is performed, a p-GaInAs layer may be grown instead of this.
【００２３】い。Yes.
【発明の効果】本発明の受光素子及びその製造方法で
は、半絶縁性ＩｎＰ基板を用い、ＰＩＮホトダイオード
のＮ型電極を直接引き出しているため、Ｎ型電極での寄
生容量が少ない。これにより、高速応答性を有する受光
素子を実現できる。According to the light-receiving element and the method of manufacturing the same of the present invention, since the semi-insulating InP substrate is used and the N-type electrode of the PIN photodiode is directly drawn out, the parasitic capacitance at the N-type electrode is small. This makes it possible to realize a light receiving element having a high-speed response.
【図１】本発明に従う受光素子の一実施例の断面構造を
示す図である。FIG. 1 is a diagram showing a cross-sectional structure of an embodiment of a light receiving element according to the present invention.
【図２】本発明に従う受光素子の製造方法の一実施例の
前半各工程での受光素子の断面構造を示す図である。FIG. 2 is a diagram showing a cross-sectional structure of the light receiving element in each step of the first half of the embodiment of the method for manufacturing the light receiving element according to the present invention.
【図３】本発明に従う受光素子の製造方法の一実施例の
後半各工程での受光素子の断面構造を示す図である。FIG. 3 is a diagram showing a cross-sectional structure of the light receiving element in each step of the latter half of the embodiment of the method for manufacturing the light receiving element according to the present invention.
【図４】従来のフリップチップボンデイング用の受光素
子の断面構造を示す図である。FIG. 4 is a diagram showing a cross-sectional structure of a conventional light-receiving element for flip-chip bonding.
１…ｎ+ ＩｎＰ基板 １０…半絶縁性ＩｎＰ基板 １０ａ…凹部 １１…ＩｎＰ層 １２…ｉ−ＧａＩｎＡｓ層 １７…引出しリード ２６…Ｐ型電極 ２５…Ｎ型電極1 ... n + InP substrate 10 ... Semi-insulating InP substrate 10a ... Recess 11 ... InP layer 12 ... i-GaInAs layer 17 ... Lead-out lead 26 ... P-type electrode 25 ... N-type electrode
Claims (2)
に、素子搭載面が対向するよう搭載されることにより一
対の引出し電極が前記基板側電極に接続される裏面入射
型受光素子において、 半絶縁性半導体基板上に形成した凹部内に、一方の素子
電極が前記凹部底面側に位置し、他方の素子電極が頂部
に位置するようＰＩＮ型受光部が配設され、前記一対の
引出し電極の一方は前記凹部側面に沿って設けられた引
出しリードを介して前記一方の素子電極に接続されて、
他方の引出し電極が前記他方の素子電極に接続されてい
る受光素子。1. A back-illuminated light-receiving element in which a pair of extraction electrodes are connected to the substrate-side electrodes by being mounted on a supporting substrate provided with a pair of substrate-side electrodes so that element mounting surfaces face each other. A PIN type light receiving portion is disposed in the recess formed on the semi-insulating semiconductor substrate so that one element electrode is located on the bottom surface side of the recess and the other element electrode is located on the top portion, and the pair of extraction electrodes are provided. One is connected to the one element electrode through a lead lead provided along the side surface of the recess,
A light receiving element in which the other extraction electrode is connected to the other element electrode.
させて搭載される受光素子の製造方法において、 半絶縁性半導体基板に凹部を形成する第１の工程と、 前記第１工程で形成した半絶縁性ＩｎＰ半導体基板の凹
部が形成されている面上に下側が一方の電極となり、上
側が他方の電極となるようなｐｉｎ型受光素子を構成す
る半導体結晶層を順次形成する第２工程と、 前記第２工程で形成した半導体結晶層の凹部内の不要部
分を除去しＰＩＮ型受光部の一方の電極となる層を露出
させる第３工程と、 前記第３工程で露出させた層から前記一方の電極を凹部
の外部の前記半絶縁性半導体基板上面に前記凹部側面に
沿って引出す引出しリードを形成する第４工程とを含む
受光素子の製造方法。2. A method for manufacturing a light-receiving element mounted on a substrate provided with electrodes with element mounting surfaces facing each other, comprising: a first step of forming a recess in a semi-insulating semiconductor substrate; and the first step. Secondly forming a semiconductor crystal layer constituting a pin type light receiving element in which the lower side is one electrode and the upper side is the other electrode on the surface of the formed semi-insulating InP semiconductor substrate on which the concave portion is formed. A step, a third step of removing an unnecessary portion in the concave portion of the semiconductor crystal layer formed in the second step to expose a layer to be one electrode of the PIN type light receiving section, and a layer exposed in the third step And a fourth step of forming an extraction lead for extracting the one electrode on the upper surface of the semi-insulating semiconductor substrate outside the recess along the side surface of the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3187884A JP3008571B2 (en) | 1991-07-26 | 1991-07-26 | Light receiving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3187884A JP3008571B2 (en) | 1991-07-26 | 1991-07-26 | Light receiving device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0537005A true JPH0537005A (en) | 1993-02-12 |
| JP3008571B2 JP3008571B2 (en) | 2000-02-14 |
Family
ID=16213888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3187884A Expired - Lifetime JP3008571B2 (en) | 1991-07-26 | 1991-07-26 | Light receiving device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3008571B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744857A (en) * | 1996-01-30 | 1998-04-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2005129776A (en) * | 2003-10-24 | 2005-05-19 | Hamamatsu Photonics Kk | Semiconductor light receiving element |
| JP2005129789A (en) * | 2003-10-24 | 2005-05-19 | Hamamatsu Photonics Kk | Semiconductor light receiving element |
| US7355259B2 (en) | 2002-02-26 | 2008-04-08 | Sumitomo Electric Industries, Ltd. | Photodiode array and optical receiver device including the same |
| JP2016025095A (en) * | 2014-07-16 | 2016-02-08 | 三菱電機株式会社 | Light receiving element |
-
1991
- 1991-07-26 JP JP3187884A patent/JP3008571B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744857A (en) * | 1996-01-30 | 1998-04-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US7355259B2 (en) | 2002-02-26 | 2008-04-08 | Sumitomo Electric Industries, Ltd. | Photodiode array and optical receiver device including the same |
| JP2005129776A (en) * | 2003-10-24 | 2005-05-19 | Hamamatsu Photonics Kk | Semiconductor light receiving element |
| JP2005129789A (en) * | 2003-10-24 | 2005-05-19 | Hamamatsu Photonics Kk | Semiconductor light receiving element |
| JP2016025095A (en) * | 2014-07-16 | 2016-02-08 | 三菱電機株式会社 | Light receiving element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3008571B2 (en) | 2000-02-14 |
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