JPH0537151A - Thin film multilayer circuit formation method - Google Patents
Thin film multilayer circuit formation methodInfo
- Publication number
- JPH0537151A JPH0537151A JP3187372A JP18737291A JPH0537151A JP H0537151 A JPH0537151 A JP H0537151A JP 3187372 A JP3187372 A JP 3187372A JP 18737291 A JP18737291 A JP 18737291A JP H0537151 A JPH0537151 A JP H0537151A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- thin film
- film
- multilayer circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】
【目的】 第3工程で真空引きを行うことにより、ピン
ホールがなく、絶縁ショートやリークの発生が少ない絶
縁膜を有する薄膜多層回路の形成方法を提供する。
【構成】 (第1工程)基板8上に導体9を形成し、
(第2工程)導体9のパターニングを行い、(第3工
程)ポリイミド樹脂溶液を塗布し、真空引きする。(第
4工程)キュアおよびヴィアホールあけを行い、(第5
工程)導体を埋め込み上記工程の繰り返しで薄膜多層回
路を形成する。
(57) [Abstract] [PROBLEMS] To provide a method for forming a thin film multilayer circuit having an insulating film which is free from pinholes and which causes less insulation short circuit and leakage by performing vacuuming in the third step. [Structure] (First Step) The conductor 9 is formed on the substrate 8,
(Second step) The conductor 9 is patterned, (third step) a polyimide resin solution is applied, and a vacuum is drawn. (Fourth step) Cure and via hole opening are performed, and (Fifth step)
Step) Embedding a conductor to repeat the above steps to form a thin film multilayer circuit.
Description
【0001】[0001]
【産業上の利用分野】本発明は、小型化高密度実装を可
能とする回路基板の薄膜多層回路形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a thin film multilayer circuit on a circuit board, which enables miniaturization and high density mounting.
【0002】[0002]
【従来の技術】近年、ポリイミドを絶縁膜とする薄膜多
層回路基板が信号の高速処理を目ざす大型コンピュータ
等に用いられている。以下図面を参照しながら、上述し
た薄膜多層回路の形成方法について説明する。図2は、
従来の薄膜多層回路の形成法を示すものである。2. Description of the Related Art In recent years, thin-film multilayer circuit boards using polyimide as an insulating film have been used in large-scale computers for the purpose of high-speed signal processing. Hereinafter, a method of forming the above-mentioned thin film multilayer circuit will be described with reference to the drawings. Figure 2
1 illustrates a conventional method for forming a thin film multilayer circuit.
【0003】第1工程はアルミナ基板1上に導体膜2
(たとえば、クロム膜500Å,銅膜5μm,クロム膜
500Åを積層した膜)をスパッタリング法によって形
成する工程である。第2工程は第1工程で形成した膜の
パターニングを行う工程であり、たとえばホトリソグラ
フィー法(レジストを約1μm塗布し、露光,現像,エ
ッチング,レジスト除去の一連の工程を経て、パターニ
ングする方法)によってパターニングを行う。第3工程
は絶縁膜としてのポリイミド樹脂溶液3を塗布する工程
であり、たとえばスピンコート法によって光硬化性のポ
リイミド樹脂溶液3を基板1上に約20μm厚に塗布形
成する。第4工程はポリイミド樹脂溶液3にヴィアホー
ル4を形成する工程であり、第3工程でポリイミド樹脂
溶液3を塗布形成した後、約80℃2時間プリキュアを
行い、ホトマスクを通して基板1上のポリイミドに樹脂
溶液3を露光,現像しヴィアホール4を形成する。現像
後約400℃でキュアを行いポリイミド膜5を形成す
る。第5工程はヴィアホール4上下の配線導体を接続す
るためにヴィアホール4内へ導体6(銅膜)を埋め込む
工程であり、たとえば、無電解メッキあるいは電解メッ
キ法によって導体6を埋込む。薄膜多層基板7は、以上
説明した第1工程から第5工程を繰り返すことにより形
成される。The first step is to form a conductor film 2 on an alumina substrate 1.
This is a step of forming (for example, a film in which a chromium film 500Å, a copper film 5 μm, and a chromium film 500Å are laminated) by a sputtering method. The second step is a step of patterning the film formed in the first step, for example, a photolithography method (a method of applying a resist of about 1 μm, and patterning through a series of steps of exposure, development, etching, and resist removal). Patterning is performed. The third step is a step of applying the polyimide resin solution 3 as an insulating film. For example, the photocurable polyimide resin solution 3 is applied and formed on the substrate 1 to a thickness of about 20 μm by a spin coating method. The fourth step is a step of forming the via holes 4 in the polyimide resin solution 3. After the polyimide resin solution 3 is applied and formed in the third step, pre-cure is performed at about 80 ° C. for 2 hours, and the polyimide on the substrate 1 is exposed through a photomask. The resin solution 3 is exposed and developed to form a via hole 4. After development, curing is performed at about 400 ° C. to form a polyimide film 5. The fifth step is a step of embedding the conductor 6 (copper film) in the via hole 4 in order to connect the wiring conductors above and below the via hole 4, for example, by embedding the conductor 6 by electroless plating or electrolytic plating. The thin film multilayer substrate 7 is formed by repeating the first to fifth steps described above.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上記第
3工程の方法では、アルミナ基板1上にポリイミド樹脂
溶液3をたとえばスピンコート法によって塗布した場
合、溶液中に気泡が含まれることがある。そのため塗布
後キュアした場合、ポリイミド膜3中に気泡がとり込ま
れたままになり、絶縁膜としての機能を発揮せずポリイ
ミド膜3の上下の配線導体間のショートあるいはリーク
の原因となる。However, in the method of the third step, when the polyimide resin solution 3 is applied onto the alumina substrate 1 by, for example, the spin coating method, the solution may contain bubbles. Therefore, when cured after coating, air bubbles remain trapped in the polyimide film 3, failing to function as an insulating film, and cause a short circuit or a leak between the upper and lower wiring conductors of the polyimide film 3.
【0005】本発明は上記従来の課題を解決するもの
で、ポリイミド膜の気泡の発生を防止した薄膜多層回路
の形成方法を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method for forming a thin film multilayer circuit which prevents the generation of bubbles in a polyimide film.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の薄膜多層回路形成方法では、前記第3工程
で基板上に樹脂溶液をスピンコート法で塗布し、真空容
器内で減圧状態にさらした後プリキュアし、さらにホト
マスクを通して露光および現像を行い最終キュアを行う
方法を採用している。In order to achieve the above object, in the thin film multilayer circuit forming method of the present invention, the resin solution is applied onto the substrate by spin coating in the third step, and the pressure is reduced in a vacuum container. A method of pre-curing after exposing to the state, and then performing final exposure by developing and exposing through a photomask is adopted.
【0007】[0007]
【作用】減圧によって樹脂膜の気泡はなくなり、絶縁シ
ョートまたはリークの発生は低減する。Function The bubbles in the resin film are eliminated by the reduced pressure, and the occurrence of insulation short circuit or leak is reduced.
【0008】[0008]
【実施例】以下本発明の実施例の薄膜多層回路形成方法
を図面を参照しながら説明する。図1は、本発明の実施
例における薄膜多層回路形成方法の工程図である。第1
工程はアルミナ基板8上に導体膜9(たとえばクロム膜
500Å,銅膜5μm,クロム膜500Å)をスパッタ
リング法によって形成する工程である。第2工程は第1
工程で形成した導体膜9をホトリングラフィー法によっ
てパターニングを行う工程である。第3工程は絶縁膜と
してのポリイミド樹脂溶液10(本実施例では光硬化性
のポリイミド樹脂溶液を用いた)アルミナ基板8上にス
ピンコート法によって約20μm厚に塗布形成した後、
真空容器内に置き、真空引きし、約5Torr1分間減
圧中にさらす工程である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film multilayer circuit forming method according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process diagram of a method for forming a thin film multilayer circuit in an embodiment of the present invention. First
The step is a step of forming a conductor film 9 (for example, a chromium film 500Å, a copper film 5 μm, a chromium film 500Å) on the alumina substrate 8 by a sputtering method. The second step is the first
This is a step of patterning the conductor film 9 formed in the step by a photolinography method. In the third step, a polyimide resin solution 10 (using a photocurable polyimide resin solution in this embodiment) as an insulating film is applied on the alumina substrate 8 by a spin coating method to a thickness of about 20 μm,
It is a step of placing in a vacuum container, evacuating, and exposing to reduced pressure for about 1 Torr for 1 minute.
【0009】第4工程はポリイミド樹脂溶液10にヴィ
アホール11を形成し、キュアを行いポリイミド膜12
を形成する工程である。上記第3工程でポリイミド樹脂
溶液10を塗布形成後、減圧中にさらした後、約80℃
2時間プリキュアを行い、ホトマスクを通してアルミナ
基板8上のポリイミド樹脂溶液10を露光および現像し
てヴィアホール11を形成する。現像後約400℃でキ
ュアを行いポリイミド膜12を形成する。第5工程はヴ
ィアホール11上下の配線導体を接続するために、ヴィ
アホール11内へ導体13(銅膜)を埋め込む工程であ
り、たとえば無電解メッキあるいは電解メッキ法によっ
て導体13を埋め込む。薄膜多層基板14は、以上説明
した第1工程から第5工程を繰り返すことにより形成さ
れる。In the fourth step, the via holes 11 are formed in the polyimide resin solution 10 and the polyimide resin 12 is cured.
Is a step of forming. After the polyimide resin solution 10 was applied and formed in the third step, it was exposed to a reduced pressure and then heated to about 80 ° C.
Precure is performed for 2 hours, and the polyimide resin solution 10 on the alumina substrate 8 is exposed and developed through a photomask to form a via hole 11. After development, curing is performed at about 400 ° C. to form the polyimide film 12. The fifth step is a step of embedding the conductor 13 (copper film) in the via hole 11 in order to connect the wiring conductors above and below the via hole 11, and the conductor 13 is embedded by, for example, electroless plating or electrolytic plating. The thin film multilayer substrate 14 is formed by repeating the first to fifth steps described above.
【0010】以上のように本実施例によれば、アルミナ
基板8上にポリイミド樹脂溶液10をスピンコート法に
よって塗布形成した後、真空容器内で5Torr、約1
分間減圧下に保持することにより、スピンコート法で滴
下形成したポリイミド樹脂溶液10中の気泡が外部に放
出れさ、そのためキュア後ポリイミド膜に中には気泡が
皆無となり、ポリイミド膜12の上下配線間の絶縁ショ
ートまたはリークの発生を低減することができる。As described above, according to the present embodiment, after the polyimide resin solution 10 is applied and formed on the alumina substrate 8 by the spin coating method, the pressure is set to about 1 Torr in the vacuum container at about 1 Torr.
By holding under reduced pressure for a minute, air bubbles in the polyimide resin solution 10 formed by the spin coating method are released to the outside, so that after curing, there are no air bubbles in the polyimide film, and the upper and lower wirings of the polyimide film 12 are eliminated. It is possible to reduce the occurrence of insulation short circuit or leakage between them.
【0011】なお上記実施例において、基板アルミナ基
板としたが、シリコン基板,ガラス基板または絶縁膜を
形成した金属(たとえばアルミ)基板でもかまわない。
また上記実施例において、ポリイミド樹脂溶液10を光
硬化性としたが、熱硬化性のポリイミド樹脂溶液でも同
じ効果が得られる。また上記実施例において、絶縁膜と
してポリイミド樹脂溶液としたが、他の硬化性樹脂溶液
でも同じ効果が得られる。また上記実施例において、第
3工程での真空引きを5Torr,1分間としたが、特
にこれに限定されたものではなく真空に引けば引く程、
時間は短くても良いし、逆に真空度が悪ければ、時間を
長くする必要がある。In the above embodiment, the substrate is an alumina substrate, but a silicon substrate, a glass substrate or a metal (for example, aluminum) substrate having an insulating film formed thereon may be used.
Further, although the polyimide resin solution 10 is made to be photo-curable in the above-mentioned embodiment, the same effect can be obtained by using a thermosetting polyimide resin solution. In addition, although the polyimide resin solution is used as the insulating film in the above-described embodiment, the same effect can be obtained with other curable resin solutions. Further, in the above embodiment, the vacuuming in the third step was set to 5 Torr for 1 minute, but it is not particularly limited to this, and the more the vacuum is pulled,
The time may be short, or conversely, if the degree of vacuum is bad, it is necessary to lengthen the time.
【0012】[0012]
【発明の効果】以上の説明で明らかなように本発明によ
れば、基板上に樹脂溶液を塗布した後、減圧下に保持す
ることにより、塗布した樹脂溶液中の気泡が外部に放出
される。そのためキュア後、樹脂膜(絶縁膜)中には気
泡が皆無となり、絶縁膜中の上下配線間の絶縁ショート
またはリークの発生を低減することができる。As is apparent from the above description, according to the present invention, after the resin solution is applied onto the substrate and then kept under reduced pressure, the bubbles in the applied resin solution are released to the outside. . Therefore, after the curing, there are no bubbles in the resin film (insulating film), and it is possible to reduce the occurrence of insulation short circuit or leak between the upper and lower wirings in the insulating film.
【図1】本発明の薄膜多層回路形成法の工程を示す図FIG. 1 is a diagram showing steps of a thin film multilayer circuit forming method of the present invention.
【図2】従来の薄膜多層回路形成法の工程を示す図FIG. 2 is a diagram showing steps of a conventional thin film multilayer circuit forming method.
8 基板 9 導体 10 ポリイミド樹脂溶液(絶縁塗膜) 11 ヴィアホール 12 絶縁膜 13 導体(ヴィアホールに埋め込む導体) 8 substrate 9 conductor 10 polyimide resin solution (insulating coating film) 11 via hole 12 insulating film 13 conductor (conductor embedded in via hole)
Claims (1)
の導体をパターニングする第2工程と、この導体を形成
した基板上に絶縁膜を形成する第3工程と、この絶縁膜
にヴィアホールを形成する第4工程と、このヴィアホー
ルに導体を埋め込む第5工程とを有し、上記第3工程で
は基板上に塗布形成した絶縁塗膜を真空引きした後キュ
アして絶縁膜を形成しており、上記工程の繰り返しによ
って行われる薄膜多層回路形成方法。Claims: 1. A first step of forming a conductor on a substrate, a second step of patterning the conductor, and a third step of forming an insulating film on the substrate on which the conductor is formed. A fourth step of forming a via hole in this insulating film, and a fifth step of embedding a conductor in this via hole. In the third step, the insulating coating film formed by coating on the substrate is evacuated and then cured. And an insulating film is formed, and a thin film multilayer circuit forming method is performed by repeating the above steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3187372A JPH0537151A (en) | 1991-07-26 | 1991-07-26 | Thin film multilayer circuit formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3187372A JPH0537151A (en) | 1991-07-26 | 1991-07-26 | Thin film multilayer circuit formation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0537151A true JPH0537151A (en) | 1993-02-12 |
Family
ID=16204857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3187372A Pending JPH0537151A (en) | 1991-07-26 | 1991-07-26 | Thin film multilayer circuit formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0537151A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7935893B2 (en) | 2008-02-14 | 2011-05-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8024858B2 (en) | 2008-02-14 | 2011-09-27 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8291584B2 (en) | 2008-06-02 | 2012-10-23 | Ibiden Co., Ltd. | Method of manufacturing a printed wiring board with built-in electronic component |
| US8327533B2 (en) | 2008-03-21 | 2012-12-11 | Ibiden Co., Ltd. | Printed wiring board with resin complex layer and manufacturing method thereof |
| US8710374B2 (en) | 2008-03-12 | 2014-04-29 | Ibiden Co., Ltd. | Printed wiring board with reinforced insulation layer and manufacturing method thereof |
-
1991
- 1991-07-26 JP JP3187372A patent/JPH0537151A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7935893B2 (en) | 2008-02-14 | 2011-05-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8024858B2 (en) | 2008-02-14 | 2011-09-27 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8336205B2 (en) | 2008-02-14 | 2012-12-25 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8613136B2 (en) | 2008-02-14 | 2013-12-24 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8710374B2 (en) | 2008-03-12 | 2014-04-29 | Ibiden Co., Ltd. | Printed wiring board with reinforced insulation layer and manufacturing method thereof |
| US8327533B2 (en) | 2008-03-21 | 2012-12-11 | Ibiden Co., Ltd. | Printed wiring board with resin complex layer and manufacturing method thereof |
| US8291584B2 (en) | 2008-06-02 | 2012-10-23 | Ibiden Co., Ltd. | Method of manufacturing a printed wiring board with built-in electronic component |
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