JPH0537330A - Multistage logic circuit - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a multi-stage logic circuit which is hardly affected by variations in temperature and power supply voltage. An intermediate voltage of differential outputs of the logic circuits (10, 20, 30) of each stage is detected by an average value detection unit (14, 24, 34), and this value is detected by the logic circuit (20, 30) is applied as a reference voltage to the input buffer section (21, 31). For this reason, it is possible to apply a reference voltage with less variation in voltage level to each logic circuit (20, 30) without providing each logic circuit with a highly accurate reference voltage generator. Therefore, it is possible to realize the interface between the logic circuits that always maximizes the noise margin regardless of the fluctuation of the temperature power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interface technology for a single-phase input / differential output type multi-stage logic circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional multi-stage logic circuit in which a plurality of single-phase input / differential output type logic circuits are connected. From the figure, the conventional multi-stage logic circuit includes a first logic circuit 110, a second logic circuit
It is an n-stage logic circuit in which a logic circuit 120 and an nth logic circuit 130 are connected. Each logic circuit is provided with an input reference voltage generator 111, 121, 131 and an output level adjustment voltage generator 112, 122, 132, respectively. Then, the input reference voltage generator 1
The logic determination is performed in each logic circuit using the reference voltage given from 11, 121, 131 as a threshold value.

[0003]

By the way, such a conventional multi-stage logic circuit is provided with an input reference voltage generator for each logic circuit of each stage, and the generated voltage of each input reference voltage generator is There were variations. Further, since the temperature characteristics and the power supply voltage fluctuation characteristics are different in each input reference voltage generating section, the logic decision level may vary. Then, due to these variations, there is a problem that a good interface cannot be obtained between the logic circuits and the noise margin is reduced.

The present invention aims to solve such problems.

[0005]

In order to solve the above-mentioned problems, the multi-stage logic circuit of the present invention applies the intermediate voltage of the differential output of each stage logic circuit to the input buffer section of the next stage logic circuit. Use as reference voltage.

[0006]

According to the multi-stage logic circuit of the present invention, the intermediate voltage of the differential output of each stage logic circuit is applied to the input buffer section of the next stage logic circuit as a reference voltage. Therefore, even if the differential output given as the input signal of the next stage fluctuates due to fluctuations in temperature and power supply voltage, the reference voltage also fluctuates, so the voltage value of the input signal and the voltage value of the reference voltage The relative value of is constant.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a circuit diagram showing the configuration of the multi-stage logic circuit of this embodiment. From the figure, in the multi-stage logic circuit of the present embodiment, a first logic circuit 10, a second logic circuit 20, and an nth logic circuit 3 which are single-phase input / differential output type logic circuits.
0 is provided. The first logic circuit 10 includes an input buffer unit 11 that compares an input signal using the reference voltage generated by the input reference voltage generation unit 5, a logic unit 12 that performs a logical operation, and an output signal from the logic unit 12. Output as a differential output signal, an average value detection unit 14 for detecting an average value of the differential output signals from the output buffer unit 13, and a voltage for level adjustment given to the output buffer unit 13. And an output level adjusting voltage generator 15 for controlling the output level. Then, the intermediate voltage signal of the differential output averaged by the average value detector 14 is given to the second logic circuit 20 in the next stage. Next, the second logic circuit 2
At 0, an input buffer unit 21 that compares the input signal with the intermediate voltage signal from the average value detection unit 14, a logic unit 22 that performs a logical operation, and an output signal from the logic unit 22 is output as a differential output signal. The output buffer unit 23, an average value detection unit 24 that detects the average value of the differential output signals from the output buffer unit 23, and an output level adjustment voltage generation unit 25 that generates a voltage for level adjustment given to the output buffer unit 23. And are provided. The third to nth logic circuits 30 have the same circuit configuration.

Next, the operation of this embodiment will be described. In this embodiment, the non-inverted output of the differential output of the first logic circuit 10 is given to the input buffer 21 of the second logic circuit 20 as an input signal. Further, the average value of the inverted output and the non-inverted output which are the differential output of the first logic circuit 10 is detected by the average value detection unit 14, and this average voltage is used as the reference voltage in the input buffer unit 21 of the second logic circuit 20. Given. Here, when the differential output of the first logic circuit 10 fluctuates due to fluctuations in temperature or power supply voltage, the voltage value of the input signal given to the input buffer unit 21 of the second logic circuit 20 and the voltage value of the reference voltage signal are Both fluctuate. This is because both the input signal and the reference voltage signal are created based on the differential output of the first logic circuit 10. Therefore, the relative values of these voltage values are constant, and the logic judgment level is also constant. Therefore, it is not necessary to provide a highly accurate input reference voltage generator in each stage logic circuit, and a large noise margin can be secured.

Next, a circuit configuration example of the average value detecting section 14 provided in the first logic circuit 10 will be described with reference to the circuit diagram of FIG. The average value detection unit 14 includes a resistor 14a and a resistor 14b connected in series, and a capacitor 14c whose one end is grounded. An inverted output signal and a non-inverted output signal from the output buffer unit 13 are given to the average value detection unit 14, and an intermediate value of these signal voltages is taken by resistance division by the resistors 14a and 14b and stabilized by the capacitor 14c. And then output. This circuit configuration example can also be applied to the average value detection units 24 and 34. Then, when the average value detection units 14, 24, 34 of the embodiment of FIG. 1 are replaced with this circuit, the circuit diagram of FIG. 3 is obtained.

In this embodiment, the ECL (Emitter Coup
It is effective when used for a GaAs IC that is compatible with led logic).

[0011]

According to the multi-stage logic circuit of the present invention, the intermediate voltage of the differential output of each stage logic circuit is applied as the reference voltage to the input buffer section of the next stage logic circuit. Therefore, it is possible to provide each logic circuit with a reference voltage with less variation in voltage level without providing each logic circuit with a highly accurate reference voltage generator.

Therefore, it is possible to realize the interface between the logic circuits which always maximizes the noise margin regardless of the fluctuation of the temperature power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a multi-stage logic circuit according to an embodiment.

FIG. 2 is a circuit diagram showing a configuration of an average value detection unit.

FIG. 3 is a circuit diagram showing a configuration of a multi-stage logic circuit of this embodiment.

FIG. 4 is a circuit diagram showing a configuration of a conventional multi-stage logic circuit.

[Explanation of symbols]

 5 ... Input reference voltage generating section 10 ... First logic circuit 20 ... Second logic circuit 30 ... Third logic circuit 11, 21, 31 ... Input buffer section 12, 22, 32 ... Logic section 13, 23, 33 ... Output buffer Units 14, 24, 34 ... Average value detecting unit 15, 25, 35 ... Output level adjusting voltage generating unit

Claims (1)

Claim: What is claimed is: 1. A multi-stage logic circuit comprising: an input buffer unit for comparing input signals with a reference voltage; A multi-stage logic circuit, wherein the intermediate voltage of the differential output of the logic circuit is used as a reference voltage to be applied to the input buffer section of the logic circuit at the next stage.