JPH0537331A - Multistage logic circuit - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a multi-stage logic circuit which is hardly affected by variations in temperature and power supply voltage. [Structure] Intermediate voltage of differential output of the logic circuit (10, 20, 30) of each stage, and the logic circuit (20, 30) of the next stage
The reference voltage generated by the reference voltage generation unit (21, 31) is compared by the voltage comparison unit (16, 26, 36). If it is found from these comparison results that these voltage values do not match, the control voltage generator (17, 27, 37)
Adjusts the differential output by changing the output level adjustment voltage. By adjusting the differential output, the average voltage value of the differential output and the voltage value of the reference voltage of the logic circuit (20, 30) at the next stage can be matched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interface technology for a single-phase input / differential output type multi-stage logic circuit.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional multi-stage logic circuit in which a plurality of single-phase input / differential output type logic circuits are connected. From the figure, the conventional multi-stage logic circuit includes a first logic circuit 110, a second logic circuit
It is an n-stage logic circuit in which a logic circuit 120 and an nth logic circuit 130 are connected. Each logic circuit has an input reference voltage generation circuit 111, 121, 131 and an output level adjustment voltage generation circuit 112, 122, 132, respectively.
Is provided. Then, the logic determination is performed in each logic circuit using the reference voltage provided from the input reference voltage generation circuits 111, 121, 131 as a threshold value.

[0003]

By the way, such a conventional multi-stage logic circuit is provided with an input reference voltage generation circuit for each logic circuit of each stage, and the generated voltage of each input reference voltage generation circuit is different. There were variations. Further, since the temperature characteristics and the power supply voltage variation characteristics are different in each input reference voltage generation circuit, the logic decision level may vary. Then, due to these variations, there is a problem that a good interface cannot be obtained between the logic circuits and the noise margin is reduced.

The present invention aims to solve such problems.

[0005]

In order to solve the above-mentioned problems, in the multi-stage logic circuit of the present invention, the intermediate voltage of the differential output of the logic circuit of each stage and the reference voltage generating section of the logic circuit of the next stage. And a control voltage generator that generates an output level adjustment voltage whose voltage values match from the comparison result of the voltage comparator.

[0006]

According to the multi-stage logic circuit of the present invention, the intermediate voltage of the differential output of the logic circuit of each stage and the reference voltage generated by the reference voltage generating unit of the logic circuit of the next stage are generated in the voltage comparison unit. Be compared. When it is found from these comparison results that these voltage values do not match, the control voltage generation unit changes the output level adjustment voltage to adjust the differential output (feedback control). By adjusting the differential output, the intermediate voltage value of the differential output and the voltage value of the reference voltage of the logic circuit at the next stage can be matched.

Therefore, when the reference voltage of the logic circuit in the next stage fluctuates due to fluctuations in temperature or power supply voltage, feedback control in the control voltage generating section works to adjust the output level adjusting voltage according to the reference voltage. It By this adjustment, the voltage value of the differential output always becomes a value that matches the reference voltage of the logic circuit in the next stage.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a circuit diagram showing the configuration of the multi-stage logic circuit of this embodiment. As shown in the figure, the multi-stage logic circuit of this embodiment includes a first logic circuit 10, a second logic circuit 20, and an nth logic circuit 30. First logic circuit 10
Includes an input reference voltage generation unit 11, an input buffer unit 12 to which a reference voltage that is a reference voltage generated by the input reference voltage generation unit 11 and an input signal are given, a logic unit 13 that performs a logical operation, and a logic unit. The output buffer unit 14 that differentially outputs the output signal from the unit 13, the average value detection unit 15 that detects the average value of the differential output from the output buffer unit 14, and the differential value that is detected by the average value detection unit 15. A voltage comparison unit 16 that compares the output intermediate voltage V ₂ with the reference voltage V ₁ from the second logic circuit 20,
A control voltage generation unit 17 is provided for adjusting the voltage value of the differential output output from the output buffer unit 14 based on the comparison result of the voltage comparison unit 16. Next, in the second logic circuit 20, an input reference voltage generation unit 21, an input buffer unit 22 to which the reference voltage generated by the input reference voltage generation unit 21 and an input signal are given, and a logic unit that performs a logical operation. 23, an output buffer unit 24 that differentially outputs the output signals from the logic unit 23, and an output buffer unit 24
Average value detection unit 25 for detecting the average value of the differential output from
And a voltage comparison unit 26 that compares the intermediate output voltage V ₂ of the differential output detected by the average value detection unit 25 with the reference voltage V ₁ from the third logic circuit, and a comparison by the voltage comparison unit 26. A control voltage generation unit 27 is provided for adjusting the voltage value of the differential output output from the output buffer unit 24 based on the result. The third to nth logic circuits 30 have the same circuit configuration. However, the nth logic circuit 30
As the reference voltage V ₁ given to the voltage comparison unit of ( ₁₎ , the reference voltage generated by the input reference circuit 31 is used because there is no next-stage logic circuit.

Next, the operation of this embodiment will be described. In this embodiment, the average value V ₂ of the inverted output and the non-inverted output which is the differential output of the first logic circuit 10 and the reference voltage signal V ₁ generated by the input reference voltage generator 21 of the second logic circuit 20. And are compared by the voltage comparison unit 16. Then, when it is determined by the signal of the comparison result given from the voltage comparison unit 16 to the control voltage generation unit 17 that these voltage values do not match, the control voltage generation unit 17 changes the output level adjustment voltage V _cs . Let Due to this change in the output level adjustment voltage V _cs , the average voltage value V _{2 of the} differential output
Changes in a direction in which it becomes equal to the reference voltage V ₁ of the second logic circuit 20. Here, assuming that the voltage comparison unit 16 and the control voltage generation unit 17 take a response as shown in FIG. 2, the output level adjustment voltage V _cs is feedback-controlled until V ₂ −V ₁ = 0V, and finally Vs is reached. ₁ = V ₂ . Therefore, when the reference voltage V ₁ of the second logic circuit 20 fluctuates due to fluctuations in temperature or power supply voltage, the feedback control in the control voltage generator 17 operates and the output level adjustment voltage V ₂ becomes the reference voltage V ₁ . Adjusted accordingly. By this adjustment, the voltage value of the differential output always holds the value that matches the reference voltage V ₁ of the logic circuit in the next stage.

Next, FIG. 3 and FIG. 4 show circuit configuration diagrams using a two-input logic circuit which is an application example of this embodiment. Figure 3
Is different from the logic circuit 40 shown in FIG.
This is a point that two sets of the input buffer units 41 and 42 and two sets of the input reference voltage generation units 43 and 44 are provided. Therefore, the logic unit 45 is given two input signals. The logic circuit 70 and the logic circuit 80 of FIG. 4 are realized by using the logic circuit 40. In the circuit configuration of FIG. 4, the reference voltage of each logic circuit is set near -1.3 V, and V _CS0 is set so that the high / low levels of the data output are near -0.9 V and -1.7 V, respectively. By setting, the maximum noise margin can always be obtained. Further, with respect to the logic circuit 80 at the final stage, the ECL output level can be achieved by inputting its own V _ref1 to V _{ref in} .

In this embodiment, the ECL (Emitter Coup
It is effective when used for a GaAs IC that is compatible with led logic).

[0012]

According to the multi-stage logic circuit of the present invention, when the reference voltage of the next-stage logic circuit fluctuates due to fluctuations in temperature or power supply voltage, feedback control in the control voltage generating section works and the output level is increased. The adjustment voltage is adjusted according to the reference voltage. By this adjustment, the voltage value of the differential output always becomes a value that matches the reference voltage of the logic circuit in the next stage.

Therefore, by using the multi-stage logic circuit of the present invention, it is possible to realize an interface in which the noise margin is always maximized regardless of variations in temperature and power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a multi-stage logic circuit according to an embodiment.

FIG. 2 is a diagram showing responses of a voltage comparison unit and a control voltage generation unit.

FIG. 3 is a circuit diagram showing an application example of the present invention.

FIG. 4 is a circuit diagram showing an application example of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional multi-stage logic circuit.

[Explanation of symbols]

 10 ... 1st logic circuit 20 ... 2nd logic circuit 30 ... 3rd logic circuit 11, 21, 31 ... Input reference voltage generation part 12, 22, 32 ... Input buffer part 13, 23, 33 ... Logic part 14, 24, 34 ... Output buffer section 15, 25, 35 ... Average value detection section 16, 26, 36 ... Voltage comparison section 17, 27, 37 ... Control voltage generation section

Claims (1)

Claim: What is claimed is: 1. A reference voltage generating section, an input buffer section for comparing an input signal with a reference voltage generated by the reference voltage generating section, and a logical operation to which an output level adjusting voltage is applied. In a multi-stage logic circuit in which a plurality of logic circuits each including an output buffer section for differentially outputting a result are connected, an intermediate voltage of the differential output of each stage logic circuit and the reference voltage of the next stage logic circuit A voltage comparison unit that compares a reference voltage generated by the generation unit, and a control voltage generation unit that generates an output level adjustment voltage whose voltage values match from the comparison result of the voltage comparison unit. Multi-stage logic circuit.