JPH0538802U - Chip thermistor - Google Patents

Chip thermistor

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Publication number
JPH0538802U
JPH0538802U JP8769391U JP8769391U JPH0538802U JP H0538802 U JPH0538802 U JP H0538802U JP 8769391 U JP8769391 U JP 8769391U JP 8769391 U JP8769391 U JP 8769391U JP H0538802 U JPH0538802 U JP H0538802U
Authority
JP
Japan
Prior art keywords
chip thermistor
solder
metal coating
electrode
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8769391U
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Japanese (ja)
Other versions
JP2569936Y2 (en
Inventor
信之 三木
吾郎 武内
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TDK Corp
Original Assignee
TDK Corp
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Priority to JP1991087693U priority Critical patent/JP2569936Y2/en
Publication of JPH0538802U publication Critical patent/JPH0538802U/en
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Publication of JP2569936Y2 publication Critical patent/JP2569936Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

(57)【要約】 【目的】 耐熱性に優れ、基板実装後の抵抗変化率が低
い安定したチップサーミスタを提供する。 【構成】 略方形状セラミック素体8と、この素体の両
端に互いに絶縁され形成された端部電極9a,9bを有
するチップサーミスタ7において、前記端部電極表面に
電解メッキ法によって鉛から成る第1の金属被膜10
a,10bを形成し、その後、前記第1の金属被膜の表
面に電解メッキ法によって錫から成る第2の金属被膜1
1a,11bを形成する。それにより、実装時の半田濡
れ性が良くなり、さらに、半田耐熱性が向上するため端
部電極の半田食われが減少されるとともに、基板実装後
におけるチップサーミスタの抵抗変化率及び抵抗の経時
変化を大幅に低減することのできる安定度の高いチップ
サーミスタを提供することができる。
(57) [Abstract] [Purpose] To provide a stable chip thermistor having excellent heat resistance and a low resistance change rate after mounting on a substrate. In a chip thermistor 7 having a substantially rectangular ceramic body 8 and end electrodes 9a and 9b formed on both ends of the body, the tip thermistor 7 is made of lead by electrolytic plating. First metal coating 10
a and 10b are formed, and then a second metal coating 1 made of tin is formed on the surface of the first metal coating by electrolytic plating.
1a and 11b are formed. As a result, the solder wettability at the time of mounting is improved, the solder heat resistance is improved, and the solder erosion of the end electrodes is reduced. It is possible to provide a highly stable chip thermistor capable of significantly reducing

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、板状又は略方形状,柱状,円筒状のセラミック素体を有するチップ サーミスタに関する。 The present invention relates to a chip thermistor having a plate-shaped or substantially rectangular, columnar, or cylindrical ceramic body.

【0002】[0002]

【従来の技術】[Prior Art]

チップサーミスタは、セラミック材料の焼結体である板状又は略方形状,柱状 ,円筒状セラミック素体の両端部に、銀,パラジウム合金(Ag/Pd),銅( Cu)等の端部電極が互いに絶縁されて形成されたものである。 A chip thermistor is a plate-shaped or substantially rectangular, columnar, or cylindrical ceramic body that is a sintered body of a ceramic material, and has end electrodes made of silver, palladium alloy (Ag / Pd), copper (Cu), or the like at both ends. Are insulated from each other.

【0003】 図4にチップサーミスタの一従来例を示す。FIG. 4 shows a conventional example of a chip thermistor.

【0004】 このチップサーミスタ1は平板状セラミック素体2の両端部に形成された第1 の端部電極3aと第2の端部電極3bとを有して成り、図5に示すように、前記 第1の端部電極3aと前記第2の端部電極3bが半田5により半田付けされるこ とによって所望のプリント基板6に実装される。The chip thermistor 1 has a first end electrode 3a and a second end electrode 3b formed at both ends of a flat ceramic body 2, and as shown in FIG. The first end electrode 3a and the second end electrode 3b are soldered with the solder 5 to be mounted on a desired printed circuit board 6.

【0005】 ところが、この半田付けの際、端部電極3a,3bが溶融した半田5によって 加熱され、端部電極材が、一部半田中に冶金的性質の拡散により移行し、一般に 半田食われと呼ばれる電極の移行現象が起きる。However, at the time of this soldering, the end electrodes 3a and 3b are heated by the melted solder 5, and the end electrode material partially migrates into the solder due to diffusion of metallurgical properties, and the solder is generally eaten away. The phenomenon of migration of electrodes, called

【0006】 この半田食われによる影響に対し、電極材料を選択することで、これを抑制す ることが可能となり、例えば電極材料としてAg/Pd合金を用いた場合、Pd の含有量を増やすことで半田食われを減少できるが、Pdは高価なため、コスト 増となる。It is possible to suppress the influence of solder erosion by selecting an electrode material. For example, when an Ag / Pd alloy is used as the electrode material, the Pd content should be increased. However, the solder erosion can be reduced, but the cost is increased because Pd is expensive.

【0007】 また半田溶融加熱により、前記半田食われ以外に、プリント基板6上の実装後 におけるチップサーミスタ1の抵抗値が変化する。In addition to the solder erosion, the resistance value of the chip thermistor 1 after mounting on the printed circuit board 6 changes due to the melting and heating of the solder.

【0008】 上記欠点の解決手段として、前記端部電極表面に、鉛,錫等から成る半田ペー ストを印刷塗布し、その後、熱処理することにより金属被膜を形成することも考 えられる。As a means for solving the above-mentioned drawback, it can be considered that a solder paste made of lead, tin or the like is printed and applied on the surface of the end electrode, and then heat treatment is performed to form a metal film.

【0009】 しかし、この方法によると、熱処理回数が多くなるため、平板状セラミック素 体の受ける熱ストレスがより大きくなり、プリント基板6上への実装後における チップサーミスタの抵抗値が低下し、さらには抵抗値の経時変化も大きくなると いう問題を生ずるHowever, according to this method, since the number of heat treatments increases, the thermal stress applied to the flat plate-shaped ceramic body becomes larger, and the resistance value of the chip thermistor after mounting on the printed circuit board 6 decreases, and Causes a problem that the resistance change with time also increases

【0010】[0010]

【考案が解決しようとする課題】[Problems to be solved by the device]

このように、従来はチップサーミスタを半田付けすることによってプリント基 板等に実装するため、その伝熱による電極の半田食われを生じ、基板実装後のチ ップサーミスタの抵抗値が変化するという問題があった。 As described above, conventionally, the chip thermistor is mounted on a printed circuit board by soldering, so that the heat transfer from the chip causes solder erosion, which changes the resistance value of the chip thermistor after board mounting. there were.

【0011】 そこで本考案は上記事情に鑑みてなされたものであり、実装時の半田濡れ性が 良く、実装後におけるチップサーミスタの抵抗値の変化及びその経時変化の少な い、半田耐熱性の優れたチップサーミスタを提供することを目的とするものであ る。Therefore, the present invention has been made in view of the above circumstances, and has good solder wettability at the time of mounting, little change in resistance value of the chip thermistor after mounting and little change with time, and excellent solder heat resistance. It is intended to provide a chip thermistor.

【0012】[0012]

【課題を解決するための手段】[Means for Solving the Problems]

上記目的を達成するために本考案は、板状又は略方形状,柱状,円筒状セラミ ック素体と、この素体の両端に互いに絶縁され形成された端部電極を有するチッ プサーミスタにおいて、前記端部電極の表面に金属被膜を電解メッキ法により形 成する。また前記金属被膜が錫からなるか、あるいは前記金属被膜が鉛を第1層 とし、錫を第2層とする2層構造からなる。さらに、前記端部電極が、パラジウ ム50%以上を含む金属を酸素雰囲気中で焼き付け処理した後、還元または中性 雰囲気中で熱処理形成されたことを特徴とするものである。 In order to achieve the above object, the present invention provides a chip thermistor having a plate-shaped or substantially rectangular-shaped, column-shaped, cylindrical ceramic element body and end electrodes that are formed insulated from each other at both ends of the element body. A metal coating is formed on the surface of the end electrode by electrolytic plating. The metal coating is made of tin, or the metal coating has a two-layer structure in which lead is the first layer and tin is the second layer. Further, the end electrode is formed by baking a metal containing 50% or more of palladium in an oxygen atmosphere, and then performing heat treatment in a reducing or neutral atmosphere.

【0013】[0013]

【作用】[Action]

上記構成のチップサーミスタによれば、基板実装前に、端部電極表面に電解メ ッキ法によって金属被膜が形成されるため、基板実装時の半田濡れ性が良くなる とともに、半田耐熱性が向上することによって基板実装時の伝熱による端部電極 の半田食われが減少し、基板実装後におけるチップサーミスタの抵抗変化率が低 減する。また端部電極が還元または中性雰囲気中で熱処理され形成されることに よっても、前記抵抗値の変化を抑えることになる。 According to the chip thermistor configured as described above, the metal coating is formed on the surface of the end electrode by the electrolytic plating method before the board is mounted, so that the solder wettability during board mounting is improved and the solder heat resistance is improved. This reduces solder erosion of the end electrodes due to heat transfer during board mounting, and reduces the resistance change rate of the chip thermistor after board mounting. Further, the change in the resistance value can be suppressed also by forming the end electrodes by heat treatment in a reducing or neutral atmosphere.

【0014】[0014]

【実施例】【Example】

以下に本考案の一実施例を図面を参照して詳述する。 An embodiment of the present invention will be described below in detail with reference to the drawings.

【0015】 図1は本考案の一実施例のチップサーミスタ7の断面図を示すものである。FIG. 1 is a sectional view of a chip thermistor 7 according to an embodiment of the present invention.

【0016】 酸化マンガンMnO,酸化コバルトCoO,酸化ニッケルNiO等を主成分と する焼結体から成る略方形状セラミック素体8の長手方向の両端部に、互いに絶 縁された第1の端部電極9aと第2の端部電極9bが設けられる。この端部電極 9a,9bは、例えば、パラジウムPdを50%以上含む、銀,パラジウム合金 (Ag/Pd)で形成される。また端部電極9a,9bの表面には電解メッキ法 によって鉛からなる第1の金属被膜10a,10bが形成され、さらにその表面 に電解メッキ法によって錫からなる第2の金属被膜11a,11bが形成される 。すなわち、端部電極9a,9bの表面には2層構造の金属被膜が形成されるこ ととなる。At both ends in the longitudinal direction of the substantially rectangular ceramic body 8 made of a sintered body containing manganese oxide MnO, cobalt oxide CoO, nickel oxide NiO, etc. as main components, first end portions insulated from each other are formed. An electrode 9a and a second end electrode 9b are provided. The end electrodes 9a and 9b are formed of, for example, silver or palladium alloy (Ag / Pd) containing 50% or more of palladium Pd. Further, first metal coatings 10a, 10b made of lead are formed on the surfaces of the end electrodes 9a, 9b by electrolytic plating, and second metal coatings 11a, 11b made of tin are formed on the surfaces by electrolytic plating. It is formed . That is, a metal coating having a two-layer structure is formed on the surfaces of the end electrodes 9a and 9b.

【0017】 その後、チップサーミスタ7は所望のプリント基板に端部電極9a,9bを電 解メッキ法によって形成された鉛から成る金属被膜10a,10b及び錫から成 る金属被膜11a,11bと共に、半田付けすることによって実装する。After that, the chip thermistor 7 is soldered together with the metal films 10a, 10b made of lead and the metal films 11a, 11b made of tin on the desired printed circuit board by forming the end electrodes 9a, 9b by the electrolytic plating method. It is implemented by attaching.

【0018】 次に、上記実施例におけるチップサーミスタ7の一製造方法について説明する 。Next, a method of manufacturing the chip thermistor 7 in the above embodiment will be described.

【0019】 まず、略方形状セラミック素体8の両端部に、例えば、パラジウムPdを50 %以上含む、銀,パラジウム合金(Ag/Pd)のペーストを塗布し、それを酸 素雰囲気中で焼き付け処理し、その焼き付け電極を還元または中性雰囲気中で熱 処理を行う。そして例えばN2 等の中性雰囲気中で基板装着温度と同じ温度、す なわち、180 乃至 200℃で5分間、加熱処理し、端部電極9a,9bが形成され る。その後、上述したように、このチップサーミスタ素子の端部電極9a,9b の表面に、常温にて電解メッキ法によって鉛メッキを施し、第1の金属被膜10 a,10bを形成する。次に、その表面に、同様にして錫メッキを施し、第2の 金属被膜11a,11bを形成する。First, for example, a paste of silver and a palladium alloy (Ag / Pd) containing 50% or more of palladium Pd is applied to both ends of the substantially rectangular ceramic body 8, and the paste is baked in an oxygen atmosphere. The baked electrode is subjected to heat treatment in a reducing or neutral atmosphere. Then, the end electrodes 9a and 9b are formed by heat treatment in a neutral atmosphere such as N 2 at the same temperature as the substrate mounting temperature, that is, at 180 to 200 ° C. for 5 minutes. After that, as described above, the surfaces of the end electrodes 9a, 9b of the chip thermistor element are subjected to lead plating by electrolytic plating at room temperature to form the first metal coatings 10a, 10b. Next, tin plating is similarly applied to the surface to form second metal coatings 11a and 11b.

【0020】 そして最後に、洗浄等を経てチップサーミスタ7が完成する。Finally, the chip thermistor 7 is completed through cleaning and the like.

【0021】 このように、中性雰囲気中で加熱処理された略方形状セラミック素体7及び端 部電極9a,9bは、初期エージングされることになるので、基板実装後の半田 付けの伝熱による平板状セラミック素体11自体の抵抗値の変化はほとんど起こ らない。また端部電極9a,9b表面に電解メッキ処理を施すことにより金属被 膜10a,11a,10b,11bが形成されるため、半田濡れ性が良くなり、 さらに前記電解メッキ処理が常温で行われるため耐熱性が向上し、端部電極9a ,9bの半田食われによる抵抗変化率も減少する。As described above, since the substantially rectangular ceramic body 7 and the end electrodes 9a and 9b which are heat-treated in the neutral atmosphere are initially aged, the heat transfer for soldering after mounting on the board is performed. The change in the resistance value of the flat plate-shaped ceramic body 11 itself hardly occurs. Further, since the metal coatings 10a, 11a, 10b, 11b are formed by subjecting the surfaces of the end electrodes 9a, 9b to electrolytic plating, the solder wettability is improved and the electrolytic plating is performed at room temperature. The heat resistance is improved, and the resistance change rate due to the solder erosion of the end electrodes 9a 1 and 9b is also reduced.

【0022】 したがって、プリント基板実装によるチップサーミスタの抵抗変化率は大幅に 低下し、そのため抵抗値のバラツキも少なくなる。Therefore, the resistance change rate of the chip thermistor due to the mounting on the printed circuit board is significantly reduced, so that the variation in the resistance value is reduced.

【0023】 このように製造されたチップサーミスタ7について、本考案者らが行った実験 により得られた結果を図3に示す。この図は半田の溶融温度に対する基板実装後 の抵抗変化率を示す図であり、従来例と本実施例におけるチップサーミスタ1, 7について比較したものである。図3でわかるように、半田温度の上昇に伴い基 板実装後の抵抗変化率も上昇するが、同じ半田温度の場合、本実施例の方が従来 例に比べ、かなり改善されていることが分かる。FIG. 3 shows a result obtained by an experiment conducted by the present inventors on the chip thermistor 7 manufactured as described above. This figure is a diagram showing the rate of resistance change after mounting on the substrate with respect to the melting temperature of the solder, and is a comparison between the chip thermistors 1 and 7 in the conventional example and the present example. As can be seen in FIG. 3, the rate of change in resistance after mounting the substrate also rises as the solder temperature rises, but at the same solder temperature, this example is considerably improved compared to the conventional example. I understand.

【0024】 またチップサーミスタ7は、プリント基板にチップサーミスタ7を取り付け、 これを半田浴中に浸せきさせることにより実装されるが、図2は、本実施例のチ ップサーミスタの耐熱性を示し、端部電極9a,9bの素材であるAg/Pdの 組成率を変えた場合の、その浸せき時間と抵抗変化率の関係を示す。この場合、 Agに対し、Pdの量が多いほど、チップサーミスタ7の抵抗変化率は低下し、 Pdのみを素材とした場合(Pd=100%)が最良ではあるが、上述したよう にPdはコストがかかるため、本実施例においては、Pdは50%以上含むこと とした。The chip thermistor 7 is mounted by mounting the chip thermistor 7 on a printed circuit board and immersing it in a solder bath. FIG. 2 shows the heat resistance of the chip thermistor of this embodiment. The relationship between the immersion time and the resistance change rate when the composition ratio of Ag / Pd, which is the material of the partial electrodes 9a and 9b, is changed is shown. In this case, the greater the amount of Pd with respect to Ag, the lower the resistance change rate of the chip thermistor 7, and it is best if only Pd is used as the material (Pd = 100%). Because of the high cost, in this embodiment, Pd is included at 50% or more.

【0025】 本実施例では、金属被膜を鉛メッキと錫メッキの2層で形成したが、錫メッキ のみで形成しても同様の効果が得られる。In the present embodiment, the metal coating is formed by two layers of lead plating and tin plating, but the same effect can be obtained by forming only the tin plating.

【0026】 また本実施例においてはセラミック素体の形状を略方形状としたが、板状又は 柱状,円筒状としても同様の効果が得られる。Further, although the ceramic body has a substantially rectangular shape in the present embodiment, the same effect can be obtained by using a plate shape, a columnar shape, or a cylindrical shape.

【0027】 尚、本考案は上記実施例に限定されず、その要旨を変更しない範囲内で種々に 変形実施できる。The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

【0028】[0028]

【考案の効果】[Effect of the device]

以上詳述した本考案によれば、端部電極の形成されたチップサーミスタを中性 雰囲気中で加熱処理した後、端部電極表面に電解メッキ法により常温で金属被膜 が形成されるので、実装時の半田濡れ性が良くなり、さらに、半田耐熱性が向上 するため端部電極の半田食われが減少されるとともに、基板実装後におけるチッ プサーミスタの抵抗変化率及び抵抗の経時変化を大幅に低減することのできる安 定度の高いチップサーミスタを提供することができる。 According to the present invention described in detail above, after the chip thermistor having the end electrodes formed thereon is heat-treated in a neutral atmosphere, a metal film is formed on the end electrode surfaces by electrolytic plating at room temperature. The solder wettability at the time is improved, and the solder heat resistance is also improved, so that the solder erosion of the end electrodes is reduced, and the rate of resistance change of the chip thermistor and the change with time of the resistance after mounting on the board are significantly reduced. It is possible to provide a highly stable chip thermistor that can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の一実施例のチップサーミスタの断面図FIG. 1 is a sectional view of a chip thermistor according to an embodiment of the present invention.

【図2】本考案の一実施例のチップサーミスタの耐熱性
を示す図
FIG. 2 is a diagram showing heat resistance of a chip thermistor according to an embodiment of the present invention.

【図3】本考案の一実施例の効果を示す図FIG. 3 is a diagram showing an effect of one embodiment of the present invention.

【図4】従来のチップサーミスタの断面図FIG. 4 is a sectional view of a conventional chip thermistor.

【図5】従来のチップサーミスタの実装工程図[FIG. 5] Mounting process diagram of a conventional chip thermistor

【符号の説明】[Explanation of symbols]

7 チップサーミスタ 8 略方形状セラミック素体 9a,9b 端部電極 10a,10b 鉛から成る第1の金属被膜 11a,11b 錫から成る第2の金属被膜 7 Chip Thermistor 8 Substantially Rectangular Ceramic Element 9a, 9b End Electrode 10a, 10b First Metal Film 11a, 11b Lead Metal Second Metal Film 11a, 11b

Claims (6)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 板状又は略方形状,柱状,円筒状のセラ
ミック素体と、この素体の両端に互いに絶縁され形成さ
れた端部電極を有するチップサーミスタにおいて、前記
端部電極の表面に金属被膜を電解メッキ法により形成し
たことを特徴とするチップサーミスタ。
1. A chip thermistor having a plate-shaped or substantially rectangular, columnar, or cylindrical ceramic body and end electrodes insulated from each other at both ends of the body, wherein a surface of the end electrode is provided. A chip thermistor having a metal coating formed by an electrolytic plating method.
【請求項2】 前記金属被膜が錫からなる請求項1記載
のチップサーミスタ。
2. The chip thermistor according to claim 1, wherein the metal coating is made of tin.
【請求項3】 前記金属被膜が鉛を第1層とし、錫を第
2層とする2層構造からなる請求項1記載のサーミス
タ。
3. The thermistor according to claim 1, wherein the metal coating has a two-layer structure in which lead is the first layer and tin is the second layer.
【請求項4】 前記端部電極は、パラジウム50%以上
を含む金属で電極層が形成されている請求項1記載のチ
ップサーミスタ。
4. The chip thermistor according to claim 1, wherein the end electrode has an electrode layer formed of a metal containing 50% or more of palladium.
【請求項5】 前記端部電極は、酸素雰囲気中で焼き付
け処理した焼き付け電極とされている請求項1記載のチ
ップサーミスタ。
5. The chip thermistor according to claim 1, wherein the end electrode is a baked electrode baked in an oxygen atmosphere.
【請求項6】 前記焼き付け電極は、還元または中性雰
囲気中で熱処理形成されている請求項5記載のチップサ
ーミスタ。
6. The chip thermistor according to claim 5, wherein the baked electrode is formed by heat treatment in a reducing or neutral atmosphere.
JP1991087693U 1991-10-25 1991-10-25 Chip thermistor Expired - Lifetime JP2569936Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991087693U JP2569936Y2 (en) 1991-10-25 1991-10-25 Chip thermistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991087693U JP2569936Y2 (en) 1991-10-25 1991-10-25 Chip thermistor

Publications (2)

Publication Number Publication Date
JPH0538802U true JPH0538802U (en) 1993-05-25
JP2569936Y2 JP2569936Y2 (en) 1998-04-28

Family

ID=13922010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991087693U Expired - Lifetime JP2569936Y2 (en) 1991-10-25 1991-10-25 Chip thermistor

Country Status (1)

Country Link
JP (1) JP2569936Y2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136302U (en) * 1987-02-27 1988-09-07
JPH02189903A (en) * 1989-01-18 1990-07-25 Murata Mfg Co Ltd Laminated varistor
JPH02296312A (en) * 1989-05-10 1990-12-06 Sumitomo Metal Ind Ltd Electronic component and manufacture thereof
JPH03250603A (en) * 1989-12-28 1991-11-08 Mitsubishi Materials Corp Thermistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136302U (en) * 1987-02-27 1988-09-07
JPH02189903A (en) * 1989-01-18 1990-07-25 Murata Mfg Co Ltd Laminated varistor
JPH02296312A (en) * 1989-05-10 1990-12-06 Sumitomo Metal Ind Ltd Electronic component and manufacture thereof
JPH03250603A (en) * 1989-12-28 1991-11-08 Mitsubishi Materials Corp Thermistor

Also Published As

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JP2569936Y2 (en) 1998-04-28

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