JPH0541382A - Lateral transistor - Google Patents

Abstract

PURPOSE:To enhance the current capacity and the current-amplification factor of a lateral PNP transistor by a method wherein an emitter-region for the lateral PNP transistor is formed by a p<+> type upper and lower isolation diffusion process. CONSTITUTION:A P<+> type emitter region for a lateral PNP transistor is formed of a rear-surface P type emitter region 9 and a surface P<+> type emitter region 10. In a rear-surface P<+> type isolation diffusion process and a surface P<+> type isolation diffusion process, they are formed simultaneously with a rear-surface P<+> type isolation diffusion region 3 and a surface P<+> isolation diffusion region 5. They are formed simultaneously by the base P<+> type diffusion process of an NPN transistor. A P<+> type collector region 7 and an N<+> type base contact region 8 for the lateral PNP transistor are framed simultaneously in an emitter N<+> type diffusion process. Thereby, the lateral PNP transistor having a large effective emitter area is formed. Since the number of holes which can contribute to a collector current is increased at this time, the current capacity of the PNP transistor is increased and its current-amplification factor is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral transistor in a semiconductor device having a vertical diffusion isolation structure.

[0002]

2. Description of the Related Art FIG. 2 shows a schematic sectional view of a conventional lateral PNP transistor. In the figure, 1 is a P type silicon substrate, 2 is an N ⁺ type buried region, 3 is a lower surface P ⁺ type isolation diffusion region, 4 is an N type epitaxial region, 5 is an upper surface P ^+.
This is a mold separation diffusion region. Then, 6 and 7 are simultaneously formed in the base P ⁺ type diffusion process of the NPN transistor,
Each of the lateral PNP transistors is a P ⁺ type emitter region and a P ⁺ type collector region. Reference numeral 8 is an N ⁺ type base contact region of the lateral PNP transistor transistor, which is simultaneously formed in the emitter N ⁺ type diffusion process of the NPN transistor. With the above structure, a lateral PNP transistor is formed, and holes injected from the emitter are laterally diffused and reach the collector to operate as a lateral PNP transistor.

[0003]

By the way, in the lateral PNP transistor according to the prior art as described above, the depth of the emitter region and the collector region is shallow and the effective emitter area and the effective collector area are small, so that the current capacity is small. A large decrease in Hfe (current amplification factor) at high current. As a result, Hfe is low because the number of holes that contribute effectively to the collector current is small. There was a problem.

The present invention solves the above problems.

[0005]

In order to solve the above problems, in the present invention, the emitter region of the lateral PNP transistor is formed by P ⁺ -type vertical separation diffusion.

[0006]

In the lateral PNP transistor of the present invention, since the P ⁺ -type upper and lower separation diffusion is used in the emitter region, the effective emitter area becomes large and the number of holes contributing to the collector current increases, so that the current capacity is increased. It becomes large and Hfe (current amplification factor) is improved.

[0007]

EXAMPLES The present invention will be described in detail below based on examples.

A schematic sectional view of a lateral PNP transistor according to the present invention is shown in FIG. In the figure, 1 is a P type silicon substrate, 2 is an N ⁺ type buried region, 3 is a lower surface P ⁺
Type isolation diffusion regions, 4 is an N type epitaxial region, and 5 is an upper surface P ⁺ type isolation diffusion region. Then, 9 and 10, the lower surface P ⁺ -type emitter region constituting a P ⁺ -type emitter region of the lateral PNP transistor, a top P ⁺ -type emitter region, respectively the lower surface P ⁺ -type isolation region diffusion process, the upper surface P ⁺ type isolation In the diffusion process, the lower surface P ⁺ type isolation diffusion region and the upper surface P ⁺ type isolation diffusion region are formed at the same time. Also, 7 is
Reference numeral 8 denotes a P ⁺ -type collector region of the lateral PNP transistor, which is simultaneously formed in the base P ⁺ -type diffusion process of the NPN transistor, and 8 is an N of the lateral PNP transistor.
^{In the +} type base contact region, it is simultaneously formed in the emitter N ⁺ type diffusion process of the NPN transistor.

In this way, the conventional lateral P
A lateral PNP transistor having a sufficiently large effective emitter area is formed as compared with the NP transistor. At this time, since the number of holes that can contribute to the collector current increases, the current capacity of the PNP transistor increases, and Hf
e is improved, and the decrease in Hfe at high current is reduced.

[0010]

As described in detail above, according to the present invention, in a semiconductor device having a vertical diffusion isolation structure,
The current capacity and Hfe (current amplification factor) of the lateral PNP transistor can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a lateral PNP transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view of a conventional lateral PNP transistor.

[Explanation of symbols]

1 P-type silicon substrate 2 N ⁺ type buried region 3 Lower surface P ⁺ type isolation diffusion region 4 N type epitaxial region 5 Upper surface P ⁺ type isolation diffusion region 7 Lateral PNP transistor P ⁺ type collector region 8 Lateral PNP transistor N ⁺ type top P ⁺ -type emitter region constituting a P ⁺ -type emitter region of the lower surface P ⁺ -type emitter region 10 lateral PNP transistor constituting the P ⁺ -type emitter region of the base contact region 9 lateral PNP transistor

Claims (1)

[Claims] 1. A lateral transistor in a semiconductor device having a vertical diffusion isolation structure, wherein an emitter region thereof is formed by vertical diffusion isolation.