JPH0542017B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a data processing device, and particularly to a modulo W circuit used for checking an arithmetic circuit or the like. [Prior Art] A modulo W circuit is one of the check circuits that has been frequently used in the past, mainly as a check circuit for arithmetic circuits and the like. By the way, Modulus W
as W=2 ^w −1 (e.g. 3, 7, 15,…)
is often used. The reason for this is Mojiyuro W
This is because the value of can be expressed in w bits, so it can be realized at a lower cost than other moduli (Hereafter, we will consider W = 2 ² - 1 = 3 as a representative of W = 2 ^w - 1. w is 2 (integer greater than or equal to). For the three values of modulus 3, 0, 1, and 2, there are four values that can be expressed with 2-bit data: [0, 0], [0, 1],
Define three values among [1, 0] and [1, 1]. For example, 0 corresponds to [0, 0], 1 corresponds to [0, 1], and 2 corresponds to [1, 0]. FIG. 10 shows an example of a conventional three-modulo circuit. Referring to FIG. 10, arithmetic device 9000:
When the first input data and the second input data are input, the respective first input operand registers 900
1. Store in the second input operand register 9002, execute the calculation between the first input operand and the second input operand by the calculation circuit 9011, store the result in the calculation result register 9003, and then output do. The modulo 3 circuit in this arithmetic unit 9000 includes a modulo 3 expected value generation circuit 9012, a modulo 3 expected value register 9004, a modulo 3 coincidence check 9013, and an error display flag 900.
It consists of 5. When a first input operand and a second input operand are input from a first input operand register 9001 and a second input operand register 9002 through data paths 901 and 902, respectively, the modulo-3 expected value generation circuit 9012 generates an arithmetic operation circuit 9012.
Execute the modulo 3 operation corresponding to 11, generate the expected value of modulo 3 of the calculation result, and send it to the data path 9.
Modulo 3 expected value register 9004 through 12
Output to. The modulo 3 expected value register 9004 inputs the modulo 3 expected value which is the output of the modulo 3 expected value generation circuit 9012 through the data path 912 and stores it.
Output to match check circuit 9013. The modulo 3 match check circuit 9013 inputs the calculation result from the calculation result register 9003 through the data path 903, and also inputs the expected modulo 3 value from the modulo 3 expected value register 9004 through the data path 904, and generates the calculation result modulo 3. , checks whether or not this value matches the modulo 3 expected value. If they do not match, an error report is output to the error display flag 9005 through the data path 913. Error display flag (hereinafter referred to as EIF) 9005
When the error report is input through the data path 913, it is stored, and the value is held until the release signal is input thereafter, and the error report is output through the data path 905. Through the above-described operation, a failure in the arithmetic unit 9000 is detected and reported, but the check is generally executed in more detail than that described in FIG. 10 in the modulo 3 check circuit. In other words, a similar consistency check is performed not only on the final result of the arithmetic circuit, but also on intermediate results. In this case, the modulo 3 expected value of the intermediate result is data path 92
1 and is input to the arithmetic circuit. FIG. 11 is a part of an arithmetic circuit in an arithmetic device, and is a diagram showing an example of a case where a modulo 3 check is executed on an intermediate result thereof. Referring to FIG. 11, an arithmetic circuit 8000 inputs two binary data X, Y and their respective modulo ternary values A, B, and calculates an arithmetic result Z between X and Y.
, the modulo 3 value C of Z, and an error report E based on the result of the modulo 3 check. First input register 801 and second input register 8
02 means that after inputting and storing X and Y, X and Y are input through data paths 81 and 82, respectively.
Y is output and is used as one input of an arithmetic circuit 811, a first input modulo 3 generation circuit 812, and a second input modulo 3 generation circuit 813 as shown. The arithmetic circuit 811 receives X through the data path 81.
When Y is input through the data path 82, an operation is performed between X and Y, and the operation result Z is passed through the data path 91 and output to the operation result output register 803.
Output to. Operation result output register 803 is connected to data path 91
After inputting and storing Z through the data path 83
Outputs Z through. Z becomes the output of the calculation result 8000 and one input of the calculation result modulo 3 generation circuit 816. When X is input through the data path 81, the first input modulo 3 generation circuit 812 generates the modulo 3
A value is generated and output through data path 92 to match circuit 814 and first modulo 3 holding register 8.
04 input. When Y is input through the data path 82, the second input modulo 3 generation circuit 813 generates the modulo 3
A value is generated and output through data path 93 to match circuit 815 and second modulo 3 holding register 80.
5 input. The first modulo 3 holding register 804 and the second modulo 3 holding register 805 input and store the modulo 3 values of X and Y through data paths 92 and 93, respectively.
5 to the modulo 3 arithmetic circuit 817. The modulo 3 arithmetic circuit 817 inputs the modulo 3 values of X through the data path 84 and the modulo 3 values of Y through the data path 85.
A modulo 3 operation corresponding to the operation is executed to generate a modulo 3 expected value of the operation result Z, output through the data path 97, and used as one input of the matching circuit 818. When the arithmetic circuit modulo 3 generation circuit 816 inputs the calculation result Z through the data path 83, it generates a modulo 3 value of Z and outputs it through the data path 96 to the coincidence circuit 818 and the modulo 3 output register 806.
Use as input. Modulo 3 output register 806 is data path 9
The modulo ternary value of Z is input through 6, and the stored modulo ternary value C of Z is outputted through the rear data path 86. C is used as one output of the arithmetic circuit 8000, and is used as an input to a modulo 3 check circuit in the subsequent stage. Matching circuit 814, through data path 92,
Input the modulo 3 value of X and the expected modulo 3 value A of X, and check whether the modulo 3 value of X and the expected value A match.
If they do not match, report an error to data path 9.
4 to the EIF (error display flag) 808. The matching circuit 815 compares the modulo three values of Y input from the data path 93 with its expected value B, and sends the result through the data path 95 to the EIF 80.
Output to 9. Furthermore, the matching circuit 818 receives the modulo 3 values of Z input from the data path 96 and the data path 97.
The EIF 807 outputs the result through the data path 98. When EIFs 807, 808, and 809 input an error report through data paths 98, 94, and 95, respectively, they store it and hold the value until a release signal is input. Output to. When the OR circuit 810 receives an error report from any of the EIFs 807, 808, and 809, the OR circuit 810 sends the error report E indicating the occurrence of a failure to the arithmetic circuit 80.
Output as 1 output of 00. [Problems to be solved by the invention] Conventional modulus 3 shown in FIGS. 10 and 11
In the circuit, Modulo 3 is used to convert the numerical value indicated by the data into 3
The remainder after dividing by. ”For the numerical reason,
The value of modulo 3 is 3, that is, binary data [1,
1] is not taken into account, but since the modulo 3 circuit originally used in data processing equipment is used as a check circuit to detect circuit failure, the value of modulo 3 may change due to a failure. ,
1] should also be considered. For example, in FIG. 11, the first input modulus 3
When binary data [1, 1] is output on the data path 92 due to a failure in the generation circuit 812,
In the conventional modulo 3 circuit, the output for the input [1, 1] is undefined, and the outputs of the matching circuit 814, modulo 3 arithmetic circuit 817, matching circuit 818, etc. are as follows.
It has no logical meaning and depends on its circuit configuration. Therefore, if the [1, 1] pattern occurs due to a failure in the modulo 3 circuit itself, it is difficult to detect the failure, and furthermore, a failure in the arithmetic circuit may cause the calculation result to be incorrect. Even in this case, if the value of modulo 3 is the same as the output for [1, 1] above, the failure will not be detected, and the detection rate of the check circuit will not only drop significantly, but also In the check circuit, when the error display flag lights up, it becomes a factor that causes an error in pointing out the failure location. In addition, when a part of the arithmetic circuit is realized by LSI etc., evaluation for failure detection of the LSI etc.
Normally, logic gates and logic patterns in LSIs are verified using outputs and flip-flop values in response to inputs of certain test patterns.
When a modulo-3 circuit is included in an LSI, the detection rate will not improve unless the case [1, 1] is included as a test input, so the arithmetic circuit as a whole is considered to be completely meaningless logically. 1, 1] is also required, and the logic completely depends on the circuit configuration as described above, resulting in a very complex description that is difficult to understand. On the other hand, in the check method using modulo 3, as mentioned above, the expected value of modulo 3 and the value of modulo 3 generated from the actual calculation result are checked for agreement, so in order to improve the detection rate, calculation It is necessary to generate expected values for each part of the circuit and set error flags for each part, which increases the amount of hardware significantly, and when multiple error flags light up, it is difficult to determine whether the cause is due to the same failure. It is difficult to determine whether or not. Generally, in conventional modulo W circuits, binary values [1,...,1] are not considered, so
It is difficult to improve the failure detection rate and dividing power as a modular W circuit, and furthermore, when verifying check circuits associated with recent LSI technology, it is meaningless [1,...,1]
The disadvantage is that the logical description of the method is an impediment to improving design efficiency. [Means for solving the problem] In the present invention, n (n is an integer of 2 or more) w (w
is an integer greater than or equal to 2) bit data A ₁ = [a ₁₁ ,...,
a _1w ], A ₂ = [a ₂₁ ,…, a _2w ]…, A _o = [a _o1 ,…,
a _ow ] is the input, and the n inputs A ₁ , A ₂ , ...,
The result of the modulo W operation between A _o is D = [d ₁ , ...,
d _w ], when one or more of the inputs A ₁ , A ₂ , ..., A _o is [1, ..., 1], C = [1,
..., 1], and in other cases C=[d ₁ , ..., d _w ]. A modulo W calculation circuit outputs w-bit data C = [c ₁ , ..., c _w ], and N-bit data Z. Among them, M-bit data Z ₁ is input, and the data Z ₁
A first modulo W generation circuit that generates and outputs a modulo W value E = [e ₁ , ..., e _w ], and N-M bit data Z ₂ of the data Z excluding the data Z ₁ . As input, the modulus W value F= of the data Z ₂
A second modulus W that generates and outputs [f ₁ ,..., f _w ]
Output CK of the generation circuit and the modulo W calculation circuit
[c ₁ , ..., c _w ] and the output F = [f ₁ , ..., f _w ] of the second modulo W generation circuit are input, and the modulus W of the difference C - F between the inputs C and F is The value is G=[g ₁ ,
..., g _w ], when one or more of the inputs C and F are [1, ..., 1], H = [1, ...,
1] In other cases, H = [g ₁ , ..., g _w ].
A modulo W subtraction circuit that outputs bit data H=[h ₁ ,..., h _w ], an output H=[h ₁ ,..., h _w ] of the modulo W subtraction circuit, and an output of the first modulo W generation circuit. The output E = [e ₁ , ..., e _w ] is input, and H
= E, then K = [e ₁ , ..., e _w ], H≠E or H, and when one or more of E is [1, ..., 1], K = [1, ..., 1] w bit data K=
a modulo W matching circuit that outputs [k ₁ , ..., k _w ], and the n input data A ₁ , A ₂ , ..., A _o
The result G obtained by subtracting the modulus W value F from the calculation result D between and the modulus W value E matches,
And when there is no value of [1,...,1] in the input data, K=E=[e ₁ ,..., e _w ], otherwise K=[1,...,1] w bit data K
A modulo W circuit is obtained, which is characterized in that it outputs =[k ₁ , . . . , k _w ]. In the present invention, furthermore, on the transmission path of the modulo W value, the modulo W value L=[l ₁ , ..., l _w ],
Strobe signal is input, output P=[1,...,
1], when a strobe signal is input, P=
[1,...,1], and when the strobe signal is input in other states, P=[l ₁ ,..., l _w ] becomes W bit data P=[p ₁ ,..., p _w ], and the input L= [l ₁ ,
..., l _w ] is provided with _a modulo W register that outputs the modulo W value after _one strobe _of The result of subtracting F is G
and the modulo W value E match, and when there is no value of [1,...,1] in the input data, w bit data K=E=[e ₁ ,..., e _w ]. At other times, K=[1,...,1] is held and outputted, and the transmission path of [1,...,1] is detected based on the value held in the modulo W register. A modulo W circuit is obtained which is characterized by the following. Further, in the present invention, the input L=[1,...,1] or P=[1,...,1] or P=[1,
..., 1], when a strobe signal is input, q
= 1, and when a strobe signal is input in any other state, a function is added to output 1-bit data q such that q = 0, and the n input data A ₁ , A ₂ , . . .
When the result G obtained by subtracting the modulo W value F from the calculation result D between A _{and o} matches the modulo W value E, and there is no value of [1,...,1] in the input data. w bit data K=E=[e ₁ ,...,
e _w ], otherwise K=[1,...,1]
is held, and outputs an error report using the w bit data KE and the 1 bit data q, and also outputs [1,
. . , 1] is obtained. [Example] Next, the present invention will be described with reference to the drawings.
Here, a modulo 3 circuit will be described as an example of a modulo W circuit. FIG. 1 is a block diagram showing a first embodiment of the present invention. Referring to FIG. 1, the modulus 3 circuit 1000
inputs N-bit data Z and two 2-bit data A and B, and inputs M of the N bits of Z.
Outputs modulo 3-value K of bit (M<N) data _Z1 . When the first modulo 3 generation circuit 101 receives the M-bit data Z ₁ of the N-bit input data Z, it generates the modulo 3 value E=[e ₁ , e ₂ ] of Z ₁ , and the data path 11 output through Modulo 3
It is assumed to be one input of the matching circuit 105. When the second modulo 3 generation circuit 102 receives N−M bit data Z ₂ obtained by excluding data Z ₁ from the N bit input data Z, the modulo 3 value of Z ₂ F=[f ₁ , f ₂ ] is generated and output through the data path 12, and is used as one input of the modulo-3 subtraction circuit 104. The modulo 3 arithmetic circuit 103 inputs two pieces of 2-bit data A and B, and modulo 3 is input between A and B.
Execute the calculation and set the resulting modulo 3 value as D=
If [d ₁ , d ₂ ], then C=D=[d ₁ , d ₂ ]2
Output bit data C=[c ₁ , c ₂ ]. However, when one or more of inputs A and B are [1, 1], C=[1, 1] is output. Output C passes through data path 13 to one of modulo-3 subtraction circuits 104.
It becomes input. The modulo 3 subtraction circuit 104 is connected to the data path 12
When the modulo 3 value F is input through the data path 13 and the modulo 3 value C is input through the data path 13, a modulo 3 subtraction of C-F is executed, and the resulting modulo 3 value is G = [g ₁ , g ₂ ], then H Outputs 2-bit data H=[h ₁ , h ₂ ] such that =G=[g ₁ , g ₂ ]. However, when one or more of inputs C and F is [1, 1], H=[1, 1] is output. The output H passes through the data path 14 and becomes one input of the modulo 3 matching circuit 105. When the modulo 3-value matching circuit 105 receives the modulo 3-value E through the data path 11 and the modulo 3-value H through the data path 14, it executes a match check between E and H, and when H=E, K=E=[e ₁ ,
e ₂ ], 2-bit data K is output. However, when H≠E or one or more of the inputs H and E are [1, 1], K=[1, 1] is output. Output K passes through data path 15 to modulo 3 circuit 1
The output will be 000. In the modulo 3 circuit 1000, for example, the second
When [1, 1] occurs as a modulo 3 value on the data path 12 due to a failure in the modulo 3 circuit 102, this value of [1, 1] passes through the modulo 3 subtraction circuit 104 and then through the data path 14. After passing through the modulo 3 matching circuit 105 and the data path 15, the modulo 3 value K=[1, 1] is output. Also, as a second example, when input A = [1, 1], the value of [1, 1] is the modulo 3 arithmetic circuit 10
3, passes through the data path 13, passes through the modulo 3 subtraction circuit 104, passes through the data path 14, passes through the modulo 3 matching circuit 105, and passes through the data path 15, and outputs the modulo 3 value K=[1, 1]. . Furthermore, as a third example, the modulus 3 circuit 100
0 as the upper M of the sum Z of N-bit binary numbers X and Y
It is used as a check circuit for an adder circuit that obtains bit data _Z1 , and if the modulo 3 values of X and Y are A and B, then the modulo 3 arithmetic circuit 103
performs modulo 3 addition between A and B, and A
If the modulus 3 values of □+B are D=[d ₁ , d ₂ ], then
2-bit data C= where C=D=[d ₁ , d ₂ ]
[c ₁ , c ₂ ] are output through the data path 13 and are used as one input of the modulo-3 subtraction circuit. On the other hand, among the N-bit data Z resulting from the addition, the lower N-M bit data _Z2 is input to the second modulo 3 generation circuit 102, and the modulo 3 value F=[f ₁ , f ₂ ] of Z ₂ is It passes through the data path 12 and becomes one input of the modulo-3 subtraction circuit. In the modulo 3 subtraction circuit, if the modulo 3 value of C-F is G = [g ₁ , g ₂ ], then H = G =
The 2-bit data H of [g ₁ , g ₂ ] is output through the data path 14 and is used as one input of the modulo 3 matching circuit. The data of the upper M bits of the N-bit data Z of the addition result of the first modulo 3 generation circuit
Z ₁ is input, a modulo 3 value E of Z ₁ is generated, outputted through the data path 11, and modulo 3 matching circuit 1
1 input of 05. Here, the modulus 3 value of Z =
The equation in the modulo 3 operation holds true: modulo 3 values of Z ₁ + modulo 3 values of Z ₂ = modulo 3 values of X + modulo 3 values of Y, so □+ is modulo 3
If addition and □- are modulo 3 subtraction, then the modulo 3 value of _Z1 should be E=A□+B□-F=C□-F=H. Therefore, the output of the modulo 3 coincidence circuit K=E=
[e ₁ , e ₂ ]. However, due to a failure in the X and Y adder circuit or a failure in the modulo 3 circuit itself, H≠
When one or more of E, H, and E becomes [1, 1], the output K becomes [1, 1]. As described above, when there is a failure in the modulo 3 circuit 1000, an abnormality in the input modulo 3 values, or a failure in the arithmetic circuit to be checked, the output modulo 3 value K is an incorrect value as the value of the modulo 3. [1, 1], and from the output K of the modulo 3 circuit 1000, the fact that a failure has occurred in the previous stage can be transmitted to the subsequent modulo 3 circuit. FIG. 2 shows a second embodiment of the present invention, and is a block diagram of an arithmetic circuit using the modulo 3 circuit of the present invention as a check circuit. Referring to FIG. 2, an arithmetic circuit 2000 inputs two binary data X, Y and their respective modulo ternary values A, B, and calculates an arithmetic result Z between X and Y.
One part of the data Z ₁ and the modulus ternary C of Z ₁
Outputs . The first input register 701 and the second input register 702 input and store X and Y, respectively, and then pass the X and Y through data paths 71 and 72, respectively.
Y is outputted and is used as one input of an arithmetic circuit 601, a first input modulo 3 generation circuit 602, and a second input modulo 3 circuit 603 as shown in the figure. The arithmetic circuit 601 connects
When inputting Y through the data path 72,
and Y, and pass the operation result Z through the data path 61 to the operation result output register 70.
Output to 3. The calculation result output register 703 is connected to the data path 6
After inputting and storing Z through data path 731 and storing it, part of the data Z ₁ of Z is output through data path 731 and the remaining data Z ₂ is output through data path 732 . Z ₁
becomes the output of the arithmetic circuit 2000 and becomes one input of the first result modulo 3 generation circuit 201, and Z ₂
becomes one input of the second result modulo 3 generation circuit 202. When the first input modulo 3 generation circuit 602 receives X through the data path 71, it generates its modulo 3 value and outputs it through the data path 62,
The first input is assumed to be one input of the modulo 3 matching circuit 604. When the second input modulo 3 generation circuit 603 receives Y through the data path 72, it generates its modulo 3 value and outputs it through the data path 63,
The second input is set as one input of the modulo 3 matching circuit 605. When the first result modulo 3 generation circuit 201 receives Z ₁ through the data path 731, it generates its modulo 3 value, outputs it through the data path 21, and uses it as one input of the first result modulo 3 matching circuit 204. When the second result modulo 3 generation circuit 202 receives Z ₂ through the data path 732, it generates its modulo 3 value and outputs it through the data path 22,
It is assumed to be one input of the modulo 3 subtraction circuit 203. The first input modulo 3 matching circuit 604 inputs the modulo 3 value of X through the data path 62 and also inputs the modulo 3 expected value A of X, and checks whether the modulo 3 value of X and this expected value A match. Check if it is not, and if it matches, modulus 3 of X
Outputs the value as is, and when either the modulo 3 values of X and the expected value A are [1, 1], or when the modulo 3 values of X and the expected value A do not match, it is [1, 1]. The output modulo 3 value is inputted to the first modulo 3 holding register 704 through the data path 64. The second input modulo 3 matching circuit 605 inputs the modulo 3 value of Y through the data path 63 and also inputs the expected modulo 3 value B of Y, and executes a matching check in the same manner as the first input modulo 3 matching circuit 604. , modulo ternary value of Y or [1, 1]
is output through the data path 65 and becomes one input of the second modulo 3 holding register 705. The first modulo 3 holding register 704 inputs the output modulo 3 value of the first input modulo 3 matching circuit 604 through the data path 64, stores it in accordance with the strobe signal, outputs it through the data path 74, and outputs it through the data path 74 to the modulo 3 arithmetic circuit. 607 is assumed to be one input. However, if the value held in this register before inputting the strobe signal is [1, 1], [1, 1] will be retained even after inputting the strobe signal, and regardless of the strobe signal, the output modulo 3 value of this register will be Keep [1, 1] and do not change. The second modulo 3 holding register 705 is connected to the second input modulo 3 matching circuit 6 through the data path 65.
After inputting the output modulo 3 values of 05 and storing them using the strobe signal, they are outputted through the data path 75 and become one input of the modulo 3 arithmetic circuit 607. However, if the value held in this register before inputting the strobe signal is [1, 1], the first modulus 3
Similar to the holding register 704, [1, 1] is held and the output does not change. The modulo 3 arithmetic circuit 607 is a first modulo 3
The output modulo 3 values of the holding register 704 are input through the data path 74, and the output modulo 3 values of the second modulo 3 holding register 705 are input through the data path 75, so that any of the modulo 3 values is [1, 1]. In this case, [1, 1] is output as is, and when both are not [1, 1], a modulo 3 operation corresponding to the arithmetic circuit 601 is executed between the two modulo 3 values, and the result is output. do. The output of the modulo 3 calculation circuit 607 is the calculation result Z
The modulo-3 expected value of is inputted to the modulo-3 subtraction circuit 203 through the data path 67. The modulo 3 subtraction circuit 203 inputs the modulo 3 value of part Z ₂ of the calculation result Z through the data path 22, and also inputs the modulo 3 expected value of Z through the data path 67, so that any modulo 3 value is [ 1, 1], outputs [1, 1] as is, and when both are not [1, 1], Z-
Generate and output modulo 3 values of Z ₂ . The output of the modulo-3 subtraction circuit 203 is the modulo-3 expected value of a part of the operation result _Z1 , which is output to the data path 2.
3 through the first result module 3 matching circuit 204
This is one input. The first result modulo 3 matching circuit 204 inputs the modulo 3 value of part Z1 of the operation result Z through the data path 21, and also inputs the modulo 3 value of part _Z1 of the calculation result Z through the data path 23.
When the expected modulo 3 value of Z ₁ is input, the first input modulo 3 matching circuit 604 and the second input modulo 3 matching circuit 605 execute a match check between the modulo 3 value of Z ₁ and its expected value. When they match, the modulo 3 values of Z ₁ are output as they are, and when either the modulo 3 values of Z ₁ and the expected value are [1, 1], or the modulo 3 values of Z ₁ and their When the expected values do not match, [1, 1] is output, and the output modulo 3 values are sent to the data path 24.
It becomes the input of the modulo 3 output register 706 through the input signal. The modulo 3 output register 706 inputs the output modulo 3 value of the first result modulo 3 matching circuit 204 through the data path 68 and outputs it through the data path 76 after being stored by the strobe signal.
This output modulo 3 value is 1 of the arithmetic circuit 2000.
It is used as an output for the input of the subsequent modulo 3 circuit. However, when the value held in this register before the input of the strobe signal is [1, 1], the value is [1,
1] is held and the output does not change. In the arithmetic circuit 2000, for example, if a failure occurs in the output of the first modulo 3 holding register 704 and the modulo 3 value on the data path 74 becomes [1, 1], the incorrect value [1, 1] is used as the modulo 3 value.
1] passes through the data path 74, passes through the modulo 3 arithmetic circuit 607, passes through the data path 67, passes through the modulo 3 subtraction circuit 203, passes through the data path 23, passes through the first result modulo 3 matching circuit 204, and then the data It passes through the path 24, the modulo 3 output register 706, and the data path 76 to output the modulo 3 value C=[1,1]. As a second example, when the modulo 3 value of Y and its expected value B do not match by the second input modulo 3 matching circuit 605, [1, 1] is determined by the data path 6.
5 through the data path 75 from the second modulo 3 holding register 705 to the modulo 3
From the arithmetic circuit 607 through the data path 67, from the modulo 3 subtraction circuit 203 through the data path 23, from the first result modulo 3 matching circuit 204 through the data path 24, and from the modulo 3 output register 70.
6 through data path 76 to modulo ternary C=
Outputs [1, 1]. Further, when the calculation result Z is an abnormal value due to a failure of the calculation circuit 601, one of the modulo 3 values on the data paths 21 and 22 becomes abnormal. When the modulo 3 value on the data path 22 is an abnormal value, it passes through the data path 23 via the modulo 3 subtraction circuit 203, and the abnormal value is the first result modulo 3 matching circuit 2 as the modulo 3 expected value of _Z1 .
04, a match check is executed with the modulo 3 value of Z ₁ from the data path 21, and when they do not match, the value [1, 1] is outputted through the data path 24, and the data is output from the modulo 3 output register 706. Through path 76, modulo ternary C=[1,1]
Output. The same applies to the case where the input expected value A = [1, 1], and the data paths 64, 74, 67, 23, 24,
And the modulus 3 value on 76 is [1, 1],
Outputs modulo 3-value C=[1, 1]. As mentioned above, when a failure occurs in the arithmetic circuit 2000 or when the input data is invalid, the output modulo 3 value C becomes an invalid value [1, 1] as the value of the modulo 3, and the output of the arithmetic circuit 2000 The fact that a failure has occurred in the stage before C can be transmitted to the modulo 3 circuits in the rear stage. Also, with this modulo 3-value C = [1, 1],
After a failure is reported, in order to find out in which part of the entire circuit the failure occurred, it is easy to pinpoint the failure location by examining how the invalid modulo ternary value [1, 1] has been propagated. It is. FIG. 3 is a block diagram showing a third embodiment of the present invention, in which input modulo 3 values or output modulo 3 values are input to three modulo 3 registers 704, 705, 706 in the arithmetic circuit 2000 of FIG. [1,
When a strobe signal is input in the state of [1],
If a strobe signal is input in other conditions,

FIG. 7 is a block diagram showing an example in which a function to output 1-bit data of [0] and an OR circuit 507 are added. Referring to FIG. 3, the first modulo 3 holding register 504 inputs the output modulo 3 value of the first input modulo 3 matching circuit 604 through the signal line 64, stores it by the strobe signal, and then transfers the output modulo 3 value to the data path 74. output through the modulo 3 arithmetic circuit 607
1 input. However, when the retention rate in this register before strobe signal input is [1, 1], or when data path 6
When the modulo 3 value input through 4 is [1, 1], [1, 1] is held even after the strobe signal is input, and the output modulo 3 value of this register is [1, 1] regardless of the strobe signal. The 1-bit data l ₁ =1 for error reporting and not changing is output through the data path 54 and output to the OR circuit 507.
This is one input. The second modulo 3 holding register 505 is connected to the second modulo 3 match circuit 60 through the data path 65.
The output modulo 3 value of 5 is inputted, stored by a strobe signal, and then outputted through the data path 75 and used as one input of the modulo 3 arithmetic circuit 607. However, when the value held in this register before strobe input is [1, 1], or when the input modulo 3 value is [1, 1], the value is [1, 1] as in the first modulo 3 holding register 504. is retained and does not change, and the 1-bit error report data l ₂ = 1
is output through the data path 55 and becomes one input of the OR circuit 507. The modulo 3 output register 506 inputs the output modulo 3 value of the first result modulo 3 matching circuit 608 through the signal line 68 and outputs it through the data path 76 after being stored by the strobe signal. This output modulo 3-value C is used as one output of the arithmetic circuit 3000 as an input to a subsequent stage modulo 3-value circuit. However, when the value held in this register before the strobe signal is input is [1, 1], or when the input modulo 3 value is [1, 1], the first and second modulo 3 holding registers 504 and 505 Similarly [1,
1] is held and does not change, and the error report 1-bit data l ₃ =1 is output through the data path 56 and becomes one input of the OR circuit 507. The OR circuit 507 connects the
When l ₁ is input, l ₂ is input through the data path 55, and l ₃ is input through the data path 56, the logical sum E of l ₁ , l _2, and l ₃ is generated and output. l ₁ , l ₂ , l ₃ are when the values held in their respective modulo 3 registers are [1, 1],
In other words, since it is 1-bit data that becomes 1 when a failure is detected, the logical sum E=1 is calculated by the arithmetic circuit 300.
This indicates that a failure was detected within 0. The other circuits in the arithmetic circuit 3000 are the same as the arithmetic circuit 2000 in FIG. 2, so their explanation will be omitted. FIG. 4 is a block diagram showing a fourth embodiment of the present invention. Referring to FIG. 4, an arithmetic circuit 4000
takes two binary data X, Y and their respective modulo ternary values A, B as input, and calculates the calculation result Z between X and Y and the modulo ternary value C of a part of data Z ₁ of Z.
and the modulo ternary value D of the remaining data _Z2 . In this embodiment, an example of a modulo 3 circuit suitable for a case where data Z resulting from an operation is handled separately as two pieces of data Z ₁ and Z ₂ in a subsequent circuit is shown. The circuit before the circuit that generates the modulo ternary values C and D, that is, the first and second input registers 70
1,702, arithmetic circuit 601, arithmetic result output register 703, first and second input modulo 3 generation circuits 602, 603, first and second modulo 3 matching circuits 604, 605, first and second modulo 3 holding registers 704 and 705 are the arithmetic circuits 2000 in FIG.
Since it is equivalent to , the explanation will be omitted. When the first result modulo 3 generation circuit 401 receives part of the data Z ₁ of the operation result Z through the data path 731, it generates its modulo 3 values, outputs them through the data path 41, and outputs them through the data path 41. and second result modulo 3 subtraction circuit 40
4 and 1 input. The second result modulo 3 generation circuit 402 generates data Z ₁ out of the operation result Z through the data path 732.
When the remaining data Z ₂ except for is input, its modulo 3 value is generated, outputted through the data path 42, and sent to the second result modulo 3 matching circuit 406 and the first
It is assumed to be one input to the result modulo 3 subtraction circuit 403. The modulo 3 arithmetic circuit 607 is a first modulo 3
The output modulo 3 values of the holding register 704 are input through the data path 74, and the output modulo 3 values of the second modulo 3 holding register 705 are input through the data path 75, so that any of the modulo 3 values is [1, 1]. In this case, [1, 1] is output as is, and if both are not [1, 1], a modulo 3 operation corresponding to the arithmetic circuit 601 is executed between the two modulo 3 values, and the result is output. do. The output of the modulo 3 arithmetic circuit 607 is passed through the data path 67 to the first result modulo 3 subtraction circuit 403 and the second result modulo 3 subtraction circuit 403 as the modulo 3 expected value of the calculation result Z.
It is assumed to be one input to the result modulo 3 subtraction circuit 404. The first result modulo 3 subtraction circuit 403 inputs the modulo 3 value of part Z ₂ of the calculation result Z through the data path 42, receives the expected modulo 3 value of Z through the data path 67, and calculates any modulo 3 value. When the values are [1, 1], [1, 1] is output as is, and when both are not [1, 1], a modulo 3 value of Z-Z ₂ is generated and output. The output of the first result modulo 3 subtraction circuit 403 is
The part of the calculation result Z ₁ becomes one input of the first result modulo 3 matching circuit 405 through the data path 43 as a modulo 3 expected value. The second result modulo 3 subtraction circuit 404 modulo ₃ of part Z1 of the operation result Z through the data path 41.
While inputting the value, Z
The expected value of modulo 3 is input, and if any of the modulo 3 values is [1, 1], it outputs [1, 1] as is, and when both are not [1, 1],
Generate and output modulo 3 values of Z-Z ₁ . The output of the second result modulo 3 subtraction circuit 404 is the expected modulo 3 value of part Z ₂ of the calculation result,
Through the signal line 44, it becomes one input of the second result modulo 3 matching circuit 406. When the first result modulo 3 matching circuit 405 inputs the expected modulo 3 value of part _Z1 of the operation result Z through the data path 41 through the data path 43, the first result modulo 3 matching circuit 405 executes a matching check and determines whether they match. When the modulo 3 value of Z ₁ is output as is, either the modulo 3 value of Z ₁ and the expected value are [1, 1], or the modulo 3 value of Z ₁ and the expected value match. If not, it outputs [1, 1], and the output modulo 3 value is sent to data path 45.
It becomes an input to the first modulo 3 output register 407 through the input signal. The second result modulo 3 matching circuit 406 modulo ₃ of part Z2 of the operation result Z through the data path 42.
When the expected value is input through the data path 43, a match check is executed, and if it matches,
Output the modulus 3 values of Z ₂ as is, and when either the modulus 3 values of Z ₂ or the expected value is [1, 1],
Alternatively, when the modulo 3 value of Z ₂ and its expected value do not match, [1, 1] is output, and the outputted modulo 3 value is input to the second modulo 3 output register 408 through the data path 46. Become. The first modulo 3 output register 407 inputs the output modulo 3 value of the first result modulo 3 matching circuit 405 through the data path 45, stores it in accordance with the strobe signal, and outputs it through the data path 47. This output modulo 3-value C is calculated by the arithmetic circuit 400.
It is used as an input to the subsequent stage modulo 3 circuit as a 1 output of 0. However, when the value held in this register before the input of the strobe signal is [1, 1], [1, 1] is held and the output does not change. The second modulo 3 output register 408 inputs the output modulo 3 value of the first result modulo 3 matching circuit 406 through the data path 46 and outputs it through the data path 48 after being stored by the strobe signal. This modulo 3-value D is calculated by the arithmetic circuit 4000.
It is used as an input for the subsequent stage modulo 3 circuit as one output. However, when the value held in this register before the input of the strobe signal is [1, 1], [1, 1] is held and the output does not change. When a failure occurs in the arithmetic circuit 4000 or when the input data is invalid, the output modulo 3-value C,
D is an invalid value for modulus 3 [1, 1]
Therefore, the fact that a failure has occurred in the stage before the output C or D of the arithmetic circuit 4000 can be transmitted to the subsequent stage modulo three circuits, and the failure can be detected by the modulo three values C or D = [1, 1]. After being reported, in order to find out in which part of the entire circuit the failure occurred, it is easy to pinpoint the failure location by investigating how the incorrect modulo ternary value [1, 1] has been propagated. In this respect, it is similar to the arithmetic circuit 2000 in FIG. 2, so a description thereof will be omitted. FIG. 5 is a truth table showing an example of a modulo-3 arithmetic circuit used in the present invention. FIG. 5a corresponds to an adder circuit, b a subtracter circuit, c a multiplier circuit, and d an inverter circuit, which are truth tables for modulo-3 addition, modulo-3 subtraction, modulo-3 multiplication, and modulo-3 inversion circuits, respectively. However, 1 indicates an arbitrary value. An example of the adder circuit shown in FIG. 5a will now be described. In the check circuit of an adder circuit that calculates the sum _Z of two arbitrary binary numbers X and Y, the value of modulo ₃ of the input binary number Assuming that the values are B=[b ₁ , b ₂ ], an expected value C=[c ₁ , c ₂ ] as the modulo 3 value of the addition result Z of the binary numbers X and Y is prepared. For example, A=[0,
1], B=[1, 0], then C=[0, 0] from the truth table of FIG. 5a. The above is equivalent to the conventional modulo 3 circuit, but
The feature of this circuit is that the value of modulo 3 is [1,
1] was taken into consideration. If the value of modulo 3 is A = [a ₁ ,
A = [1, 1] due to a failure in the circuit that generates _{a 2} ]
In this case, as shown in the truth table in Figure 5a,
Expected value C=[c ₁ , c ₂ ]=[1, 1]. The same applies to failures on the binary Y side. In other words, there are three cases in which the expected value C is [1, 1]; 1 is when A = [1, 1], and the other is when B =
[1, 1], and a case where C=[1, 1] due to a failure of the modulo-3 addition circuit itself. FIG. 6 is a diagram showing a truth table of a modulo-3 matching circuit used in the present invention. When two 2-bit data A=[a ₁ , a ₂ ] and B=[b ₁ , b ₂ ] are A=B, C=[c ₁ , c ₂ ]=[a ₁ , a ₂ ], When A≠B and when A or B = [1, 1], C = [c ₁ , c ₂ ]
Outputs 2-bit data C such that =[1, 1]. FIG. 7 shows a check circuit including a modulo-3 arithmetic circuit 302 configured with the logic shown in the truth table of FIG. 5 and a modulo-3 matching circuit 303 configured with the logic shown in the truth table of FIG. FIG. For example, two binary data X = [0, 1, 1, 0]
By adding Y=[0, 1, 0, 1], X and Y
In the case of a check circuit of an adder circuit that outputs the sum Z=X+Y [1, 0, 1, 1], the modulo 3 arithmetic circuit 302 outputs the modulo 3 value of X A=[a ₁ , a ₂ ]=
[0, 0] and Y modulo ternary value B = [b ₁ , b ₂ ] =
Input [1, 0], sum of A and B C=A□+B
= [c ₁ , c ₂ ] = [1, 0] is generated as a modulo 3 expected value, and is passed through the data path 32 as a modulo 3
It is assumed to be one input of the matching circuit 303. When the modulo 3 generation circuit 307 inputs the sum binary number Z, the modulo 3 value of Z = [d ₁ , d ₂ ] = [1,
0] is generated and sent to the modulus 3 through the data path 31.
Input 1 in the matching circuit 303. When the modulo 3 matching circuit 303 inputs the modulo 3 value D of Z through the data path 31 and its expected value C through the data path 32, when D=C, M=[m ₁ , m ₂ ]=[d ₁ , d ₂ ], when D≠C,
and when D or C=[1, 1], M=[m ₁ ,
2-bit data M with m ₂ ]=[1, 1] is output. Here, if a failure occurs in the modulo 3 generating circuit 301 and D = [1, 1], and if the input A or B of the modulo 3 arithmetic circuit 302 becomes [1, 1], the modulo 3 arithmetic circuit If a failure occurs in 302 and C = [1, 1], modulus 3
A failure occurs in the coincidence circuit 303 itself, and M=[1,
1], the arithmetic circuit section or modulo 3
If a failure occurs in the arithmetic circuit 302 and D≠C, the output M = [1, 1] in either case, it is detected that a failure has occurred in the circuit before the output M, and the failure is detected. The value of modulo 3 [1, 1] shown will be output to the check circuit at the subsequent stage. The check circuit at the latter stage can determine that the data is normal when a value other than [1, 1] is input, and that a failure has been detected when it is [1, 1]. Figures 8a and 8b are truth tables and block diagrams of modulo 3 registers used in the present invention. Referring to FIGS. 8a and 8b, modulo 3 register 501 inputs 2-bit data D=[d ₁ , d ₂ ] and strobe signal STB, and according to the logic configuration shown in the truth table, 2-bit data E= [e ₁ , e ₂ ] is output. For example, when the output E = [1, 0] before the strobe signal is input, when the strobe signal is input with D = [0, 1], the output E changes from [1, 0] to [0, 1]. . Similarly, in this state D=
When a strobe signal is input at [0, 0], the output E changes from [0, 1] to [0, 0]. However, when the original state of the output E is [1, 1], it will remain in the [1, 1] state regardless of the value of D. Therefore, when D = [1, 1] or E = [1, 1], the output E after strobe input is fixed to [1, 1], and [1, 1] is originally invalid data as the value of modulo 3. Therefore, it is detected that a failure has occurred in the circuit before this circuit. Furthermore, if an error report signal is generated from the invalid data [1, 1] of this circuit, this circuit will also serve as an error display flag. FIGS. 9a and 9b are a truth table and a block diagram of a modulo 3 register in which a function for outputting bit data f that can be used for error reporting, etc. is added to the modulo 3 register 501 of FIG. 8. Referring to FIGS. 9a and 9b, the modulo 3 register 502 inputs the 2-bit data D=[d ₁ , d ₂ ] and the strobe signal STB, and according to the logical configuration shown in the truth table, the 2-bit data E= [e ₁ , e ₂ ] and 1-bit data f are output. 1-bit data f becomes "1" when a strobe signal is input in the state of input D = [1, 1], and then output E
=[1, 1] and the state of f=1 is maintained. Since this 1-bit data f=1 means that invalid data [1, 1] has been input, it can be used as it is as an error report signal. The other operations are the same as those of the modulo 3 register 501 explained in FIG. 8, so the explanation will be omitted. In the above embodiment, W=3, that is, a modulo 3 circuit was explained, but W=2 ^w −1(w
is an integer greater than or equal to 2). [Effect of the invention] As explained above, in the present invention, invalid data [1,..., 1] is considered as the value of modulo W, and [1, ..., 1] is
..., 1] as the value of modulo W at the time of fault detection, [1, ..., 1] of the check circuit itself
In addition to being able to detect failures in the circuit, it is also possible to transmit the failure detection in the previous stage to the check circuit in the subsequent stage, and by following the transmission path of [1,...,1],
Since it is easy to identify the fault location, the detection rate and resolution of the entire check circuit can be improved, and the structure can be made suitable for LSI implementation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a block diagram showing an example of an arithmetic circuit using the modular 3 circuit of the present invention as a check circuit, Fig. 3 is a block diagram showing another example of the arithmetic circuit, and Fig. 4 is a block diagram showing yet another example of the arithmetic circuit. A block diagram showing an example, FIG. 5 shows a module 3 used in the present invention.
FIG. 6 is a diagram showing the truth value display of the arithmetic circuit; FIG. 6 is a diagram showing the truth value table of the modulo-3 matching circuit used in the present invention; FIG. 7 is a diagram showing the truth value table of the modulo-3 matching circuit used in the present invention; A block diagram showing an example, FIGS. 8a and 8b are a diagram and a block diagram showing a truth table of a modulo 3 register used in the present invention, respectively, and FIGS. 9a and b are another example of a modulo 3 register, respectively. Fig. 10 is a block diagram showing an example of a conventional modulo 3 check circuit; Fig. 11 is a part of an arithmetic unit; FIG. 2 is a block diagram showing an example. 101, 102, 602, 603, 201, 2
02,401,402,301,812,81
3,816... Modulo 3 generation circuit, 103,6
07,302,817... Modulo 3 arithmetic circuit,
104, 203, 403, 404...Mojiyuro 3
Subtraction circuit, 105, 604, 605, 204, 4
05,406,303...modulo 3 matching circuit,
1000...Modulo 3 circuit, 704,705,
706,504,505,506,407,40
8,501,502,804,805,806...
...Module 3 register, 701, 702, 80
1,802...Input register, 601,811...
... Arithmetic circuit, 703, 803... Arithmetic result output register, 507, 810... OR circuit, 200
0,3000,4000,8000... Arithmetic circuit, 814,815,818... Matching circuit, 80
7,808,809...EIF, 9001,900
2...Input operand register, 9003...Arithmetic result register, 9011...Arithmetic circuit, 901
2... Modulo 3 expected value generation circuit, 9004...
Modulo 3 expected value register, 9013... Modulo 3 coincidence check circuit, 9005... Error display flag, 9000... Arithmetic unit.

Claims (1)

[Claims] 1 n (n is an integer of 2 or more) w (w is an integer of 2 or more) bit data A ₁ = [a ₁₁ , ..., a _1w ], A ₂ =
[a ₂₁ , ..., a _2w ], ..., A _o = [ _{a o1} , ..., _{a ow} ] as inputs, and _the modulus W (W =2 ^w −1) The result of the operation is D=[d ₁ ,
…, d _w ], the inputs A ₁ , A ₂ , …, A _o
If one or more of them is [1,...,1], C=
[1,...,1], otherwise C=[d ₁ ,..., d _w ]
A modulo W arithmetic circuit that outputs w-bit data C=[c ₁ ,...,c _w ] and N-bit data Z
Among them, M-bit data _Z1 is input and the data is
a first modulo W generation circuit that generates and outputs a modulo W value E=[e ₁ ,..., e _w ] of Z ₁ ;
Among them, input the N-M bit data _Z2 excluding the data _Z1 , and calculate the modulo W value F of the data _Z2 .
A second modulo W generation circuit that generates and outputs = [f ₁ , ..., f _w ] and an output C of the modulo W calculation circuit
= [c ₁ , ..., c _w ] and the output F = [f ₁ , ..., f _w ] of the second modulo W generation circuit are input, and the modulo of the difference C - F between the inputs C and F is The W value is G=[g ₁ ,
..., g _w ], when one or more of the inputs C and F are [1, ..., 1], H = [1, ...,
1], otherwise H = [g ₁ , ..., g _w ].
A modulo W subtraction circuit that outputs bit data H=[h ₁ ,..., h _w ], an output H=[h ₁ ,..., h _w ] of the modulo W subtraction circuit, and an output of the first modulo W generation circuit. The output E = [e ₁ , ..., e _w ] is input, and H
= E, then K = [e ₁ , ..., e _w ], H≠E or H, and when one or more of E is [1, ..., 1], K = [1, ..., 1] w bit data K=
a modulo W matching circuit that outputs [k ₁ , ..., k _w ], and the n input data A ₁ , A ₂ , ..., A _o
When the result G obtained by subtracting the modulus W value F from the calculation result D between the two matches the modulus W value E, and there is no value of [1,...,1] in the input data, K = E = [e ₁ ,..., e _w ], otherwise K = [1,..., 1], w bit data K
A modulo W circuit characterized in that it outputs = [k ₁ ,..., k _w ]. 2 n (n is an integer of 2 or more) w (w is an integer of 2 or more) bit data A ₁ = [a ₁₁ ,..., a _1w ], A ₂ =
[a ₂₁ , ..., a _2w ], ..., A _o = [ _{a o1} , ..., _{a ow} ] as inputs, and _the modulus W (W =2 ^w −1) The result of the operation is D=[d ₁ ,
…, d _w ], the inputs A ₁ , A ₂ , …, A _o
If one or more of them is [1,...,1], C=
[1,...,1], otherwise C=[d ₁ ,..., d _w ]
A modulo W arithmetic circuit that outputs w-bit data C=[c ₁ ,...,c _w ] and N-bit data Z
Among them, a first modulo W generation circuit receives M-bit data Z ₁ as input and generates and outputs a modulo W value E=[e ₁ , ..., e _w ] of the data Z ₁ ; , a second modulo W generation circuit which takes as input N-M bit data Z ₂ excluding the data Z ₁ and generates and outputs a modulo W value F=[f ₁ , _. . . , f _w ] of the data Z 2. , the output C = [c ₁ , ..., c _w ] of the modulo W calculation circuit, and the output F = [f ₁ , ..., f _w ] of the second modulo W generation circuit, and the input C The modulus W value of the difference C-F between and F is G=
When [g ₁ , ..., g _w ], when one or more of the inputs C and F are [1, ..., 1], H = [1,
..., 1] In other cases, a modulo W subtraction circuit outputs w-bit data H=[h ₁ , ..., h _w ] such that H=[g ₁ , ..., g _w ]; Output H=[h ₁ ,..., h _w ] and the first modulus W
The output E = [e ₁ , ..., e _w ] of the generation circuit is input,
When H=E, K=[e ₁ , ..., e _w ]; when H≠E or H, one or more of E is [1, ..., 1], K = [1, ..., 1] ], w bit data K=
a modulo W matching circuit that outputs [k ₁ ,..., k ₂ ];
On the transmission path of the modulo W value, input the modulo W value L = [l ₁ , ..., l _w ] and the strobe signal, and output the strobe signal in the state of P = [1, ..., 1]. If you input strobe signal in other conditions, P = [l ₁ ,
..., l _w ], w bit data P = [p ₁ , ..., p _w ]
a modulo W register that outputs as a modulo W value after one strobe of the input L=[l ₁ , . . . , l _w ], and the n input data A ₁ , A ₂ , .
When the result G obtained by subtracting the modulus W value F from the calculation result D between A _{and o} matches the modulus W value E, and there is no value of [1,...,1] in the input data, , w bit data K=E=[e ₁ ,
..., e _w ], and in other cases K=[1, ...,
1], the modulo W circuit holds and outputs the modulo W circuit, and detects the transmission path of [1, . . . , 1] based on the value held in the modulo W register. 3 n (n is an integer of 2 or more) w (w is an integer of 2 or more) bit data A ₁ = [a ₁₁ ,..., a _1w ], A ₂ =
[a ₂₁ , ..., a _2w ], ..., A _o = [ _{a o1} , ..., _{a ow} ] as inputs, and _the modulus W (W =2 ^w −1) The result of the operation is D=[d ₁ ,
…, d _w ], the inputs A ₁ , A ₂ , …, A _o
If one or more of them is [1,...,1], C=
[1,...,1], otherwise C=[d ₁ ,..., d _w ]
A modulo W arithmetic circuit that outputs w-bit data C=[c ₁ ,...,c _w ] and N-bit data Z
Among them, a first modulo W generation circuit receives M-bit data Z ₁ as input and generates and outputs a modulo W value E=[e ₁ , ..., e _w ] of the data Z ₁ ; , a second modulo W generation circuit which takes as input N-M bit data Z ₂ excluding the data Z ₁ and generates and outputs a modulo W value F=[f ₁ , _. . . , f _w ] of the data Z 2. , the output C = [c ₁ , ..., c _w ] of the modulo W calculation circuit, and the output F = [f ₁ , ..., f _w ] of the second modulo W generation circuit, and the input C The modulus W value of the difference C-F between and F is G=
When [g ₁ , ..., g _w ], when one or more of the inputs C and F are [1, ..., 1], H = [1,
..., 1], and a modulo W subtraction circuit that outputs w-bit data H=[h ₁ , ..., h _w ] such that H=[g ₁ , ..., g _w ] in other cases, and the modulo W subtraction circuit. output H = [h ₁ ,..., h _w ], and the first modulus W
The output E = [e ₁ , ..., e _w ] of the generation circuit is input,
When H=E, K=[e ₁ , ..., e _w ]; when H≠E or H, one or more of E is [1, ..., 1], K = [1, ..., 1] ], w bit data K=
A modulo W matching circuit that outputs [k ₁ , ..., k _w ], the modulo W value L = [l ₁ , ..., l _w ] and a strobe signal are connected on the transmission path of the modulo W value. When inputting a strobe signal with the output P=[1,...,1], P=[1,...,1],
When a strobe signal is input in other conditions, P=
w bit data P = [p ₁ , ..., l _w ] [l ₁ , ..., l w ]
p _w ] as the modulo W value after one strobe of the input L = [l ₁ , ..., l _w ], and the input L = [1, ..., 1] or p = [1, ...,
1], when a strobe signal is input, q=
1. A modulo W register that outputs 1-bit data q such that q=0 when a strobe signal is input in any other state, and the n input data
The result G obtained by subtracting the modulus W value F from the calculation result D between A ₁ , A ₂ , ..., A _o , and the modulus W
The value E matches, and the input data contains [1,
..., 1], w bit data K=E
= [e ₁ , ..., e _w ], and in other cases K =
[1, . . . , 1] are held, and an error report is output using the w bit data K and the 1 bit data q, and at the same time, according to the value held in the modulo W register, [1, . . . 1) A modulo W circuit characterized by detecting the transmission path.