JPH0786840B2 - Modulo W circuit - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and particularly to a checker for an arithmetic circuit or the like.
The present invention relates to a modulo W circuit used in a clock. [Prior Art] Modulo W circuits are used as check circuits for arithmetic circuits and the like.
One of the more frequently used check circuits
It Also, as the modulus W, W = 2 ^W -1 (for example, 3,7,1
5, ...) is often used. Because of modulo W
The value can be expressed in w bits, so compared to other modulus
This is because it can be realized at low cost. Below, W = 2 ^W As a representative of -1, W = 2 ² Consider -1 = 3.
2-bit data for three values 0, 1, 2 of modulo 3
Four values that can be expressed [0,0], [0,1], [1,
0] Define three values among [1,1]. For example, 0
For [0,0], for 1 for [0,1], for 2 for [1,0]
Let Fig. 10 shows an example of a modulo 3 circuit conventionally used
Indicates. In FIG. 10, the arithmetic unit 9000 is the first input device.
Input the data and the second input data
Input operand register 9001, second input operand register
Stored in the computer 9002, and the first input operation is performed by the arithmetic circuit 9011.
The operation between the land and the second input operand,
The result of is stored in the operation result register 9003 and then output.
It The modulo 3 circuit in this arithmetic unit 9000 is modulo
3 expected value generation circuit 9012 and modulo 3 expected value register 90
04, modulo 3 match check circuit 9013, and error display
It is composed of a flag 9005. The modulo-3 expected value generation circuit 9012 has the first input operand
Register 9001 and second input operand register 9002
1st input operation through the data paths 901 and 902, respectively.
When the land and the second input operand are input, the arithmetic circuit
The modulo 3 operation corresponding to 9011 is executed and the operation result
Generate expected values for Juro 3 and through datapath 912
Output to the modulo 3 expected value register 9004. The modulo 3 expected value register 9004 is used to generate the modulo 3 expected value
Data path of expected value of modulo 3 which is output of synthesis circuit 9012
Input through 912, store and then through data path 904
Output to the modulo 3 match check circuit 9013. Modulo 3 match check circuit 9013 is the operation result register
If you input the calculation result from data path 903 from 9003
Data path 90 from modulo 3 expected value register 9004
Input the expected value modulo 3 through 4, and
Modulo 3 is generated and its value and modulo 3 expected value are equal.
Check whether or not they match, and if they do not match
Reports the error report through the datapath 913.
Output to lag 9005. The error display flag (hereinafter referred to as FIF) 9005 is a data
Input error report via switch 913 and store it
If the value is held until the release signal is input,
Both output an error report through the data path 905. By the operation as described above, the failure of the arithmetic unit 9000 is detected.
However, in a general modulo 3 circuit,
Performing checks in more detail than shown in Figure 10
Is normal. In other words, not only the final result of the arithmetic circuit,
A similar match check is also performed on the intermediate results.
It In this case, the intermediate result modulo 3 expected value is the data
It is input to the arithmetic circuit through the switch 921. FIG. 11 shows a part of the arithmetic circuit in the arithmetic unit.
When performing a modulo 3 check on intermediate results
It is a figure which shows an example. In FIG. 11, the arithmetic circuit 8000 shows two binary data X and Y.
And the respective modulo 3 values A and B are input, and binary data
Calculation result Z between X and Y, and modulo 3 of calculation result Z
Error report E with value C and modulo 3 check result
And are output. The first input register 801 and the second input register 802 are respectively
After inputting and storing the binary data X and Y,
Output binary data X and Y through data paths 81 and 82, and
Input the binary data X and Y into the arithmetic circuit 811
X and Y are the first input modulo 3 generation circuit 812 and
And the second input modulo 3 generation circuit 813. The arithmetic circuit 811 passes the binary data X through the data path 81.
, And when the binary data Y is input through the data path 82, 2
The operation is executed between the binary data X and Y, and the operation result Z
To the operation result output register 803 through the data path 91
To do. The operation result output register 803 plays through the data path 91.
After inputting and storing the calculation result Z, play through the data path 83
The calculation result Z is output. Calculation result Z is the output of calculation circuit 8000
And the input of the calculation result modulo 3 generation circuit 816
Becomes The first input modulo 3 generation circuit 812 passes through the data path 81.
And input the binary data X, the modulo 3 value is generated.
Generated and output through the data path 92 to obtain the modulo 3 value.
Input to the matching circuit 814 and the first modulo 3 holding register 804.
It The second input modulo 3 generation circuit 813 passes through the data path 82.
And input the binary data Y, the modulo 3 value is generated.
Generated and output through the data path 93 to obtain the modulo 3 value.
Input to the input circuit 815 and the second modulo-3 holding register 805.
It 1st modulo 3 holding register 804 and 2nd modulo 3 holding
The register 805 is binary through the data paths 92 and 93, respectively.
After inputting and storing modulo 3 values of data X and Y,
Input of modulo 3 arithmetic circuit 817 through data paths 84 and 85
Use as power. The modulo 3 arithmetic circuit 817 is binary through the data path 84.
Binary modulo 3 value of data X through data path 85
Input the modulo 3 value of the data Y and calculate the calculation circuit 811
Modulo 3 operation corresponding to
Generate expected value of Euro 3 and output through data path 97
Then, the coincidence circuit 818 is input. The calculation result modulo 3 generation circuit 816 passes through the data path 83.
And input the operation result Z, the modulo 3 of the operation result Z
Generates a value and passes it through the datapath 96 to the matching circuit 818
It is used as an input of the output unit 806 of the Euro 3 output. Modulo 3 output register 806 is routed through datapath 96
After inputting and storing the modulo 3 value of the operation result Z, the data
Output modulo-3 value C of operation result Z through path 86
It The modulo 3-value C of the operation result Z is one output of the operation circuit 8000.
As a force, input of the modulo 3 circuit (not shown) in the latter stage, etc.
Used for. The matching circuit 814 outputs the binary data X through the data path 92.
Input modulo 3 value and modulo binary data X
3 Input expected value A, modulo 3 value of binary data X and its
Check if the expected value A matches,
FIF through datapath 94 if not
(Error display flag) Output to 808. The matching circuit 815 is also input from the data path 93
Compare the modulo-3 value of the base data Y and its expected value B,
The result is output to the FIF809 via the data path 95. Similarly, the matching circuit 818 is also an operation input from the data path 96.
Result Z input modulo 3 value and data path 97
Compared with the waiting value and the result is passed through the data path 98 to FIF8
Output to 07. FIF807,808,809 through data path 98,94,95 respectively
If you enter an error report with
Hold that value until you enter the
Output to the Riwa circuit 810. The OR circuit 810 gives an error from one of FIF807, 808, and 809.
When a report is input, an error report E indicating failure occurrence is calculated
Output as one output of the circuit 8000. [Problems to be Solved by the Invention] In FIGS. 10 and 11, the conventional modular 3 circuit is used.
Modulo 3 is the remainder of dividing the numerical value indicated by the data by 3.
Ri. For the mathematical reason that it is
Then, 3 or binary data [1,1] is not considered.
However, the module originally used in the data processing device is
(B) Circuit 3 is a check circuit for detecting circuit failures.
Since it is used for
The case where the value of 3 is [1,1] should also be considered. For example, in FIG. 11, the first input modulo 3 generation circuit 81
[1,1] is output on the path of data path 92 due to the failure of 2.
, The input of the conventional modulo 3 circuit [1,1]
Output is indefinite, the coincidence circuit 814, modulo 3 operation times
The outputs of the path 817, the matching circuit 818, etc. have a logical meaning.
No, it depends on the circuit configuration. Therefore, due to the failure of the modulo 3 circuit itself, [1,1]
It is difficult to detect the failure when the pattern of
In addition, the calculation result is incorrect due to a failure in the calculation circuit.
Even when it becomes positive, the value of modulo 3 is [1,
If the same value as the output for [1], the failure is detected.
If the detection rate of the check circuit drops significantly,
Not in the scale, but in the check circuit below it
-When the display flag lights up, the failure location can be pointed out.
It becomes a factor that causes an error. If a part of the arithmetic circuit is realized by LSI, etc.
A certain type of test is usually used for evaluation for failure detection of a single unit such as SI.
Output and flip-flop for input of strike pattern
Logic gates and logic patterns in LSI etc.
To verify. If the modulo 3 circuit is included in the LSI,
Then, if the case of [1,1] is not included, the detection rate is improved.
Not logically meaningless as a whole arithmetic circuit
It is necessary to describe the logic even for the input of [1,1]
And its logic depends entirely on the circuit configuration.
The description is complicated and difficult to understand. On the other hand, as a check circuit using modulo 3,
Generated from the expected value of modulo 3 and the actual calculation result
The value of modulo 3 is checked for a match. for that reason,
In order to improve the detection rate, the expected value of each part of the arithmetic circuit
You have to create and set an error flag for each of them.
Therefore, as the amount of hardware increases significantly,
When several error flags light up, the cause is the same.
It is difficult to determine whether it is due to an obstacle. Generally, in the conventional modulo W circuit, all bits are "1".
As a modulo W circuit,
It is difficult to improve the fault coverage and resolution, and in recent years
When verifying the check circuit associated with the LSI implementation of
The logical description of "1" is an obstacle to improving design efficiency
There is a drawback that. In other words, the conventional modulo W circuit
While the check circuit design is easy, the parity check
When an error occurs by comparing with other check circuits such as
Error detection rate for error detection and error detection
It has the drawback of low resolution. [Means for Solving the Problems] The present invention is a model having a w-bit input and a w-bit output.
Juro W circuit expressed by w bits (w ≧ 2)
Can 2 ^w All binary bits are "1"
Exclude W (= 2 ^W -1) One code of binary values
Is defined as an error code indicating that a failure has been detected.
Is defined, and the remaining W (= 2) in which all bits include "1" ^W -1)
The binary value of R is defined as the W code of modulo W
Error code generated when a failure occurs or is detected.
When it is done, it is special to propagate the error code.
Is a modulo W circuit that is a characteristic
Type A ₁ = [A ₁₁ , a ₁₂ …, A _1w ], A ₂ = [A _{twenty one} , a _{twenty two} …, A _2w ], ...,
A _n = [A _n1 , a _n2 , ..., a _nw ] One or more of the
When an error code is shown, w bit data C =
[C ₁ , c ₂ , ..., c _w ], The error code is output. [Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings. In the following explanation, when W = 3, that is, modulo
Three circuits will be described. FIG. 1 shows an embodiment of the present invention.
It is a block diagram of an arithmetic circuit using a path. In FIG. 1, the arithmetic circuit 6000 has two binary data X and Y.
And the respective modulo 3 expected values A and B are input, and binary
The calculation result Z between the data X and Y, and the calculation result Z
Outputs a three-valued C value. The first input register 701 and the second input register 702 are respectively
After inputting and storing the binary data X and Y,
Output binary data X, Y through data path 17,72,
Input the binary data X and Y into the arithmetic circuit 601
X and Y are the first input modulo 3 generation circuit 602 and
And the second input modulo 3 generation circuit 603. The arithmetic circuit 601 receives the binary data X through the data path 71.
Input binary data Y through the data path 72,
The operation is executed between the binary data X and Y, and the operation result Z
To the operation result output register 703 through the data path 61.
Force The calculation result output register 703 plays through the data path 61.
After inputting and storing the calculation result Z, play through the data path 73.
The calculation result Z is output. Calculation result Z is the output of calculation circuit 6000
And the input of the calculation result modulo 3 generation circuit 606
Becomes The first input modulo 3 generation circuit 602 passes through the data path 71.
And input the binary data X, the modulo 3 value is generated.
Generated, output through data path 62, and modulo 3 value
1-input Modulo-3 coincidence circuit 604 is input. The second input modulo 3 generation circuit 603 passes through the data path 72.
And input the binary data Y, the modulo 3 value is generated.
Generated, output through data path 63, modulo 3 value
It is input to the 2-input modulo 3-coincidence circuit 605. The calculation result modulo 3 generation circuit 606 passes through the data path 73.
Then, input the operation result Z and generate its modulo 3 value
Output through data path 66 and calculate modulo 3 value
The result is input to the modulo 3 match circuit 608. The first input modulo 3-coincidence circuit 604 passes through the data path 62.
And input the modulo 3 value of binary data X, and
Input the modulo 3 expected value A of data X, and enter the binary data X
Check whether the modulo 3 value and its expected value A match.
Check, and when they match, modulo 3 of binary data X
Output the value as it is and expect it to be the modulo 3 value of binary data X
When either the value A is [1,1], or binary data
When the expected value A of the modulo 3 value of X does not match,
[1,1] is output, and the output modulo 3-value is the data
The input of the first modulo 3 holding register 704
Become. The second input modulo 3 match circuit 605 is connected to the data path 63.
And input the modulo 3 value of the binary data Y, and
Input the modulo 3 expected value B of data Y, and enter the first input
Performs a match check in the same way as the Euro 3 match circuit 604, and outputs a binary
Data modulo 3 value or [1,1]
Output through the bus 65 and the second modulo 3 holding register 705
And input. The first modulo 3 holding register 704 passes through the data path 64.
Output 1 modulo 3 match circuit 604 output modulo 3 value
Input and store by strobe signal, then data path
Output through 74 and input to modulo 3 arithmetic circuit 607
It However, the storage in this register before strobe signal input
If the holding value is [1,1]), even after the strobe signal is input
[1,1] is held, and this register does not depend on the strobe signal.
The output modulo 3 value of the data remains [1,1] and does not change. The second modulo 3 holding register 705 passes through the data path 65.
The output modulo 3 value of the second input modulo 3 match circuit 605
Input and store by strobe signal, then data path
Output through 75 and another input of modulo 3 arithmetic circuit 607
And However, in this register before strobe signal input
If the holding value of [1,1] is, the first modulo 3 holding register
[1,1] is held as in the case of the starter 704, and the output does not change.
Yes. The modulo 3 arithmetic circuit 607 is a first modulo 3 holding register.
Input the modulo 3 value of the data 704 through the data path 74
And the output mode of the second modulo 3 holding register 705.
Juro 3 values are input through data path 75, and either
When the modulo 3 value of is [1,1], output [1,1] as it is
However, when both are not [1,1], the two modules
B Modulo 3 operation corresponding to the operation circuit 601
Execute and output the result. Modulo 3 arithmetic circuit 607
The output of is the expected value modulo 3 of the operation result Z, and the data
Input of calculation result modulo 3 match circuit 608 through path 67
And The calculation result modulo 3 match circuit 608 passes through the data path 66.
And input the modulo 3 value of the operation result Z,
Input the expected value of modulo 3 of calculation result Z through tapas 67
Then, the first input modulo 3 match circuit 604 and the second input
As with the force modulo 3 match circuit 605, the calculation result Z
Performs a match check between the three-point value and its expected value, and matches
Outputs the modulo 3 value of the operation result Z as it is
If either the modulo 3 value of the operation result Z or the expected value is
When [1,1], or modulo 3 value and period of operation result Z
If the wait values do not match, [1,1] is output and
The modulo 3 value is output modulo 3 through data path 68.
The input to the force register 706. The modulo 3 output register 706 stores the arithmetic result modulo 3
Output modulo 3 value of matching circuit 608 through data path 68
Data path 76 after input and storage by strobe signal
Output through. This output modulo 3-value C is calculated
As one output of the path 6000, a modulo 3 circuit in the subsequent stage (not shown)
It is used for inputting etc.). However, with strobe signal
If the value held in this register before input is [1,1], the first
And the second modulo 3 holding registers 704 and 705,
[1,1] is held and output does not change. In the arithmetic circuit 6000, for example, the first modulo 3 holding level
A failure occurs in the output of the register 704, causing a failure on the data path 74.
When the three-valued value becomes [1,1], it is regarded as the value of modulo-3
And the incorrect value [1,1] passes through the data path 74 and modulo 3
After passing through the calculation circuit 607 and the data path 67, the calculation result module
From the Euro 3 match circuit 608 through the data path 68 to the modulo
3 Output register 706 through data path 76
(B) Three-valued C = [1,1] is output. As a second example, the second input modulo-3 coincidence circuit 605
The binary modulo 3 value of Y and its expected value B
If not, [1,1] will be output through the data path 65.
From the second modulo 3 holding register 705 to the data path 75
Through the modulo 3 arithmetic circuit 607 and the data path 67.
From the calculation result modulo 3 match circuit 608 to the data path 68
Through the modulo 3 output register 706 to the data path 76
To output a modulo three value C = [1,1]. Furthermore, the calculation result Z may differ due to a failure of the calculation circuit 601.
If it is a normal value, the modulo 3 value is
The calculation result is input to the modulo 3 match circuit 608 and the data
A match check with the expected value on path 67 is performed and there is a match.
The value [1,1] when there is no modulo 3 through the data path 68
Modulo 3 from output register 706 through datapath 76
The value C = [1,1] is output. The same is true when the input expected value A = [1,1], and the data
The modulo 3 value on the paths 64,74,67,68,76 is [1,1].
Output modulo 3-value C = [1,1]. As described above, when a failure occurs in the arithmetic circuit 6000,
Or when the input data is invalid, output modulo 3-value C
Is an illegal value [1,1] for the modulo 3 value,
After the output circuit C of the output circuit 6000,
Can be transmitted to the modulo 3 circuit of the stage. In addition, this modulo 3-value C = [1,1]
After being reported, which part of the entire circuit the failure occurred
To know how an illegal modulo 3 value [1,1] is
If you check whether it has propagated, it is easy to find the point of failure.
It's easy. FIG. 2 is a block diagram showing a second embodiment of the present invention.
, Various operational circuits equivalent to the operational circuit 6000 in FIG.
A combined example, modulo 3 circuit according to the invention
Corresponds to the arithmetic circuit in each arithmetic circuit block.
Included in the configuration. In the following explanation, Is a moshulo 3 addition, Is modulo 3 subtraction or inversion, and Indicates modulo 3 multiplication. In FIG. 2, the arithmetic circuit 7000 has six binary numbers X, Y, Z, R,
For S and T inputs, P =-(X + Y + Z-R), Q = (X +
2 binary numbers Y-S-T)-(X + Y + Z-R)
In addition to outputting P and Q, X, Y, Z, and
Input modulo 3 values A, B, C, D, E, F of R, S, T respectively
Then It outputs the two L, M values of the Moshulo 3 which are When the adder circuit 201 inputs binary numbers X and Y, the addition result X + Y
Is generated and output through the data path 1, and the adder circuit 204
And the input of the subtraction circuit 205, and
Juro 3 circuit inputs modulo 3 values A and B of binary numbers X and Y
Then, the modulo 3 expected value of the addition result X + Y is generated and added.
When the result is checked and a failure is detected, [1,1]
Otherwise, the addition result X + Y modulo 3 value Is output through the data path 21 and subtracted by the adder circuit 204
As input to circuit 205. When the subtraction circuit 202 inputs binary numbers Z and R, the subtraction process Z-R
Is generated and output through data path 2, and a binary number
Input modulo 3-values C and D of Z and R, subtraction result Z-R result
Check [1,1] or subtraction result Z-R
Three-value Is output through the data path 22 and is input to the adder circuit 204.
To do. The multiplication circuit 203 receives the binary numbers S and T and outputs the multiplication result S · T.
Generate (= S × T) and output through data path 3
And the modulo three values E and F of binary numbers S and T are input, and the multiplication result
Check the result of S ・ T and check [1,1] or multiplication result.
Fruit S · T modulo 3 value Is output through the data path 23, and the
To do. The adder circuit 204 uses the binary number X + Y through the data path 1.
, Input binary Z-R through data path 2 and add
Generate the result X + Y + Z-R and output through data path 4.
The data path 21 and the binary number X + Y
Juro 3-value Through the data path 22 to the binary Z-R modulo 3-value Enter, and check the result of addition result X + Y + Z-R
And its modulo 3 value Is output through the data path 24. Here again, addition times
If a fault is detected in the path 204, or the adder circuit 204
If [1,1] is entered before input of ( Is [1,1]), Is output through the data path 24 and this output is rotated in reverse 20
6, Input to multiplication circuit 207. The subtraction circuit 205 uses the binary number X + Y through the data path 1.
Input binary number S · T through data path 3 and subtract
Result X + Y-S · T is generated and output through data path 5.
Power and modulo three values through data path 21 Through the data path 23 modulo 3-value Enter, check the subtraction result X + Y−S · T,
Its modulo 3 value Is output through the data path 25 and is input to the multiplication circuit 207.
To do. The modulo 3 value on the data path 25 also precedes it
If a failure has occurred, it is [1,1]. The inverting circuit 206 uses the binary number X + Y + through the data path 4.
If you input Z-R, the inversion result-(X + Y + Z-R)
Generate and output through data path 6 and data
Modulo-3 through pass 24 Enter and check the inversion result- (X + Y + Z-R)
And its modulo 3 value Is output through the data path 26. Model on data path 26
If there is a failure in the Juro 3 value before that
Becomes [1,1]. The multiplication circuit 207 outputs a binary number X + Y + through the data path 4.
Z-R is a binary number X + Y-S · T through the data path 5.
If you enter, the multiplication result (X + Y + Z−R) · (X + Y
-ST) is generated and output through the data path 7.
Both are modulo 3-valued through data path 24 Through the data path 25 modulo 3 values If you enter, the multiplication result (X + Y + Z−R) · (X + Y
-S / T) is checked, and its modulo 3 value Are output through the data path 27. Model on data path 27
If the Juro 3 value also has a failure in the previous stage
Becomes [1,1]. The output P =-(X + Y + Z-R) of the inverting circuit 206 and its output
Juro 3-value , And the output of the multiplication circuit 207 Q = (X + Y + Z−R) ·
(X + Y-S ・ T) and its modulo 3 value Becomes the output of the arithmetic circuit 7000 and is input to the circuit in the subsequent stage.
It Here, for example, when a failure occurs in the multiplication circuit 203,
If the modulo 3 value on data path 23 is [1,1],
This modulo 3-value is passed through the subtraction circuit 205 and the data path 2
5 through the multiplication circuit 207, then through data path 27, M =
It is output as [1,1]. M = [1,1] is invalid data
It is clear that a failure occurred somewhere up to M.
And by tracing the route [1,1]
It is easy to point out that the cause is the multiplication circuit 203.
It As a second example, when input D = [1,1], modulo 3
The invalid data [1,1] of the value passes through the subtraction circuit 202,
Passes through the data path 24 through the adder circuit 204 through the path 22.
And passes through the data path 26 via the inverting circuit 206 and L = [1,1]
Is output as well as the multiplication circuit from the data path 24.
Outputs as M (1, 1) via data path 27 via 207
To be done. L = M = [1,1] is invalid data, and L or
It is clearly stated that a failure has occurred somewhere before reaching M,
And by tracing the route of [1,1], the cause is
The cause is not in the arithmetic circuit 7000, but in the preceding stage.
The cause that M becomes [1,1] is due to the same cause.
It turns out. In the case of the conventional modulo 3 circuit, the consideration for [1,1] is
Since it has not been performed, the above-mentioned failure may occur in the middle of the circuit.
In this case, the values of L and M depend on other inputs and circuit configuration.
Therefore, it is difficult to determine whether the data is invalid and
There may be cases where it is not possible. In addition, when pointing out the failure point
However, because it is difficult to determine the value of incorrect data in the middle,
The resolution is very low. On the other hand, in the case of this embodiment, the invalid data is the value [1,1].
Since it is easy to judge with, the failure detection rate is high.
Are all the values of the path that passed the value of [1,1] are [1,1]?
The fault location causing the value of [1,1].
It is easy to remove and the resolution is high. Also, unlike the conventional modulo 3 circuit, [1,
1] is considered, and the output [1,1] is also logically meaningful
Because it is a value, if it is realized by LSI etc., it is for the logic verification.
However, it is not necessary to make a logically meaningless description of [1,1].
And does not hinder the design efficiency. FIG. 3 is a block diagram showing a third embodiment of the present invention.
, Three modulo-3 registers in the arithmetic circuit 6000 of FIG.
Input 704, 705, 706 to input modulo 3-value or output modulo
(B) When the strobe signal is input when the 3-value is [1,1]
[1] If the strobe signal is input in other states

In this example, modulo 3 registers 504, 505, and 506 are used, each having a function of outputting 1-bit data of [0], and an OR circuit 507 is added. In FIG. 3, the first modulo-3 holding register 504 is
Through the data path 64, the first input modulo 3 match circuit 604
The output modulo 3 value is input, stored by the strobe signal, output through the data path 74, and input to the modulo 3 arithmetic circuit 607. However, if the value held in this register before the strobe signal is input is [1,1], or if the modulo-3 value that is input through the data path 64 is [1,1], the value [1,1] will remain even after the strobe signal is input. 1] is held, the output modulo 3 value of this register remains [1,1] regardless of the strobe signal, it does not change, and error report 1
Bit data l ₁ = 1 is output through the data path 54,
It becomes the input of the logical sum circuit 507. The second modulo 3 holding register 505 inputs the output modulo 3 value of the second modulo 3 coincidence circuit 605 through the data path 65, stores it by the strobe signal, and then stores it in the data path 75.
Is output through and is used as another input of the modulo 3 arithmetic circuit 607. However, when the value held in this register before strobe input is [1,1], or when the input modulo 3 value is [1,1].
In the case of 1], as in the case of the first modulo 3 holding register 504, [1,1] is held and does not change, and 1-bit data l ₂ = 1 of the error report is output through the data path 55, and the OR circuit It becomes another input of 507. The modulo 3 output register 506 inputs the output modulo 3 value of the operation result modulo 3 coincidence circuit 608 through the data path 68, stores it by the strobe signal, and then stores it in the data path.
Output through 76. The output modulo three value C is used as one output of the arithmetic circuit 5000 for input to a modulo three circuit (not shown) in the subsequent stage. However, if the value held in this register before the strobe signal is input is [1,1], or if the input modulo 3 value is [1,1], the first and second
Similar to the modulo 3 holding registers 504 and 505, [1,1]
Is held and does not change, and 1-bit data l ₃ = 1 of the error report is output through the data path 56 and is input to the logical sum circuit 507. When the logical sum circuit 507 inputs l ₁ through the data path 54, l ₂ through the data path 55, and l ₃ through the data path 56, the logical sum circuit 507 generates and outputs a logical sum E of l ₁ , l ₂ and l _3. . l ₁ ,
l ₂ and l ₃ have the values held in their modulo 3 registers as [1,
1], that is, 1-bit data which becomes 1 when a failure is detected, the logical sum E = 1 is calculated by the arithmetic circuit 5000.
It means that the failure is detected in the inside. The other circuits in the arithmetic circuit 5000 are the same as the arithmetic circuit 6000 in FIG. FIG. 4 is a block diagram showing a fourth embodiment of the present invention. In FIG. 4, the arithmetic circuit 4000 has two binary data.
X, Y and the respective modulo 3-values A, B are input, the operation result Z between the binary data X and Y, the modulo 3-value C of a part of the data Z1 of the operation result Z, and the remaining The modulo 3 value D of the data Z2 is output. In this embodiment, the calculation result data Z
The following is an example of a modulo 3 circuit suitable for the case where the latter circuit handles two data of Z1 and Z2 separately. A circuit preceding the circuit for generating modulo three values C and D, that is, the first and second input registers 701 and 702, the arithmetic circuit 6
01, the operation result output register 703, the first and second input modulo 3 generation circuits 602 and 603, the first and second modulo 3 coincidence circuits 604 and 605, and the first and second modulo 3 holding registers 704 and 705, Since it is the same as the arithmetic circuit 6000 of FIG. 1, description thereof will be omitted. The first result modulo 3 generation circuit 401, when a part of the data Z1 of the operation result Z is input through the data path 731, generates the modulo 3 value and outputs it through the data path 41, and the first result modulo 3 coincidence circuit 405. And the second result modulo 3 subtraction circuit 404. The second result modulo 3 generation circuit 402 outputs the remaining data, excluding the data Z1, of the calculation result Z through the data path 732.
When Z2 is input, its modulo 3 value is generated and output through the data path 42, and the second result modulo 3 coincidence circuit 406
And the first result modulo 3 subtraction circuit 403. The modulo 3 arithmetic circuit 607 inputs the output modulo 3 value of the first modulo 3 holding register 704 through the data path 74, and the output modulo 3 value of the second modulo 3 holding register 705 through the data path 75. When the modulo 3 value is [1,1], [1,1] is output as it is. When both are not [1,1], the arithmetic circuit 601 corresponds between the two modulo 3 values. Executes modulo 3 operation and outputs the result. The output of the modulo-3 arithmetic circuit 607 is used as the modulo-3 expected value of the arithmetic result Z through the data path 67 and the first result modulo-3 subtraction circuit 403 and the second result.
The result is another input to the modulo-3 subtraction circuit 404. The first result modulo-3 subtraction circuit 403 inputs the modulo-3 value of a part Z2 of the operation result Z through the data path 42, and inputs the modulo-3 expected value of the operation result Z through the data path 67 to input either modulo-3 When the three values are [1,1], [1,1] is output as it is, and when neither is [1,1], a modulo three value of ZZ2 is generated and output. First
The output of the modulo-3 subtraction circuit 403 becomes the input of the first result modulo-3 coincidence circuit 405 through the data path 43 as the modulo-3 expected value of a part Z1 of the operation result. The second modulo-3 subtraction circuit 404 inputs the modulo-3 value of a part Z1 of the operation result Z through the data path 41, and
When the modulo 3 expected value of the operation result Z is input through the data path 67, [1,1] is output as it is when any modulo 3 value is [1,1], and when both are not [1,1] Generates and outputs the modulo 3 value of Z-Z1. The output of the second modulo-3 subtraction circuit 404 becomes the input of the second result modulo-3 coincidence circuit 406 through the data path 44 as the modulo-3 expected value of a part Z2 of the calculation result. The first result modulo 3 match circuit 405 passes the modulo 3 value of a part Z1 of the operation result Z through the data path 41 to the data path.
When the modulo 3 expected value is input via 43, a match check is executed, and when the modulo 3 expected value of Z1 is output as it is, one of the modulo 3 value of Z1 and the expected value is [1,1 ], Or when the modulo 3 value of Z1 and its expected value do not match, [1,1] is output, and the output modulo 3 value passes through the data path 45 to the first modulo 3
It becomes the input of the output register 407. The second result modulo 3 match circuit 406 passes the modulo 3 value of a part Z2 of the operation result Z through the data path 42 to the data path.
When the expected value is entered through 44, a match check is executed, and if they match, the modulo 3 value of Z2 is output as is, and either the modulo 3 value of Z2 or the expected value is [1,1].
, Or when the modulo 3 value of Z2 and its expected value do not match, [1,1] is output, and the output modulo 3 value is stored in the second modulo 3 output register 408 through the data path 46. It becomes an input. The first modulo-3 output register 407 inputs the output modulo-3 value of the first result modulo-3 coincidence circuit 405 through the data path 45, stores it by the strobe signal, and then outputs it through the data path 47. This output modulo 3-value C is
It is used as one output of the arithmetic circuit 4000 for inputting the modulo 3 circuit in the subsequent stage. However, when the value held in this register before the strobe signal is input is [1,1], [1,1] is held and the output does not change. The second modulo-3 output register 408 inputs the output modulo-3 value of the second result modulo-3 coincidence circuit 406 through the data path 46, stores it by the strobe signal, and then outputs it through the data path 48. This modulo three value D is used as one output of the arithmetic circuit 4000 for input to the modulo three circuit in the subsequent stage. However, when the value held in this register before the strobe signal is input is [1,1], [1,1] is held and
The output does not change. When a failure occurs in the arithmetic circuit 4000, or when the input data is invalid, the output modulo 3 values C and D become an invalid value [1,1] as the value of modulo 3, and the output C of the arithmetic circuit 4000 or The fact that a failure has occurred at the stage before D can be transmitted to the modulo 3 circuit at the rear stage. Also, after a fault has been reported with a modulo 3-value C or D = [1,1], how can the incorrect modulo 3-value [1,1] be used to know in which part of the circuit the fault has occurred? It is the same as the arithmetic circuit 6000 in FIG. 1 in that it is easy to point out the failure point by checking whether it has propagated. FIG. 5 is a truth table showing an example of the modulo 3 arithmetic circuit used in the present invention. (A) is an addition circuit, (b) is a subtraction circuit, (c) is a multiplication circuit, and (d) is an inversion circuit. The truth of modulo 3 addition, modulo 3 subtraction, modulo 3 multiplication, and modulo 3 inversion circuit, respectively. It is a value table. One in the figure indicates an arbitrary value. An example of the adder circuit in (a) will be described. In the check circuit of the adder circuit for obtaining the sum Z of any two binary numbers X and Y, the value of the modulo 3 of the input binary number X is A = [a ₁ ,
a ₂ ], the value of the modulo 3 of the input binary number Y is B = [b ₁ , b ₂ ].
Then, the expected value C = [c ₁ , c ₂ ] as the value of the modulo 3 of the addition result Z of the binary numbers X and Y is prepared. For example, A =
When [0,1], B = [1,0], C = from the truth table in (a)
It becomes [0,0]. The above is the same as the conventional modulo 3 circuit, but the feature of this circuit is that [1,1] is considered as the value of modulo 3. If the binary number X is modulo 3, the value A = [a ₁ , a ₂ ]
If A = [1,1] due to the failure of the circuit that generates the expected value C = [c ₁ ,
c ₂ ] = [1,1]. The same applies to the failure on the binary Y side. That is, there are three cases in which the expected value C becomes [1,1], one in the case of A = [1,1], the other in the case of B = [1,1], and This is the case where C = (1,1] due to a failure of the modulo-3 addition circuit itself, Fig. 6 is a truth table showing an example of the modulo-3 coincidence circuit used in the present invention. Bit data A =
When [a ₁ , a ₂ ] and B = [b ₁ , b ₂ ] are A = B, C = [c ₁ ,
c ₂ ] = [a ₁ , a ₂ ], when A ≠ B and A or B = [1,
In the case of 1], the 2-bit data C for which C = [c ₁ , c ₂ ] = [1,1] is output. FIG. 7 includes a modulo-3 arithmetic circuit 302 configured by the logic shown in the truth table of FIG. 5 and a mosculo-3 coincidence circuit 303 configured by the logic shown in the truth table of FIG. It is a block diagram of a check circuit. For example, two binary data X = [0,1,1,0] and Y = [0,1,
0,1], the sum of X and Y Z = X + Y = [1,0,
In the case of the check circuit of the adder circuit that outputs [1, 1], the modulo-3 arithmetic circuit 302 determines the modulo-3 value A = of the binary data X.
[A ₁ , a ₂ ] = [0,0] and the modulo 3 value of binary data Y B =
Input [b ₁ , b ₂ ] ＝ [1,0] and add modulo 3 of A and B Is generated as a modulo 3 expected value, and is input to the modulo 3 coincidence circuit 303 through the data path 32. When the binary number Z, which is the sum of binary data X and Y, is input, the modulo 3 generation circuit 301 receives the modulo 3 value D = [d ₁ , d of the binary number Z.
₂ ] = [1,0] is generated and is used as another input of the modulo 3 coincidence circuit 303 through the data path 31. When the modulo 3 coincidence circuit 303 inputs the modulo 3 value D of the binary number Z through the data path 31 and the expected value C through the data path 32, when D = C, M = [m ₁ , m ₂ ] =
2-bit data M such that M = [m ₁ , m ₂ ] = [1,1] when [d ₁ , d ₂ ], D ≠ C and when D or C = [1,1]
Is output. Here, if a failure occurs in the modulo 3 generation circuit 301 and D =
When it becomes [1,1], input A of modulo 3 arithmetic circuit 302
Or when B = [1,1], modulo 3 arithmetic circuit 3
When a failure occurs in 02 and C = [1,1], and when a failure occurs in the modulo-3 coincidence circuit 303 itself and M = [1,1], the arithmetic circuit unit or the modulo-3 operation is performed. When a failure occurs in the circuit 302 and D ≠ C, the output becomes M = [1,1] in any of the cases, and it is detected that the failure occurs in the circuit before the output M, and the failure is indicated. Modulo 3 value [1,
1] will be output to the check circuit in the subsequent stage. In the check circuit in the subsequent stage, when a value other than [1,1] is input, it is possible to determine that a failure has been detected when the data is normal [1,1]. FIG. 8 is (a) a truth table and (b) a block diagram showing an example of a modulo 3 register used in the present invention. In FIG. 8, the modulo 3 register 501 receives 2-bit data D = [d ₁ , d ₂ ] and strobe signal STB as inputs,
(A) 2-bit data E with the logical configuration shown in the truth table
= [E ₁ , e ₂ ] is output. For example, when the strobe signal is input with D = [0,1] when the output E = [1,0] before strobe input, the output E changes from [1,0] to [0,1]. . Similarly, when a strobe signal is input with D = [0,0] in this state, the output E changes from [0,1] to [0,0]. However, when the original state of the output E is [1,1], the state of [1,1] is maintained regardless of the value of D. Therefore, D ＝
The output E after strobe input in the case of [1,1] or E = [1,1] is fixed to [1,1], and the original modulo 3 value [1,1] is invalid data. It means that the failure of the circuit before this circuit is detected. If an error report signal is generated from the illegal data [1,1] of this circuit, this circuit also serves as an error display flag. FIG. 9 shows an example of a modulo 3 register in which a function of outputting bit data f that can be used for error reporting is added to the modulo 3 register 501 of FIG. 8 (a) truth table and (b) It is a block diagram. In FIG. 9, the modulo 3 register 502 receives 2-bit data D = [d ₁ , d ₂ ] and strobe signal STB as inputs,
(A) 2-bit data E with the logical configuration shown in the truth table
= [E ₁ , e ₂ ] and 1-bit data f are output. The 1-bit data f becomes 1 when the strobe signal is input with the input D = [1,1], and then the output E = [1,1].
At the same time, the state of f = 1 will be maintained. Since the 1-bit data f = 1 means that the illegal data [1,1] is input, it can be used as it is as an error report signal. The other operations are the same as those of the modulo 3 register 501 described with reference to FIG. In addition, in the above-mentioned embodiment, although the moshulo 3 circuit is described, the present invention is not limited to this, and modulo W (=
Of course, the same can be applied to the 2 ^W -1) circuit. [Effects of the Invention] As described above, the present invention considers an incorrect error code as the value of modulo W, and sets the error code as the value of modulo W at the time of detecting a failure, so that the error code of the check circuit itself is A failure can be detected and the failure detection of the previous stage can be transmitted to the check circuit of the subsequent stage. Furthermore, by following the error code transmission path, it is easy to identify the failure location, so there is the effect that the failure detection rate and resolution of the entire check circuit can be improved, and that a configuration suitable for LSI implementation can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an arithmetic circuit using a modulo 3 circuit of the present invention, and FIG. 2 is an example of an arithmetic circuit using a plurality of various arithmetic circuits equivalent to the arithmetic circuit of FIG. FIG. 3 is a block diagram showing an example of an arithmetic circuit in which a function is added to the first embodiment shown in FIG. 1, and FIG. 4 is a fourth embodiment applying the first embodiment shown in FIG. FIG. 5 is a truth table showing an example of a modulo 3 arithmetic circuit used in the present invention, and FIG. 6 is a truth value showing an example of a modulo 3 coincidence circuit used in the present invention. Table and FIG. 7 are modulo 3 of the logic configuration shown in the truth table of FIG. 5 and modulo 3 of the logic configuration shown in the truth table of FIG.
A block diagram showing an example of a check circuit including a matching circuit,
FIG. 8 is a truth table and a block diagram showing an example of a modulo 3 register used in the present invention, and FIG. 9 is a truth table showing an example of a modulo 3 register in which a function is added to the modulo 3 register of FIG. And a block diagram, FIG. 10 is a block diagram showing an example of a modulo 3 circuit conventionally used, and FIG. 11 is a part of an arithmetic circuit in an arithmetic unit, and an example of a modulo 3 circuit for an intermediate result thereof. It is a block diagram shown. 602,603,606,401,402,301 …… Modulo 3 generation circuit, 604,
605,608,405,406,303 ... Modulo 3 matching circuit, 704,705,
706, 504, 505, 506, 407, 408, 501, 502 ... Modulo 3 register, 607, 302 ... Modulo 3 arithmetic circuit, 701, 702 ... Input register, 601 ... Arithmetic circuit, 201, 204 ... Addition circuit, 202, 2
05 …… Subtraction circuit, 203, 207 …… Multiplication circuit, 206 …… Inversion circuit, 507 …… OR circuit, 703 …… Operation result output register, 4
000, 5000, 6000, 7000 ... Arithmetic circuit, 403, 404 ... Modulo-3 subtraction circuit.

Claims (1)

[Claims] 1. A modulo W circuit having a w-bit input and a w-bit output, wherein all 2 ^w of binary values represented by w bits (w ≧ 2) are “. 1 "
One of the W (= 2 ^w -1) binary values except for is defined as an error code indicating that a failure has been detected, and the remaining W (= all the bits include "1" (= 2 ^w -1)
A binary value is defined as W modulo W codes, and when a fault occurs or a fault is detected and an error code is generated, the error code is propagated. And n pieces of w-bit data A ₁ = [a _{11 ,,} a ₁₂ ..., a _1w ], A ₂ = [a ₂₁ , a ₂₂ ..., a _2w ],
_,, A _n = [a _n1 , a _n2 , ..., a _nw ] When at least one of the inputs indicates the error code, w bit data C
A modulo W circuit which outputs the error code as = [c ₁ , c ₂ , ..., C _w ].