JPH0543242U - Interrupt request circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object to provide an interrupt request circuit having a high reliability and a simple circuit configuration without the influence of metastable. [Structure] An interrupt request flip-flop for storing a plurality of interrupt requests prepared corresponding to the number of interrupt request inputs, and an interrupt factor read commanded by an output signal of the interrupt request flip-flop from the main system. An interrupt factor flip-flop circuit that is latched by a signal, an interrupt factor output buffer that outputs this output signal to the main system data bus by the interrupt factor read signal, and an output signal of the interrupt factor flip-flop circuit. And an interrupt factor reset signal as an input to reset the corresponding interrupt request flip-flop, an OR gate circuit for ORing the output signals of the interrupt request flip-flops, and the output of this OR gate circuit Signal and an interrupt factor reset signal are input, and an AND request that outputs an interrupt request signal to the above main system And a road.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an interrupt request circuit for allocating a plurality of interrupt request inputs to one interrupt request signal to a main system in a computer control system.

[0002]

[Prior Art]

 FIG. 3 is a diagram showing a conventional interrupt request circuit shown in, for example, Japanese Patent Publication No. 62-46017. In the figure, 1a to 1n are interrupt input signals in which a high signal (hereinafter abbreviated as "H") is significant, and 2a to 2n are interrupt request flip-flops, which outputs are input to input terminals D1 to Dn. An interrupt factor transparent latch that latches a low signal (hereinafter abbreviated as "L") with a significant interrupt factor read signal 4 and also outputs the latch interrupt factor from output terminals Q1 to Qn. It is input to the circuit 3. The output of the interrupt factor transparent latch circuit 3 becomes the input of each reset NAND gate 6a to 6n together with the inverted read signal obtained by inverting the interrupt factor read signal 4 by the inverter 5, and its output is the interrupt request flip-flop. Input to the reset terminals of 2a to 2n. 7 takes the logical sum of the outputs of the interrupt request flip-flops 2a to 2n, the output of which is input to the AND gate 8 together with the interrupt factor read signal 4 and the output of which is "H" to the main system (not shown). “Significant interrupt request signal 9 is given. Reference numeral 10 is an "H" significant interrupt factor output buffer which is controlled by the interrupt factor read signal 4 and outputs the output of the interrupt factor transparent latch circuit 3 as an interrupt factor signal 11 to the data bus.

Next, the operation will be described. It is assumed that all interrupt request flip-flops 2a to 2n are reset at the time of initial setting. First, when the interrupt input signal 1a becomes significant in the "H" state, it is stored in the interrupt request flip-flop 2a, and its output Q becomes the "H" state. When the output Q of at least one interrupt request flip-flop, for example, the interrupt request flip-flop 2a, of the plurality of interrupt request flip-flops 2a to 2n becomes the "H" state, the output of the OR gate circuit 7 becomes " It becomes the H "state. At this time, if the interrupt factor read signal 4 is in the "H" state and is insignificant, wait immediately, and if the interrupt factor read signal 4 is in the "L" state and significant, wait for the "H" state to be insignificant. Then, the interrupt request signal 9 to the central processing unit (hereinafter abbreviated as CPU) of the main system (not shown) is made significant in the “H” state, and the corresponding output Q of the interrupt factor transparent latch circuit 3 is set. It is significant in the "H" state. When this CPU accepts the interrupt request signal 9 and makes the interrupt factor read signal 4 significant in the “L” state to read the interrupt factor, the interrupt request signal 9 is output. As a result, the interrupt factor transparent latch circuit 3 latches the interrupt factor that has been input so far, and interrupt request flips 2a to 2n for significant interrupt factors in the latched "H" state. To reset. Also, the latched interrupt factor signal 11 is passed from the interrupt factor output buffer 10 to the CPU via the data bus. Then, the interrupt request signal 9 corresponding to the interrupt input signals 1a to 1n generated while the interrupt factor read signal 4 is in the "L" state is "H" when the interrupt factor read signal 4 becomes insignificant. It becomes a state and becomes significant again. In general, the CPU's interrupt request signal detects a change edge to a significant level, so this operation causes the CPU to accept the interrupt. In this way, a plurality of interrupt inputs are processed only by the interrupt request signal 9 to one main system.

[0004]

[Problems to be solved by the device]

 Since the conventional interrupt request circuit is configured as described above, the interrupt request signal 9 to the CPU is generated because the interrupt input signal 1a becomes significant in the "H" state as shown in FIG. It becomes significant, and when another interrupt input signal 1b becomes significant in the "H" state almost at the same time when the CPU sets the interrupt factor read signal 4 to the "L" state to read the interrupt factor. The setup time of the interrupt factor transparent latch 3 is not satisfied with the output signal of the interrupt request flip-flop 1b, and the output Q2 of the interrupt factor transparent latch 3 becomes a metastable state. In general, the metastable state ends in a time shorter than the CPU read time. Therefore, in this state, the output Q2 becomes indefinite for a short time, and the interrupt request flip-flop 1b is reset, but the interrupt factor read by the CPU is not interrupted. This is a phenomenon that does not include the factor of the input signal 1b. That is, there is a problem that the factor of the interrupt input signal 1b is not processed by the CPU.

The present invention has been made in order to solve the above problems, and has a circuit configuration of the same scale as the conventional one, and has a high reliability that does not affect the system operation even if metastable occurs. It is an object of the present invention to provide an interrupt request circuit.

[0006]

[Means for Solving the Problems]

 One of the interrupt request circuits according to the present invention is an interrupt request command from the main system that outputs an output signal of an interrupt request flip-flop that stores a plurality of interrupt requests prepared corresponding to the number of interrupt request inputs. An interrupt factor flip-flop circuit that latches with a factor read signal, and an interrupt factor output buffer that outputs the output signal of this interrupt factor flip-flop circuit to the main system data bus by the interrupt factor read signal. Further, an AND gate circuit that inputs the output signal of the interrupt factor flip-flop circuit and the interrupt factor reset signal and resets the corresponding interrupt request flip-flop, and the logical sum of the interrupt request flip-flop output signals. Of the OR gate circuit, and the output signal of the OR gate circuit and the reset signal of the interrupt factor as input, An AND circuit for outputting an interrupt request signal to Temu, is provided with a means for performing in Bulk the interrupt factor reset signal to reset the interrupt request flip-flop from the CPU. Another of the interrupt request circuits according to the present invention is an interrupt request flip-flop that stores a plurality of interrupt requests corresponding to the number of interrupt request inputs, and outputs an output signal of an interrupt request flip-flop commanded from the main system. An interrupt factor flip-flop circuit that is latched by an interrupt factor read signal, and an interrupt factor output buffer that outputs the output signal of this interrupt factor flip-flop circuit to the main system data bus by the above interrupt factor read signal. And an OR gate circuit that takes the logical sum of each interrupt factor flip-flop output signal as a reset signal of the corresponding interrupt request flip-flop, and the OR gate circuit. An AND circuit that receives the circuit output signal and the multiple interrupt detection signal and outputs an interrupt request signal to the main system is provided. It is provided with a means for detecting a unit and multiple interrupts be made individually by reset signal for each interrupt factor of the reset flop from the CPU.

[0007]

[Action]

 The interrupt request circuit according to the present invention resets the interrupt request flip-flop by an interrupt factor reset signal that is independent of the interrupt factor read signal, and even if the metastable of the interrupt factor flip-flop occurs. The factor does not disappear, and the interrupt input that caused the metastable at the next interrupt request is surely transmitted to the CPU.

[0008]

【Example】

 Example 1. A first embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. 3 are designated by the same reference numerals, and reference numeral 20 designates the output signals of the interrupt request flip-flops 2a to 2n to the input terminals D1 to Dn and the interrupt factor read signal. 4 is an interrupt factor flip-flop that latches 4 with an inverted signal in the inverter circuit 21 and outputs the latched interrupt factor from the output terminals Q1 to Qn. Reference numeral 22 is an interrupt request AND gate which receives the output of the OR gate circuit 7 and the interrupt factor reset signal 23 which becomes significant in the "L" state and outputs the interrupt request signal 9. The outputs 24a to 24n receive the outputs Q1 to Qn of the interrupt factor flip-flop 20 and a signal obtained by inverting the interrupt factor reset signal 23 which is significant in the "L" state by the inverter circuit 25, and interrupt its output. It is a NAND gate circuit which is used as a reset signal for the input request flip-flops 2a to 2n.

Next, the operation will be described. First, it is assumed that all the interrupt request flip-flops 2a to 2n are reset at the initial setting. First, when the interrupt input signal 1a becomes significant in the "H" state, it is stored in the interrupt request flip-flop 2a, and its output Q becomes the "H" state. When the output Q of at least one interrupt request flip-flop, for example, the interrupt request flip-flop 2a, of the plurality of interrupt request flip-flops 2a to 2n becomes the "H" state, the output of the OR gate circuit 7 becomes " It becomes the H "state. At this time, if the interrupt factor reset signal 23 is in the "H" state and it is insignificant, immediately, and if the interrupt factor reset signal 23 is in the "L" state and significant, wait for the "H" state to be insignificant. Then, the interrupt request signal 9 to the CPU (not shown) is made significant in the "H" state. When the CPU accepts the interrupt request signal 9 and makes the interrupt factor read signal 4 significant in the “L” state in order to perform the interrupt process, the interrupt factor read signal 4 falls, and the interrupt factor read signal 4 falls. The interrupt factor flip-flop circuit 20 latches each output signal of the interrupt request flip-flops 2a to 2n and makes the corresponding output Q significant in the "H" state. Further, the latched interrupt factor signal 11 is passed from the interrupt factor output buffer 10 to the CPU via the data bus. When the CPU completes the processing for the read interrupt factor, it makes the interrupt factor reset signal 23 significant in the "L" state, and the interrupt request flip-flops 2a to 2a corresponding to the significant interrupt factor when the CPU read. Only 2n are reset. If the CPU makes the interrupt factor read signal 4 significant in the “L” state and the interrupt factor reset signal 23 is made significant in the “L” state due to the completion of the interrupt processing, there is an interrupt factor newly generated. When the interrupt factor reset signal 23 becomes insignificant, the interrupt request signal 9 becomes "H" state again and becomes significant (that is, an edge changing to a significant level occurs).

Example 2. In the first embodiment described above, the interrupt request flip-flops 2a to 2n corresponding to the interrupt factors that were significant when the CPU read the interrupt factors by the interrupt factor reset signal 23 are collectively reset. However, as shown in FIG. 2, by the interrupt factor reset signals 26a to 26n which become significant in the "L" state for each interrupt factor, the CPU causes the interrupt factor reset signals 26a to 26n for the interrupt factor. Only in the "L" state, the interrupt request flip-flops 2a to 2n are individually reset, and the multiple interrupt detection signal 27 and the Q signal of each of the interrupt request flip-flops 2a to 2n are significant in the "L" state. The AND gate circuit 28 which receives the output signal of the OR gate circuit 7 which takes the logical sum of the above and uses the output as the interrupt request signal 9 to the CPU, and the CPU individually resets the interrupt request flip-flops 2a to 2n. Shi After that, the multiple interrupt detection signal 27 is set to "L" in order to generate an interrupt request to the CPU due to a factor that becomes significant during the interrupt process or an interrupt factor that has not been processed by the interrupt process. If the status is significant and there is a factor that has become significant during the interrupt process or an interrupt factor that has not been processed in the interrupt process, the interrupt request signal 9 is temporarily changed by the action of the multiple interrupt detection signal 27. When the "L" state becomes insignificant and the multiple interrupt detection signal 27 returns to the "H" state insignificantly, the "H" state becomes significant again. That is, an edge occurs in the interrupt request to the CPU. In FIG. 2, the same parts as those in FIG. 3 are designated by the same reference numerals. Further, in the second embodiment, the circuit for latching the interrupt factor is constituted by the flip-flop, but even if the circuit is constituted by the transparent latch and the inverter circuit 21 is removed, the same effect as in the second embodiment can be obtained.

[0011]

[Effect of the device]

 As described above, according to the present invention, after the interrupt factor read, the interrupt factor reset is performed after the metastable time has sufficiently set, so that the interrupt factor read is started. Even if a metastable occurs in the factor flip-flop circuit, only the interrupt request flip-flop is not reset for the interrupt factor that the CPU does not recognize, and a highly reliable interrupt request circuit can be obtained. Be done. According to the invention of claim 2, in addition to the above effect, the means for resetting the interrupt factor and the method for detecting multiple interrupts are separated, so that all the interrupt factors that are significant when the interrupt factor is read. There is no need to perform it in one interrupt process, only one cause is processed in one interrupt, and multiple interrupt detection is performed at the end of the process until the processing for all interrupt factors is completed. Since the interrupts to the CPU are automatically generated repeatedly, the structure of the interrupt processing program can be simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an interrupt request circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an interrupt request circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional interrupt request circuit.

FIG. 4 is a time chart showing a problem of a conventional interrupt request circuit.

[Explanation of symbols]

 1a to 1n Interrupt request input signal 2a to 2n Interrupt request flip-flop 4 Interrupt factor read signal 7 OR gate circuit 9 Interrupt request signal 10 Interrupt factor output buffer 11 Interrupt factor signal 20 Interrupt factor flip-flop 24 Reset NAND gate circuits 26a to 26n Reset signal for each interrupt factor 27 Multiple interrupt detection signal 28 AND gate circuit for multiple interrupt detection

Claims (2)

[Scope of utility model registration request] 1. An interrupt request flip-flop for storing a plurality of interrupt requests prepared corresponding to the number of interrupt request inputs.
The interrupt factor flip-flop circuit that latches the output signal of this interrupt request flip-flop by the interrupt factor read signal instructed from the main system, and the output signal of this interrupt factor flip-flop circuit by the above interrupt factor read signal. An interrupt factor output buffer which outputs to the data bus of the main system, and an AND which inputs the output signal of the interrupt factor flip-flop circuit and the interrupt factor reset signal and resets the corresponding interrupt request flip-flop A gate circuit, an OR gate circuit for ORing the output signals of the interrupt request flip-flops, and
An interrupt request circuit comprising an AND circuit which receives an R gate circuit output signal and the interrupt factor reset signal and outputs an interrupt request signal to the main system. 2. An interrupt request flip-flop for storing a plurality of interrupt requests prepared corresponding to the number of interrupt request inputs,
The interrupt factor flip-flop circuit that latches the output signal of this interrupt request flip-flop by the interrupt factor read signal instructed from the main system, and the output signal of this interrupt factor flip-flop circuit by the above interrupt factor read signal. , An interrupt factor output buffer for outputting to the data bus of the main system, and a reset signal for each interrupt factor as a reset signal of the corresponding interrupt request flip-flop, and further, each interrupt factor flip-flop output signal An interrupt request circuit comprising an OR gate circuit that takes the logical sum of the above and an AND circuit that receives the output signal of the OR gate circuit and the multiple interrupt detection signal and outputs an interrupt request signal to the main system.