JPH054632U - Level conversion circuit - Google Patents

Abstract

(57) [Summary] [Objective] The ECL type IC, which is a load, operates stably even if the input impedance is small, and the current consumption of the circuit itself is also small. [Constitution] When the output signal of the CMOS type IC1 is at a high (H) level, the diode 2 is reverse biased, and the resistor 3,
Since the voltage at the connection points of the resistors 4 and 5 of the voltage dividing circuit composed of 4 and 5 is a positive voltage with respect to the ground, an H level signal is supplied to the ECL type IC 7 of the load via the transistor 6.
Further, when the output signal of the IC 1 becomes low (L) level, the diode 2 becomes conductive and the voltage at the connection point of the resistors 4 and 5 becomes a negative voltage with respect to the ground, so that the voltage of the L level via the transistor 6 becomes low. The signal is supplied to IC7. The transistor 6 connected to the emitter follower can reduce the output impedance and the power consumption of the voltage dividing circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit for converting a CMOS level signal into an ECL level signal.

[0002]

[Prior Art]

 This type of level conversion circuit converts the level, polarity, etc. of the output signal of the CMOS type IC in order to input it to the ECL type IC, and the circuit shown in FIG. 2 is generally used. FIG. 2 is a circuit diagram showing a conventional circuit.

When the output signal of the CMOS type IC 1 is at a high (H) level, the diode 2 becomes a reverse bias and is in a non-conducting state. Therefore, the voltage dividing circuit including the resistors 3, 4 and 5 is a positive voltage source. a and the negative voltage source b are added. At this time, the voltage at the connection point between the resistors 4 and 5 becomes a positive voltage with respect to the earth, so that an H level signal is supplied to the ECL type IC 7.

When the output signal of the CMOS IC 1 becomes low (L) level, the diode 2 becomes conductive, and the voltage on the anode side of the diode 2 becomes only the forward voltage of the diode 2 with respect to the ground. This voltage and the voltage of the negative voltage source b are applied to both ends of the resistors 4 and 5, and the voltage at the connection point of the resistors 4 and 5 at this time is a negative voltage with respect to the ground, so that the L level signal is ECL. It is supplied to the mold IC7.

[0005]

[Problems to be solved by the device]

 As described above, in the conventional example, since the level conversion is performed by the voltage dividing circuit by the resistor, if the input impedance of the load IC is lower than the resistance value of this resistor, the level conversion is not completely performed. The operation becomes defective. Also, if the resistance value of this resistor is reduced and the impedance is lowered, the operation will not be a problem, but there is the problem that the current consumption will increase.

[0006]

[Means for Solving the Problems]

 The level converter of the present invention comprises a diode having an anode connected to the output of a CMOS type IC, a first resistor having one end connected to the cathode of the diode and the other end connected to a positive voltage source, A second resistor having one end connected to a connection point between the diode and the first resistor, one end connected to the other end of the second resistor and the other end connected to a negative voltage source. A third resistor, and a transistor having a base connected to a connection point between the second resistor and the third resistor, a collector grounded, and an emitter connected to an input of an ECL type IC. ..

[0007]

【Example】

 Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the circuit of this embodiment. When the output signal of the CMOS type IC1 is at H level, the diode 2 is reverse biased and becomes non-conducting state. And join. At this time, the voltage at the connection point between the resistors 4 and 5 becomes a positive voltage with respect to the ground, so that an H-level signal is supplied to the ECL type IC 7 of the load via the transistor 6. When the output signal of the CMOS type IC1 becomes L level, the diode 2 becomes conductive, and the voltage on the anode side of the diode 2 becomes only the forward voltage of the diode 2 with respect to the ground. This voltage and the voltage of the negative voltage source b 1 are applied to both ends of the resistors 4 and 5. At this time, the voltage at the connection point between the resistors 4 and 5 becomes a negative voltage with respect to the ground, and an L level signal is supplied to the ECL type IC 7 via the transistor 6.

As described above, since the circuit is provided with the transistor 6 connected to the emitter follower on the output side, the load impedance seen from the voltage dividing circuit by the resistors 3, 4 and 5 is increased. Therefore, even if the actual load impedance (input impedance of the ECL type IC7) is small, it operates stably. In other words, the output impedance of this circuit became smaller. It is also possible to reduce the resistance value of the resistors 3, 4, 5 of the voltage dividing circuit to reduce the current consumption.

[0009]

[Effect of the device]

 As described above, since the present invention includes the transistor of the emitter follower connection on the output side, the output impedance is small, the ECL type IC as a load operates stably even if the input impedance is small, and the current consumption is small. There is also an effect that can be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit of this embodiment.

FIG. 2 is a circuit diagram showing a circuit of a conventional example.

[Explanation of symbols]

 1 CMOS type IC 2 Diode 3, 4, 5 Resistor 6 Transistor 7 ECL type IC

Claims (1)

Claims for utility model registration: 1. A diode having an anode connected to the output of a CMOS IC, and a first resistor having one end connected to the cathode of the diode and the other end connected to a positive voltage source. And a second resistor having one end connected to a connection point between the diode and the first resistor, one end connected to the other end of the second resistor and the other end used as a negative voltage source. A third resistor connected thereto, and a transistor having a base connected to a connection point between the second resistor and the third resistor, a collector grounded, and an emitter connected to an input of an ECL type IC. A level conversion circuit comprising.