JPH0547762A - Method of forming aluminum based wiring - Google Patents
Method of forming aluminum based wiringInfo
- Publication number
- JPH0547762A JPH0547762A JP20182391A JP20182391A JPH0547762A JP H0547762 A JPH0547762 A JP H0547762A JP 20182391 A JP20182391 A JP 20182391A JP 20182391 A JP20182391 A JP 20182391A JP H0547762 A JPH0547762 A JP H0547762A
- Authority
- JP
- Japan
- Prior art keywords
- based wiring
- film
- substrate
- wiring film
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title 1
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 18
- 238000009826 distribution Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 28
- 238000013508 migration Methods 0.000 abstract description 11
- 230000005012 migration Effects 0.000 abstract description 11
- 238000001312 dry etching Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 34
- 239000011800 void material Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路装置を形成す
るＡｌ又はＡｌ合金系配線の製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing Al or Al alloy-based wiring for forming an integrated circuit device.
【０００２】[0002]
【従来の技術】従来のＡｌ又はＡｌ合金系配線膜は、半
導体素子を形成した基板を加熱し、電子ビームでＡｌ又
はＡｌ合金系固体ソースを溶融し、蒸発したＡｌ又はＡ
ｌ合金系原子を基板上に堆積する方法や、Ａｒイオンを
Ａｌ又はＡｌ合金のターゲットの表面に衝突させ、Ａｌ
又はＡｌ合金のターゲットよりＡｌ又はＡｌ合金の原子
を叩き出して、基板上にＡｌ又はＡｌ合金の原子を堆積
させる方法により形成されていた。堆積するときの基板
の温度は、Ａｌ又はＡｌ合金系配線膜の平坦性の向上や
結晶粒径を大きくさせるため、２００℃前後で堆積され
る。2. Description of the Related Art A conventional Al or Al alloy-based wiring film is formed by heating a substrate on which a semiconductor element is formed, melting an Al or Al alloy-based solid source with an electron beam, and evaporating Al or A.
Al alloy-based atoms are deposited on a substrate, or Ar ions are made to collide with the surface of an Al or Al alloy target,
Alternatively, it is formed by a method of tapping Al or Al alloy atoms from a target of Al alloy and depositing Al or Al alloy atoms on the substrate. The temperature of the substrate during the deposition is around 200 ° C. in order to improve the flatness of the Al or Al alloy-based wiring film and increase the crystal grain size.
【０００３】[0003]
【発明が解決しようとする課題】しかし、従来の方法で
形成されたＡｌ又はＡｌ合金系配線膜においては、スト
レスマイグレーション耐性やエレクトロマイグレーショ
ン耐性が十分でないという問題があった。However, the Al or Al alloy type wiring film formed by the conventional method has a problem that the stress migration resistance and the electromigration resistance are not sufficient.
【０００４】本発明の目的は、このような従来のＡｌ又
はＡｌ合金系配線における問題点を解決し、ボイドの成
長を抑制してストレスマイグレーション耐性やエレクト
ロマイグレーション耐性に優れたＡｌ又はＡｌ合金系配
線膜の製造方法を提供することにある。An object of the present invention is to solve the problems in the conventional Al or Al alloy-based wiring, and suppress the growth of voids to have excellent stress migration resistance and electromigration resistance. It is to provide a method for manufacturing a membrane.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明によるＡｌ系配線の形成方法においては、Ａ
ｌ＜１１１＞が法線方向にピークを持つ分布を示すＡｌ
又はＡｌ合金系の連続膜を形成後、２００℃以上でＡｌ
系配線膜を形成するものである。In order to achieve the above object, in the method of forming an Al-based wiring according to the present invention,
Al showing a distribution in which l <111> has a peak in the normal direction
Or after forming a continuous film of Al alloy system, Al at 200 ℃ or more
A system wiring film is formed.
【０００６】[0006]
【作用】ストレスマイグレーションによって生じたボイ
ド（楔型ボイド又はスリット型ボイド）がＡｌ系配線の
信頼性を低下させており、このボイドの形成を防ぐこと
が重要となっている。ボイドの形成とＡｌの配向性には
密接な関係があると報告されている。The void (wedge type void or slit type void) generated by stress migration reduces the reliability of the Al-based wiring, and it is important to prevent the formation of the void. It is reported that there is a close relationship between the formation of voids and the orientation of Al.
【０００７】スリット型ボイド形成により新たに発生し
た断線面をＴＥＭで観察した結果、｛１１１｝で構成さ
れていることが報告された。酸化膜上ではＡｌは強い＜
１１１＞配向することが知られているが、断線部でＡｌ
が＜１１１＞に配向すると、法線方向のＡｌ＜１１１＞
は、法線方向から２０度程度傾くことになる。[0007] As a result of TEM observation of a disconnection surface newly generated by the slit type void formation, it was reported that it was composed of {111}. Al is strong on the oxide film
111> orientation is known, but Al
Is oriented to <111>, Al <111> in the normal direction
Is inclined by about 20 degrees from the normal direction.
【０００８】また楔型ボイドが発生した結晶粒の基板法
線方向のＡｌの配向をＴＥＭで観察した結果において
も、法線方向にはＡｌ＜１１１＞から１０〜１５度傾い
た（２３３），（１２２）が観測されている。The TEM observation of the orientation of Al in the direction normal to the substrate of the crystal grains in which wedge-shaped voids were generated also showed a tilt of 10 to 15 degrees from Al <111> in the direction normal (233). (122) is observed.
【０００９】このようにＡｌ配線にボイドが発生する場
合、Ａｌ＜１１１＞が基板法線方向から傾くことが伴っ
ている。このことからストレスマイグレーションにおけ
るボイドの発生を防ぐためには、Ａｌ＜１１１＞が基板
法線方向から傾けないで法線方向に配向することが必要
である。When a void is generated in the Al wiring as described above, Al <111> is inclined with respect to the substrate normal direction. From this, in order to prevent the occurrence of voids in stress migration, it is necessary that Al <111> be oriented in the normal direction without tilting from the substrate normal direction.
【００１０】Ａｌ又はＡｌ合金系配線膜は、堆積すると
きの基板温度によって配向性が変化する。基板温度を１
８０℃以上でＡｌ又はＡｌ合金系配線膜を形成すると、
Ａｌ＜１１１＞が基板法線方向から±４〜５度傾いて軸
対称的な分布を示す。The orientation of the Al or Al alloy-based wiring film changes depending on the substrate temperature during deposition. Substrate temperature is 1
When an Al or Al alloy-based wiring film is formed at 80 ° C or higher,
Al <111> shows an axially symmetrical distribution with an inclination of ± 4 to 5 degrees from the substrate normal direction.
【００１１】これに対し、基板温度が１８０℃以下では
Ａｌ＜１１１＞は、基板法線方向にピークを持つ分布を
示し、ストレスマイグレーション耐性が向上する。しか
し、結晶粒径が１μｍ以下と小さいためエレクトロマイ
グレーション耐性が劣化することが予想された。そこで
Ａｌ＜１１１＞が基板法線にピークを持つ分布を示した
まま結晶粒径を大きくすればストレスマイグレーション
及びエレクトロマイグレーション耐性が向上する。On the other hand, when the substrate temperature is 180 ° C. or lower, Al <111> exhibits a distribution having a peak in the substrate normal direction, and the stress migration resistance is improved. However, it was expected that the electromigration resistance would deteriorate because the crystal grain size was as small as 1 μm or less. Therefore, if the crystal grain size is increased while Al <111> shows a distribution having a peak at the substrate normal line, resistance to stress migration and electromigration is improved.
【００１２】その方法として、Ａｌ＜１１１＞が法線方
向にピークを持つ分布を示すＡｌ又はＡｌ合金系の連続
膜を形成後、基板温度２００℃以上でＡｌ又はＡｌ合金
系配線膜を形成すると、Ａｌ＜１１１＞は基板法線方向
にピークを持つ分布となり、結晶粒径も３〜４μｍの大
きさになる。As a method therefor, after forming an Al or Al alloy-based continuous film in which Al <111> has a distribution having a peak in the normal direction, an Al or Al alloy-based wiring film is formed at a substrate temperature of 200 ° C. or higher. , Al <111> has a distribution having a peak in the substrate normal direction, and the crystal grain size is also 3 to 4 μm.
【００１３】ストレスマイグレーションの高温モード
（３００℃以上で起こる）が原因で発生する楔型ボイド
は、Ａｌとカバー膜の境界で生じ、結晶粒界に沿ってＡ
ｌ原子が拡散し、ボイドの成長が起こる。Wedge-shaped voids caused by the high temperature mode of stress migration (which occurs at 300 ° C. or higher) are generated at the boundary between Al and the cover film, and A along the grain boundary
l atoms diffuse and void growth occurs.
【００１４】上記の方法でＡｌ系配線膜を形成すると、
はじめに形成した連続膜の部分とその上の２００℃以上
で形成した部分とでＡｌの結晶粒界がずれ、ボイドの成
長が抑制される。このことからもストレスマイグレーシ
ョン耐性が向上する。When the Al-based wiring film is formed by the above method,
The grain boundaries of Al are deviated between the portion of the continuous film formed first and the portion formed above it at 200 ° C., and the growth of voids is suppressed. This also improves stress migration resistance.
【００１５】[0015]
【実施例】以下に本発明の一実施例を図１〜図３を用い
て説明する。図１において、絶縁膜１１を上面に有する
Ｓｉ基板１２上にＡｌ系配線膜１３を電子ビーム蒸着す
る。電子ビームでＡｌ系配線膜の固体蒸発源を溶融し、
蒸発した原子１４がＳｉ基板１２上に３ｎｍ／ｓｅｃの
速度で堆積する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, an Al-based wiring film 13 is electron beam evaporated on a Si substrate 12 having an insulating film 11 on the upper surface. The solid evaporation source of Al wiring film is melted by electron beam,
The vaporized atoms 14 are deposited on the Si substrate 12 at a rate of 3 nm / sec.
【００１６】基板温度を１５０℃に設定し、Ａｌ系配線
膜１３を１００ｎｍ蒸着する。その後２５０℃に基板温
度を上げ、さらにＡｌ系配線膜１３を４００ｎｍ堆積す
る。蒸着したＡｌ膜の配向性をＸ線ロッキングカーブ法
により測定した。The substrate temperature is set to 150 ° C. and the Al-based wiring film 13 is vapor-deposited to 100 nm. After that, the substrate temperature is raised to 250 ° C., and an Al-based wiring film 13 is further deposited to 400 nm. The orientation of the deposited Al film was measured by the X-ray rocking curve method.
【００１７】Ａｌ（１１１）に対するＸ線ロッキングカ
ーブを図３に示す。基板温度１５０℃で蒸着するＡｌ膜
が６０ｎｍの場合は、連続膜になっておらず、蒸着膜の
Ａｌ＜１１１＞は基板法線方向から傾いた方向にピーク
を持つ分布を示す。膜厚１００ｎｍ蒸着した場合は、連
続膜となり、Ａｌ＜１１１＞は法線方向にピークを持つ
分布を示す。図３中の矢印は基板法線方向を示す。The X-ray rocking curve for Al (111) is shown in FIG. When the Al film deposited at a substrate temperature of 150 ° C. has a thickness of 60 nm, it is not a continuous film, and Al <111> in the deposited film exhibits a distribution having a peak in a direction inclined from the substrate normal direction. When a film having a thickness of 100 nm is deposited, a continuous film is formed, and Al <111> exhibits a distribution having a peak in the normal direction. The arrow in FIG. 3 indicates the substrate normal line direction.
【００１８】上記の方法で作成したＡｌ系配線膜をフォ
トレジスト工程とドライエッチング工程によって図２に
示すように、Ａｌ系配線２１を形成する。その後、ＣＶ
Ｄ法によって燐ガラス２２を１μｍを堆積し、さらにそ
の上にプラズマＣＶＤ法で窒化珪素膜２３を０．３μｍ
堆積する。As shown in FIG. 2, an Al-based wiring 21 is formed on the Al-based wiring film formed by the above method by a photoresist process and a dry etching process. Then CV
Phosphorus glass 22 is deposited to a thickness of 1 μm by the D method, and a silicon nitride film 23 is deposited to a thickness of 0.3 μm by the plasma CVD method.
accumulate.
【００１９】このように形成されたＡｌ系配線を２００
℃の温度で１０００時間の保管試験を行った結果、スリ
ット形ボイドの発生は観測されず、かつ故障が発生する
平均時間よりも従来より１０倍以上向上した。The Al-based wiring thus formed is
As a result of carrying out a storage test at a temperature of 1000 ° C. for 1000 hours, the occurrence of slit-shaped voids was not observed, and the average time for failure was improved 10 times or more as compared with the conventional case.
【００２０】スパッタ法で上記のようにＡｌ系配線膜を
堆積した場合についても同様の効果があった。またＡｌ
合金系配線膜についても同様の効果があった。The same effect was obtained when the Al-based wiring film was deposited by the sputtering method as described above. Also Al
The same effect was obtained with the alloy-based wiring film.
【００２１】[0021]
【発明の効果】以上のように本発明の成形方法によれ
ば、ボイドの発生を抑制してＡｌ系配線のストレスマイ
グレーション及びエレクトロマイグレーション耐性を向
上させることができる効果を有する。As described above, according to the molding method of the present invention, it is possible to suppress the generation of voids and improve the stress migration and electromigration resistance of Al-based wiring.
【図１】本発明方法によるＡｌ系配線膜の断面図であ
る。FIG. 1 is a cross-sectional view of an Al-based wiring film formed by the method of the present invention.
【図２】本発明方法によるＡｌ系配線の断面図である。FIG. 2 is a sectional view of an Al-based wiring according to the method of the present invention.
【図３】電子ビーム蒸着法により作成したＡｌ系配線膜
のＡｌ（１１１）に対するＸ線ロッキングカーブを示す
もので、（ａ）は基板温度１５０℃で蒸着したＡｌ膜厚
が６０ｎｍの場合、（ｂ）は基板温度１５０℃で蒸着し
たＡｌ膜が１００ｎｍの場合の図である。FIG. 3 shows an X-ray rocking curve for Al (111) of an Al-based wiring film formed by an electron beam evaporation method, where (a) shows a case where the Al film thickness deposited at a substrate temperature of 150 ° C. is 60 nm ( b) is a diagram when the Al film deposited at a substrate temperature of 150 ° C. has a thickness of 100 nm.
１１ 絶縁膜 １２ Ｓｉ基板 １３ Ａｌ系配線膜 １４ Ａｌ系配線膜の構成原子 ２１ Ａｌ系配線 ２２ 燐ガラス ２３ 窒化珪素 11 Insulating Film 12 Si Substrate 13 Al-based Wiring Film 14 Al-based Wiring Film Constituent Atom 21 Al-based Wiring 22 Phosphor Glass 23 Silicon Nitride
Claims (1)
つ分布を示すＡｌ又はＡｌ合金系の連続膜を形成後、２
００℃以上でＡｌ系配線膜を形成することを特徴とする
Ａｌ系配線の形成方法。1. After forming a continuous film of Al or Al alloy system in which Al <111> has a distribution having a peak in the normal direction, 2
A method for forming an Al-based wiring, comprising forming an Al-based wiring film at a temperature of 00 ° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20182391A JPH0547762A (en) | 1991-08-12 | 1991-08-12 | Method of forming aluminum based wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20182391A JPH0547762A (en) | 1991-08-12 | 1991-08-12 | Method of forming aluminum based wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547762A true JPH0547762A (en) | 1993-02-26 |
Family
ID=16447492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20182391A Pending JPH0547762A (en) | 1991-08-12 | 1991-08-12 | Method of forming aluminum based wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547762A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538329B2 (en) | 1995-01-11 | 2003-03-25 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for making the same |
-
1991
- 1991-08-12 JP JP20182391A patent/JPH0547762A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538329B2 (en) | 1995-01-11 | 2003-03-25 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for making the same |
| US6583049B2 (en) | 1995-01-11 | 2003-06-24 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for making the same |
| US6780757B2 (en) | 1995-01-11 | 2004-08-24 | Renesas Technology Corp. | Semiconductor integrated circuit device and method for making the same |
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