JPH0322434A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a flat wiring, in which no hillock grows in a post-process, by forming an alloy film in thickness thicker than required thickness, executing heat treatment at a temperature higher than subsequent heat treatment, growing a hillock on a surface and flattening the surface through etchback up to neces sary thickness and patterning the surface. CONSTITUTION:N-type diffusion layers 2a, 2b are shaped to the surface of a P-type silicon substrate 1, and a silicon oxide film 3 is deposited. The silicon oxide film 3 is etched selectively to form a contact hole 4. An Al-Si alloy film 5 is deposited in thickness thicker than required thickness. Hillocks 6 are grown on the surface of the alloy film 5 through heat treatment at 470 deg.C. A surface is flattened through electrolytic polishing treatment while being etched back in specified thickness. Photo-resist films 7 are formed onto the alloy film 5 and patterned. The alloy film 5 is etched while using the photo-resist films 7 as masks to shape wirings 5a, 5b, and the photo-resist films 7 are removed. A phospho-silicate glass film is deposited on the surface at 400 deg.C lower than a previous heat treatment temperature, and used as a protective film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having metal wiring.

11- [Prior Art] As semiconductor devices become more highly integrated, the flatness of wiring becomes a problem.

FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

As shown in FIG. 3(a), N-type diffusion layers 2a and 2b are selectively formed on the main surface of a P-type silicon substrate l, and a silicon oxide film 3 is formed on the surface including the N-type diffusion layers 2a and 2b. form.

Next, the silicon oxide film 3 is selectively etched to form a contact hole 4.

Next, as shown in FIG. 3(b), the contact hole 4
An An-Si alloy film 5 is deposited on the surface including the .

Next, as shown in FIG. 3(c), the Al-Si alloy film 5
A photoresist film 7 is formed and patterned on top of the photoresist film 7. Next, the Au-Si alloy film 5 is etched using the photoresist film 7 as a mask to form interconnections 5a and 5b.

Next, as shown in FIG. 3(d), the photoresist film 7 is removed and heated at 400 to 450°C for 30 to 60 minutes. 77) A heat treatment is performed to deposit a protective film 8 on the surface including the wirings 5a and 5b.

Here, hillocks 6 are generated due to the heat treatment of the wirings 5a and 5b.

[Problem to be solved by the invention]

The conventional semiconductor device manufacturing method described above is based on A. &-Si
Heat treatment is performed after forming the wiring made of alloy film.
Hillocks grow on the surface of the wiring.

Hillock length also increases depending on the temperature during growth of the protective film.

The coverage of the protective film in areas where these hillocks are prominent is poor, and the probability of bottle holes occurring is high. There is also a possibility that cracks will occur in the protective film during the hillock growth process. Therefore, the conventional technology has the disadvantage that the moisture resistance and reliability of the semiconductor device are significantly reduced due to the influence of hillocks.

Furthermore, as the interconnect spacing becomes narrower as the degree of integration increases, hillocks extending laterally from the interconnects cause short circuits between the interconnects, resulting in a decrease in yield and reliability. Deterioration in yield and reliability due to lateral hillock growth is also a drawback of the prior art.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of depositing an AA alloy film with a thickness <thickness required for wiring on an insulating film provided on a semiconductor substrate having an element region, and a temperature higher than a heat treatment temperature in a subsequent step. heat treatment to generate hillocks on the surface of the An alloy film, and an electrolytic polishing process to
A step of flattening the surface of the alloy film by etch-packing it,
The method includes a step of selectively etching back the AA alloy film to form wiring.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
N-type impurities are selectively introduced into the surface of the N-type diffusion layer 2a.
, 2b are formed, and a silicon oxide film 3 is deposited on the surface including the N-type diffusion layers 2a and 2b.

Next, the silicon oxide film 3 is selectively etched to form a contact hole 4.

Next, as shown in FIG. 1(b), the contact hole 4
1. An-Si alloy film 5 containing 1% Si on the surface containing 1.
Deposit to a thickness of 6 μm.

Next, as shown in Figure 1(c), when heat treatment is performed at 470°C for 1 hour in an H2N2 atmosphere, hillock 6 is formed.
extends to a certain extent on the surface of the Al-Si alloy film 5.

Next, as shown in Figure 1(d), the concentration was 3% and the liquid temperature was 30%.
℃ in HBF4 solution, voltage 25V, current density 0. 5
Electrolytic polishing is performed using A/ctll using the Al-Si alloy film 5 as an anode to flatten the surface and etching the An-Si alloy film 5 to a thickness t-1.0 μm.

Next, as shown in FIG. 1(e), a photoresist film 7 is formed on the Ai7-Si alloy film 5 and subjected to stamping.

Next, as shown in FIG. 1(f), the AA-Si alloy film 5 is etched using the photoresist film 7 as a mask to form the wirings 5a and 5b, and the photoresist film 7 is removed.

Next, as shown in FIG. 1(g), a phosphosilicate glass film is applied to the surface including the wirings 5a, 5-lXb at a temperature of 40°C.
The protective film 8 is formed by depositing it to a thickness of 1.0 μm at 0° C. Here, the Al'-Si alloy film 5 is already at 470°C.
No hillocks were observed because the heat treatment was carried out for one hour. Therefore, there is no danger of the occurrence of holes or cracks in the protective film 8, and moisture-resistant and highly reliable wiring can be realized.

Further, it is possible to prevent wiring short circuits due to the occurrence of lateral hillocks.

FIGS. 2(a) to 2(g) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 2(a), the Ai7-Si alloy film 5 is shaped and heat-treated in the same process as in the first embodiment shown in FIGS. 1(a) to (c), and the hillock 6 is cause

Next, as shown in FIG. 2(b), electrolytic polishing is performed to
! - Etch the Si alloy film 5 to a thickness of -6- 0.5 μm.

Here, A. The surface of the &-Si alloy film 5 is further planarized than in the first embodiment.

Next, as shown in FIG. 2(c), the Al-Si alloy film 5
A patterned photoresist film 7 is formed thereon.

Next, as shown in FIG. 2(d), the Aj2-Si alloy film 5 is etched using the photoresist film 7 as a mask to form interconnections 5a and 5b. Next, after removing the photoresist film 7, an interlayer insulating film 9 is formed on the surface including the wirings 5a and 5b.
．． 1 stack with a thickness of 0 μm.

Next, as shown in FIG. 2(e), the interlayer insulating film 9 is selectively etched to provide contact openings 10 for the wirings 5a and 5b.

Next, as shown in FIG. 2(f), an Al--Si alloy film 11 is deposited on the surface including the opening 1o.

Next, as shown in FIG. 2(g), the AA-Si alloy film 1
1 is selectively etched to form a wiring 11a connecting to the wirings 5a and 5b, and a protective film 8 is formed on the surface including the wiring 11a.
form.

Here, there is an advantage that the amount of electrolytic polishing of the Aj2-Si alloy film 5 is increased to flatten the surface of the Aj2-Si alloy film 5 and to reduce the level difference between the wirings 5a and 5b that has occurred near the contact hole. . This technology makes it possible to realize a semiconductor device that is flat and free from the risk of interlayer shorts, pinholes, and cracks caused by hillocks.

〔Effect of the invention〕

As explained above, the present invention forms an Aj2-Si alloy film that is thicker than the required thickness as a wiring, and heat-treats the film at a higher temperature than the heat treatment in the post-process. - Create hillocks on the surface of the Si alloy film, etch-pack it to the required thickness of the Al-Si alloy film by electrolytic polishing treatment,
By flattening the surface and then patterning it by photolithography, it is possible to realize wiring with a flat surface without the growth of hillocks during post-process heat treatment and film lengthening.

Further, according to the present invention, it is possible to prevent short circuits between wiring lines due to lateral hillocks that grow in the Au-Si alloy film, and it is possible to improve yield and reliability.

[Brief explanation of drawings]

1(a)-(g) and FIG. 2(a)-(g) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention; Figures (a) to (d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device. 1...P-type silicon substrate, 2a, 2b...
...N-type diffusion layer, 3...Silicon oxide film, 4.
...Contact hole, 5...Aj2-
Si alloy film, 5a, 5b... wiring, 6...
...Hillock, 7...Photoresist film, 8...
...Protective film, 9...Interlayer insulating film, 10...
...Opening part, 11...Au-Si alloy film,
lla...Wiring.

Claims (1)

[Claims] Depositing an Al alloy film thicker than the thickness required for wiring on an insulating film provided on a semiconductor substrate having an element region;
The Al
a step of generating hillocks on the surface of the alloy film; a step of etching back and planarizing the surface of the Al alloy film by electrolytic polishing; and a step of selectively etching back the Al alloy film to form wiring. A method for manufacturing a semiconductor device, comprising: