JPH0548015B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to an information conversion device suitable for use in PCM recording of audio signals and the like. BACKGROUND TECHNOLOGY AND PROBLEMS For example, it has been proposed to convert audio signals into PCM and magnetically record them. When recording signals in such devices, modulation generally called NRZI is used. This is “1” in the data signal
The signal is inverted at "0" and not inverted at "0". By the way, when recording such a signal, if a large amount of low-frequency components are included, stability during reproduction deteriorates. On the other hand, if "0" continues in the above-mentioned NRZI, the modulation signal will not be inverted during that time, and the frequency will drop. Therefore, the PCM information is broken down into an arbitrary number of bits, and each bit is converted into a larger number of bits to prevent a large number of consecutive "0"s. As such an information conversion method, the applicant of the present application previously proposed the following. In this method, 8 bits (B ₁ , B ₂ , B ₃ ,
B ₄ , B ₅ , B ₆ , B ₇ , B ₈ ) information in 10 bits (P ₁ ,
P ₂ , P ₃ , P ₄ , P ₅ , P ₆ , P ₇ , P ₈ , P ₉ , P ₁₀ ). Here, there are 2 ⁸ =256 forms that the 8-bit information (B ₁ to B ₈ ) can take. On the other hand, for 10 bits (P ₁ to P ₁₀ ), first, in order to remove the DC component, the signal after NRZI modulation is
It is sufficient that 5 bits out of 10 bits be positive (1) and 5 bits be negative (0). Note that in order to set Tmax/Tmin=4, the condition is that the number of consecutive "0"s in NRZI representation is 3 or less, that is, the number of consecutive "0"s in the modulated signal is 4 or less at the same level. Considering these conditions, we further consider that the number of first or last “0” is 0 or 1 in NRZI representation.
The number of combinations in each case is as shown in Table 1 below.

[Table] From Table 1, it is possible to make the number of consecutive "0"s three or less even in the connection part between 10-bit patterns, for example, if the number of consecutive "0"s is two or less and the last "0" is This is the case when the number of 0'' is one or less. However, in this case, the number of combinations is only 69+34+40+20+20+10=193. This is less than the number of 8-bit 256 combinations, and with other selection methods, the number would be even smaller. Therefore, combinations other than DC component 0 will be considered. That is, for example, when the number of the last "0" is one or less, the number of combinations based on the number of the first "0" and the accumulated amount of DC is as shown in Table 2 below.

[Table] Here, regarding the accumulated amount of DC, for example, as shown in FIG. 1, it is assumed that the previous combination ends in a negative value (0). Therefore, if the previous combination ends with a positive (1), the positive and negative signs are reversed. For example, for a combination where the first bit is “0”,
When this leading bit is converted to "1", the sign of the accumulated amount of DC is reversed as shown in FIG. So, for example, the accumulated amount of DC in Table 2 is -2
Then, using 43+30=73 combinations in which the leading bit is "0", 8 out of 266 combinations, including the 193 first combinations without DC component mentioned above and 73 second combinations, are used. One-to-one correspondence with 256 bit combinations. Each time the second combination appears, the first bit is converted so that the accumulated amount of DC is alternately positive and negative. In other words, as shown in Figure 3, when a combination of 2 appears, the number of inversions (the number of "1"s) from the second bit is counted, and the number of inversions is counted until the next second combination appears. If it is an even number, the first bit (arrow) is converted to "1" as shown in A, and if it is an odd number, it remains as "0" as shown in B. Even if this causes an accumulation of DC of ±2, this is canceled out by the next second combination, and the DC component becomes 0 in any series of combinations. Furthermore, FIG. 4 shows an example of an apparatus for performing conversion according to the above-described method. In the figure, 1 is the input terminal, 2
is an 8-bit shift register for input, 3 is a conversion logic, and 4 is a 10-bit shift register for output. The information supplied to the input terminal 1 is transferred 8 bits at a time through the shift register 2, and 8 bits (B ₁ to B ₈ ) of information are supplied to the conversion logic 3. The conversion logic 3 performs the above-mentioned one-to-one conversion, and the converted 10-bit (P ₁ to P ₁₀ ) information is supplied to the shift register 4. Furthermore, the number of inversions of the signal after conversion is detected. Here, since the number of inversions is known in advance for each combination, for example, information on the number of inversions is stored in the read-only memory that constitutes the conversion logic 3 (it is only necessary whether the number of inversions is an odd number or an even number; for example, if it is an odd number, it is "1").
can be output simultaneously. This output Q is supplied to a latch circuit 8, and this latch output Q' is supplied to a conversion logic 3. Furthermore, the timing of every 8 bits of information supplied to the input terminal 1 is detected by the detection circuit 9, and this timing signal is supplied to the load terminal of the shift register 4 and the latch terminal of the latch circuit 8. For example, when converting to the second combination described above, use Q' to convert the first bit where Q' is "0" to "1" and the first bit where Q' is "1" to "0". . At that time, odd and even number information of the number of inversions of the output second combination is output to Q and latched. Furthermore, when converting to the first combination, the 10 output bits are output as they are, and the odd and even number information of the sum of the output inverting circuit of the first combination and Q' is output and latched to Q. Ru. Further, a clock signal having a frequency 5/4 times that of the input signal is supplied from the clock terminal 5 to the shift register 4, and the above-mentioned 10 bits are read out in sequence. This signal is supplied to the JK flip-flop 6, the clock signal from the terminal 5 is supplied to the flip-flop 6, and the NRZI modulated signal is taken out at the output terminal 7. Further, FIG. 5 shows an example of a device for demodulation, in which a signal from an input terminal 11 is supplied to a 10-bit shift register 13 through an NRZI demodulation circuit 12.
Information (P ₁ to _{P 10} ) from this shift register 13 is supplied to a conversion logic 14 . Demodulation is then performed by the above-mentioned one-to-one inverse conversion, and the demodulated information (B ₁ to _{B 8} ) is supplied to the shift register 15 and taken out to the output terminal 16. Note that when 10 bits according to the above-mentioned second combination are supplied, the first bit is ignored and the inverse conversion is performed. Conversion and demodulation can be performed in this way. However, in this method, the conversion logic 3,
If 14 were configured with read-only memory, an extremely large number of bits would be required, for example, if the circuit
This is not preferable because it requires a large area when converted into an LSI. OBJECTS OF THE INVENTION In view of these points, the present invention makes it possible to simplify the conversion logic. Summary of the Invention When performing NRZI modulation on information data consisting of multiple bits, an even-numbered bit of the information data is detected, and when this bit is 0, a DC value exists in this bit and the two bits in series. An information conversion device that detects that the information is detected and uses this detection signal to control the conversion of the information data. Example For example, there are 271 10-bit patterns out of a total of 1024 patterns that satisfy the above conditions. If these 271 patterns of 10 bits are divided into upper and lower 5 bits and classified, the patterns of the lower 5 bits can be classified into 5 groups A to E as shown in Table 3 below. Note that there are other exception patterns.

[Table] In Table 3, the leading bits of groups A and B are inverted and the remaining 4 bits are equal. Furthermore, the lower 3 bits of groups C and D are equal to the lower 3 bits of a pattern in which the leading bit is 0 in group A and the leading 1 in group B. On the other hand, the top 5 bits are as shown in Table 4 below.
There are 21 patterns.

【table】

[Table] The groups (A to E) of lower 5 bits that can be connected to these patterns while satisfying the above conditions are shown in the center column of the table. In addition, in the table, A' means those in group A whose first part is not 0, and B' means those whose first part is not 0 in group B.
Indicates something other than 00. Therefore, by adopting the groups marked with circles in the table, the number of patterns formed by each connection becomes as shown in the right column of the table, which is 240 in total.
pattern can be formed. Add to this 16 patterns in which the lower 5 bits become group E.
256 patterns can be formed. On the other hand, an 8-bit input pattern is divided into upper and lower 4 bits. Here, there are 16 patterns each of 4 bits. Therefore, the patterns of the upper 4 bits are respectively made to correspond to one or more of the 21 patterns in Table 4, and the patterns of the lower 4 bits are respectively made to correspond to the patterns of the 5 groups of Table 3. That is, first, the 16 patterns of the lower 4 bits are made to correspond to the 16 patterns of groups A and B in Table 3. As a result, the nine patterns of the upper five bits adopted in groups A and B (including B') in the center column of Table 4 can be directly associated with the upper four bits of the input. Next, among the 9 patterns of the upper 5 bits in which only either group A (including A') or group B is adopted, 2 patterns in which group B is adopted and any 2 patterns in which group A is adopted. These two sets (each two patterns) of the upper 5 bits are made to correspond to the two patterns of the upper 4 bits of the input. Further, any two patterns out of the remaining five patterns employed in group A are combined, and one set (two patterns) of these upper five bits is made to correspond to one pattern of the upper four bits of the input. Furthermore, by combining two patterns of the upper 5 bits adopted in groups A (including A') and C with any two patterns of the remaining 3 adopted patterns of group A, the upper 5 bits of these 2 patterns are combined. The two sets (two patterns each) are made to correspond to the two patterns of the upper 4 bits of the input. Also, by combining the remaining pattern adopted in group A and the one pattern adopted in groups B and D, one set (2
pattern) corresponds to one pattern of the upper 4 bits of the input. Then, the 16 patterns of the upper 5 bits employed in the E group are made to correspond to one pattern of the upper 4 bits of the input. By combining in this way, the 8→10 conversion can be divided into two systems of 4→5 conversion, and the conversion logic can be extremely simplified. Further, an example of a conversion/demodulation circuit will be described below. In FIG. 6, 21 is a group of 8-bit input terminals, 22 is a main logic circuit for conversion consisting of a programmable logic array (PLA) or a gate, and 23 is a sub logic circuit for reducing circuit 22. In FIG. In this sub logic circuit 23, by detecting the input pattern, for example in the above example, the detection signals a and E group are turned on when there is an input corresponding to a pattern that does not include group B, and are off otherwise. The detection signal c is on when the input corresponding to the group containing groups is received, and is off otherwise. It is formed. In other words, for example, if you input a set with two A groups, the top 4
FIG. 7 shows a specific example of a circuit in which bits _6H , _7H , and _EH are assigned, and a set including group E is assigned to _FH of the upper four input bits. Note that the detection signal c
In Table 3, the input lower 3 bits are 000.
If ~111 is assigned in order from the top, 010,
It is sufficient to turn on at 100 and 110 and turn off at other times, resulting in the circuit shown in the figure. These detection signals a to c are then supplied to the circuit 22 to control the conversion logic, thereby making it possible to greatly simplify the conversion logic. Note that 24 is used to reduce the main logic circuit 22.
A group of inverters inserted into the output of PLA,
Although it is not in parentheses, the effect is great. ( )
It is advantageous to include the items marked with . Further, 25 is a shift register for output. Furthermore, 26 is a circuit for forming an inversion control signal for the output leading bit by detecting the amount of accumulated DC. Further, 27 is an exclusive OR circuit for inverting the leading bit in accordance with this control signal, and 28 is a DC storage amount detection circuit. Here, the inversion control signal forming circuit 26 is formed as follows. In FIG. 8, the output of even-numbered bits of the output is supplied to the exclusive OR circuit 31,
All exclusive ors are taken. Here, when an even numbered bit is 1, inversion is performed in this part, and the DC amount between this bit and the immediately preceding bit becomes 0. On the other hand, when it is 0, there is a DC amount of ±2. Furthermore, if there are two 0s, the DC amount will be 0 or ±4, and similarly, if there are three, the DC amount will be ±2 or ±6. In other words, if the number of 0's is even, the DC flow is 0, ±
4, ±8...If it is an odd number, it will be ±2, ±6, ±10... On the other hand, the total DC amount for 10 bits is limited to 0 or -2. Therefore, by detecting whether the number of 0's in the even-numbered bits is even or odd, it is possible to determine whether the DC amount is 0 or ±2. Therefore, in the exclusive OR circuit 31 described above, when the output is 1, the DC amount is 0, and when the output is 0, the DC amount is -2.
can be detected. Furthermore, in FIG. 8, an exclusive OR circuit 32 and a D flip-flop 33 constitute an NRZI modulation circuit. Further, the DC accumulation amount detection circuit 28 is constituted by an up-down counter 34. That is, counter 3
4 is driven by a 1/2 frequency clock and only even numbered bits are counted. Further, the up-down is controlled by the output of the exclusive OR circuit 32. This allows the amount of accumulated DC to be detected. Note that since the output of the counter 34 is always delayed by 2 bits, exclusive OR circuits 35 and 36 are provided to correct the value using the final 2 bits. This detects whether the accumulated amount of DC is positive or negative.
This signal and the signal from the exclusive OR circuit 31 are supplied to a NAND circuit 37 to form an inversion control signal for the output leading bit. Regarding the inversion of the leading bit, the amount of DC accumulation may be detected using a counter or the like, and the leading bit of the output from the shift register 25 may be directly inverted. In this way, the converted signal is taken out to the output terminal 29. Furthermore, FIG. 9 shows an example of a demodulation circuit. Reference numeral 41 denotes a detection circuit for detecting the accumulated amount of DC, which is composed of a counter and the like.
The input signal passes through this circuit 11 and is supplied to a shift register 42, and the leading bit is inverted by an exclusive OR circuit 43 in accordance with the signal from the circuit 41 and supplied to a main logic circuit 44. Further, 45 is a sub logic circuit, for example, the 10th
Configured as shown in the figure, a detection signal e is generated when the pattern includes the E group, and a detection signal f is generated when the pattern includes the A group. When detecting groups A and B, when the 3rd and 5th bits are equal and the first bit is 1, and when the 3rd and 5th bits are different and the first bit is 0, group A, 3rd and 5th bits are detected. are equal and the first bit is 0, and when the third and fifth bits are different and the first bit is 1, it is group B. These detection signals e and f are then supplied to the circuit 44, which controls the conversion logic, thereby making it possible to greatly simplify the conversion logic. Note that by using the detection signal f, the sixth bit of the input becomes unnecessary. In this way, the demodulated signal is taken out to the output terminal group 45. Further, FIG. 11 shows a case where the main logic circuits 22 and 44 of the conversion and demodulation circuits are integrated, and the input circuit 21' corresponding to the input terminal group 21 of FIG. 6 and the output of the shift register 42 of FIG. Both are tri-stated and connected in common to the main logic circuit 50. On the other hand, the conversion/demodulation switching signal is sent to terminal 51.
is supplied to the main logic circuit 50 from. On the other hand, when examining the logic of the main logic circuits 22 and 44, there are many logics common to both. Therefore, as shown in the figure, by providing a logic X that is selected when the signal from the terminal 51 is 0, a logic Y that is selected when it is 1, and a common logic Z that is always selected, the two are configured separately The configuration can be further simplified. Note that if it is desired to perform conversion and demodulation simultaneously, these can be performed in a time-division manner. Effects of the Invention Therefore, according to the present invention, with the above-described configuration, it is possible to determine the necessity of inverting the first bit of the information data using a simple gate circuit.
It is not necessary to store the number of times data is inverted in the ROM, and this has the advantage of being suitable for LSI implementation.

[Brief explanation of drawings]

Figures 1 to 5 are diagrams for explaining background technology;
FIGS. 6 to 11 are diagrams for explaining the present invention. 22, 44, 50 are main logic circuits, 23, 45 are sub logic circuits, 31 is an exclusive OR circuit,
51 is a switching control terminal.

Claims (1)

[Claims] 1 When performing NRZI conversion on information data consisting of m (m is an even number) bits whose DC accumulation amount is defined as 0 or +2, or 0 or -2, the number of “0” in the even numbered bits of the above information data is A gate circuit that determines that the number of "0s" is an odd number, a detection circuit that detects the amount of accumulated DC, and when the gate circuit determines that the number of "0"s is an odd number, the output of the detection circuit is An information conversion device comprising: an inversion control circuit that inverts the first bit of the information data depending on whether the information is positive or negative.