JPS6048643A - Information converter - Google Patents

Abstract

PURPOSE:To simplify conversion logic by forming a logic used in conversion/ demodulation in common to a selected part at all times in an information converter used for PCM recording of a sound signal or the like. CONSTITUTION:An input pattern is classified into a high-order and a low-order bit, and the low-order bit is classified into 5 groups of A-E. The pattern of the group A having a bit other than 0 at the head is named as a group A' and the pattern of the group B having other bits than 00 at the head is named as a group B'. A sub-logical circuit 23 forms a detection signal (b) which is turned on when an input corresponding to a pattern not including the group A exists and is turned off in other cases by detecting the input pattern and a detection signal (b) when an input corresponding to the groups A', B' exists and a detection signal (c) which is turned on when the input corresponding to the set including the groups A' and B' exists and is turned off in other cases. The detection signals a-c are supplied to a main logical circuit of conversion to control the conversion logic.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information conversion device suitable for use in PCM recording of audio signals and the like.

Background Art and its Problems For example, it has been proposed to convert audio signals into PCM and magnetically record them. In recording the °ζ signal in such a device, modulation generally called NRZI is used. This will invert the signal at “1” in the data signal, and
” to prevent it from being reversed.

By the way, when recording such a signal, if it contains a lot of low-frequency components, the stability during playback becomes a problem. On the other hand, if "0" continues in the above-mentioned NRZI, the variable 6-cycle signal will not be inverted during that period, and the frequency will become low -F.

Therefore, the information by PCM is decomposed into an arbitrary number of bits, each of which is converted into a larger number of bits, and 0''
Efforts are being made to prevent a large number of consecutive occurrences.

As such an information conversion method, the applicant of the present application previously proposed the following.

In this method, 8 bits (B1, B2, B3 to B
4.86~B@SBy, Be) information in 10 bits (Pl, P2, Pl, P4, P5, Ps, Pv,
Pg, Ps, Pzo).

Here, there are 2e-256 possible forms for the 8-bit (81 to Bg) 1n information.

On the other hand, for 10 bits (P1 to Pto), 'ζ is first changed to 1 (
)Pip I・5 bits inside are stop (1), 5 bits are negative (0
). Note that T max / T min −
4, the number of consecutive “0” in NRZI expression is 31.
The condition is that it is 1M or less, that is, the number of successive bits of the same level in the signal after modulation is 4 bits or less.

After considering these conditions, further using NRZI expression,
The number of first or last “0” is 0, 1, 2, or 3
The number of combinations for each case is as shown in Table 1 below.

Table 1 From Table 1, we can see that even in the connection between 10-bit patterns, the number of consecutive "0"s is 3 or less. For example, if the number of consecutive "0"s is 2 or more and the last This is the case when the number of "0" is one or more. However, in this case, the number of combinations is 69+ 34+ 40-1-20+ 20+ ], 0=
There are only 193 ways. This is less than the number of 8-bit 256 combinations, and with other selection methods, the number would be even smaller.

Therefore, we will consider combinations other than the DC component 0.For example, if the number of the last "0" is 1 or less, the number of combinations based on the number of first "0" and the accumulated amount of DC is as follows. It will look like Table 2.

Table 2 Here, the accumulated amount of DC (°C) is the case where, for example, the previous combination ends in a negative value (0) as shown in FIG. If the last combination before the subordinate game C is positive (1) and the final game ζ is positive, the signs of positive and negative are reversed. For example, if the leading bit is converted to "pi" for a combination in which the leading hint is "0", the sign of the DC storage 4Ht is reversed as shown in FIG.

Therefore, for example, by using the 43 + 30 = 73 combinations in which the accumulated amount of DC in Table 2 is -2 - C1 where the first bit is "0", the above-mentioned 193 combinations (without DC component) and the first combination are used. , this second combination is 73 ways in total, 2
One-to-one correspondence is made with 256 combinations of 8 bits out of 66 combinations. And each time a second combination appears,
The first bit is converted so that the accumulated amount of DC stops and becomes negative alternately.

In other words, as shown in Figure 3, when the second combination appears, the number of reversals (11") from the second bit is counted, and the number of reversals is calculated until the next second combination appears. If it is an even number, the first bit (arrow) is converted to "1" as shown in A, and if it is an odd number, it remains 0" as shown in B.

Even if this causes a DC m product of ±2, this is canceled out by the next second combination, and the DC component becomes 0 in any series of combinations.

Furthermore, FIG. 4 shows an example of a device that performs the conversion according to the above-described method. In the figure, (11 is an input terminal, (21 is an 8-bit shift register for input, (3) is a conversion logic,
(4) is a 10-bit shift register for output. And the input terminal! The information supplied to Shift 11 is transferred 8 bits at a time through the shift 1 register (2), and 8 bits (Bz~
Be) is fed to the conversion logic (3). This conversion logic (3) performs the above-mentioned one-to-one conversion, and the information of the converted 10 pins) (Pi~Pto) is transferred to the shift I.
- Supplied to register (4).

Furthermore, the number of inversions of the signal after conversion is detected. Here, the number of inversions is known in advance for each combination, so for example, when configuring the conversion logic (3), information on the number of inversions is stored in the only memory (it is only necessary to know whether the number of inversions is odd or even; for example, if it is an odd number, 1'') can be output simultaneously.

This output Q is supplied to a latch circuit (8), and this latch output Q' is supplied to a conversion logic (3). Furthermore, the timing of every 8 bits of information supplied to the input terminal +11 is detected by the detection circuit (9), and this timing signal is transmitted to the load terminal of the shift register (4) and the latch circuit (8).
) is supplied to the launch terminal of

For example, when converted to the second combination mentioned above, Q
' If Q' is 0, set the first pitch to 1.
If Q' is 1'', the first bit is converted to 0. At that time, the odd/even number information of the number of inversions of the output second combination is output and latched to Q. It is further converted to the first combination. At this time, the lO bit of the output is output as is, and Q is the number of inversions of the first combination output and Q'
The odd and even number information of the sum of is output and latched.

Furthermore, from the clock terminal (5), a clock signal with a frequency 57/4 times that of the clock of the human input signal is sent to the shift register (
4), and the above-mentioned 10 bits are read out sequentially. This signal is supplied to the JK flip-flop (6),
The clock signal from the terminal (5) is sent to the flip-flop (6
), and the NRZI modulated signal is sent to the output terminal (
7).

FIG. 5 shows an example of a device for fjEtJm, in which the signal from the input terminal (11) is sent to the NRZI demodulation circuit (12).
) is supplied to the UIO bit shift register (13), and (P1 to P1 from this shift register (13)
10) is fed to the conversion logic (14). Demodulation is then performed by the above l to l inverse transformation, and the iM modulated (Bt to Bs) information is transferred to the shift register (15).
and is taken out to the output terminal (16). Note that when 10 bits according to the second combination described above are supplied, the first bit is ignored (inverse conversion is performed).

Conversion and demodulation can be performed in this way.

However, in this method, °ζ, conversion logic (3), (
14) is configured with read-only memory (3), it becomes extremely
C: It requires a large number of hits, and for example, when the circuit is implemented as an LSI, it requires a large area, which is not preferable.

OBJECTS OF THE INVENTION In view of these points, the present invention is intended to simplify the conversion logic.

Summary of the Invention The present invention converts m-bit information data into n-bit information,
In demodulating the n-bit information data into m-bit information, the m-bit information data and the n-bit information data are supplied to a single logic circuit, and this logic circuit is provided with a control terminal; The logic circuit is provided with a first part that is selected when the control terminal is 1, a second part that is selected when the control terminal is 0, and a third part that is always selected. The information conversion device is characterized in that logic commonly used for conversion and ffi opening is formed in the third portion, whereby the conversion logic can be simplified.

For example, there are 278 IO bit patterns out of a total of 1024 patterns that satisfy the two conditions.

If the 278 patterns of 10 bits are divided into upper and lower 5 bits and classified, the patterns of the lower 5 bits can be classified into 5 groups A to E as shown in Table 3 below. Note that there are other exception patterns.

Table 3 In Table 3, for groups A and B, the leading bit and 71- are reversed, and the remaining 4 bits are equal. Also, the lower 3 bits of groups C and D are A
The first position in the group is 0, and the first position in group B is equal to the top position of Bataan, 3 pips 1-.

On the other hand, there are 21 patterns for the first five bits as shown in Table 4 below.

Table 4 For these patterns, the group of lower 5 bits <A-E) that can be connected while satisfying the above conditions is always in the center column of the table. Note that in the table, A'' indicates a number whose leading part is other than 0 in the A group, and B' indicates a number whose leading part is other than 00 in the 8 groups.

Therefore, by adopting the groups marked with circles in the table, the number of patterns formed by each connection becomes as shown in the right column of the table, and a total of 240 patterns can be formed. By further adding 16 patterns in which the upper 5 bits are E group, 256 patterns can be formed.

On the other hand, the 8-bit input pattern is divided into upper and lower 4 bits.
Divide into bits. Here, there are 16 patterns each of 4 bits. Then, the patterns of the top 4 pinpoints are respectively made to correspond to one or more of the 2i patterns in Table 4, and the patterns of the -1st 4 bits are made to correspond to the patterns of the 5 groups of Table 3, respectively.

That is, first, the 16 patterns of the lower 4 bits are shown in Table 317.
) Corresponds to 16 patterns of ASB group. As a result, for the nine patterns of the upper 5 bits employed in groups A and B (including B') in the center column of Table 4, the upper 4 bits of the input can be directly associated with ζ. Next, A (A
), out of the nine patterns of the upper 5 bits that are adopted only from either group B, two patterns that are adopted from group B and any two patterns that are adopted from group A are combined, These two sets (two patterns each) of the top five bits are made to correspond to the two patterns of the -L four hits of human power. Also A
Any two patterns of the remaining five patterns adopted in the group are combined, and one set (two patterns) of these upper five bits is made to correspond to one pattern of the upper four bits of the input.

Furthermore, A (including A'), the top 5 adopted groups of 0
Combining the two bit patterns with any two of the remaining three patterns adopted for Am - these two sets (two patterns each) of the upper five bits are manually combined with the two patterns of the upper four bits of -F. Make it correspond. In addition, the remaining pattern adopted from group A and the pattern adopted from group B, I) are combined, and one set of these upper 5 bits (2 patterns) are created manually using the upper 4 bits. Compatible with one pattern・L
Ru. Then, the 16 Bakuns of the top 5 bits adopted by EJIF are made to correspond to one pattern of the top 4 bits of human power.

By combining in this way, the 8-10 conversion becomes 4→5
Since the conversion can be divided into two systems, the conversion logic can be extremely simplified.

Further, an example of a conversion/demodulation circuit will be described below.

In Fig. 6, ζ, (21) is a group of 8-bit input terminals, (
22) is a programmable logic array (PLA)
Or the main logic circuit for conversion consisting of gates, (23)
is a sub-logic circuit for reducing the size of the circuit (22).

In this sub-logic circuit (23), a detection signal is turned on when there is an input corresponding to a pattern of a set that does not include group B, and turned off otherwise. A, detection signal that is on when there is an input corresponding to the group including group E, and off otherwise.
A detection signal C is formed which is turned on when there is an input corresponding to the group including ', B' groups, and turned off otherwise.

That is, for example, a specific example of a circuit when a set containing two A groups is assigned to the upper 4 bits of 6H17H, B, and a set including the E group is assigned to F of the upper 4 bits of the input is shown in the seventh example.
It will look like the figure. Regarding the detection signal C, as shown in Table 3, if the 3 bits OOO to 111 of the C input position are assigned in order from the top, it is only necessary to turn on at 010.100 and 110 and turn off at other times. , resulting in the circuit shown in the figure.

These detection signals a"-"c are connected to the circuit (22)
By controlling the conversion logic with this, the conversion logic can be greatly simplified.

Note that (24) is P in order to reduce the main logic circuit (22).
The inverter group that is inserted into the output of the LA without the parentheses has a great effect. It is advantageous to include the items marked in parentheses.

Further, (25) is a shift register for output.

Further, (26) is a circuit that forms an inversion control signal for the leading bit of cutting edge by detecting the amount of accumulated DC as described above. Further, (27) is an exclusive OR circuit for inverting the first bit in accordance with this control signal, and (2B) is a DC accumulation amount detection circuit.

Here, the inversion control signal forming circuit (26) is formed as follows.

In FIG. 8, the output of even-numbered bits of the output is supplied to an exclusive OR circuit (31), and all exclusive ORs are taken. Here, when an even numbered bit is 1, each time an inversion is performed in this part, the DC amount between this bit and the immediately preceding bit becomes 0. On the other hand, when it is 0, there is a DC amount of ±2. Furthermore, if there are two 0s, the DC flow is 0 or ±4, and similarly, in the case of 31v1, ±2
or ±6. If the number of zeros is even, the DC flow is 0,
±4, ±8... If it is an odd number, it will be ±2, ±6, ±10... On the other hand, the total DC amount for 10 bits is limited to 0 or -2. Therefore, by detecting whether the number of 0s in the even-numbered bits mentioned above is even or odd, the DC amount is 0 or ±2
It is possible to determine whether

Therefore, in the exclusive OR circuit (31) described above, when the output is 1, DC MO can be detected, and when the output is 0, DC MO can be detected.

Furthermore, in Fig. 8, "ζ" is an exclusive OR circuit (
32) and a D flip-flop (33) constitute an NRZI modulation circuit.

Further, the DC accumulation amount detection circuit (28) is composed of an up-down counter (34). i.e. counter (34)
is driven by a clock with a frequency of A, and only even-numbered bits are counted. Also, exclusive OR circuit (3
The output of 2) is controlled to be up/down. This allows the amount of accumulated DC to be detected. Naori Unta (34)
The output of is closely delayed by 2 bits, so the value is changed to the last 2 bits;
・Exclusive OR circuit (3) so that h11 stops at
5) and (36) are provided.

This detects whether the accumulated amount of DC is positive or negative, and this signal and the signal from the exclusive OR circuit (31) are supplied to the NAND circuit (37) to form a 4-bit inversion control signal at the cutting edge. .

Regarding the inversion of the first bit, "ζ" is stored in a counter etc. as "C".
It is also possible to detect the DC star and directly invert the leading bit of the output from the shift register (25).

In this way, the converted signal is taken out to the output terminal (29).

Furthermore, FIG. 9 shows an example of a demodulation circuit. (41) is a detection circuit for detecting the amount of DC accumulation, and is composed of a counter and the like.

The human signal passes through this circuit (41) and is supplied to the shift register (42), and the leading bit is inverted by an exclusive OR circuit (43) according to the signal from the 1id (41). It is supplied to the main logic circuit (44).

Reference numeral (45) denotes a sub-logic circuit, which is constructed as shown in FIG. 10, for example, and generates a detection signal e when the pattern includes the E group, and a detection signal f when the pattern includes the A group. When detecting groups A and B, when the 3rd and 5th bits are equal and the first bit is 1, and when the 3rd and 5th bits are different and the first bit is 0, group A, 3rd and 5th bits are detected. are equal and the first bit is 0, and when the third and fifth bits are different and the first bit is 1, it is group B.

These detection signals θ and f are supplied to the circuit (44), and by controlling the 'ζ conversion logic, the conversion logic can be extremely simplified.

Note that by using the detection signal f, the sixth bit of human power is not required.

In this way, the demodulated signal is taken out to the output terminal group (45).

Furthermore, FIG. 11 shows a case where the main logic circuits (22) and (44) of the conversion and il lfJ circuits are integrated into a circuit (5o), and the input circuit corresponds to the input terminal group (21) in FIG. (21') and the outputs of the shift register (42) in FIG. The main logic circuit (5o) is supplied from the main logic circuit (5o).

On the other hand, when examining the logic of the main logic circuits (22) and (44), there is a lot of logic common to both.

Therefore, as shown in the figure, logic X is selected when the signal from the terminal (51) is O, and logic Y is selected when the signal is ■.
By providing a common logic Z selected for , lightning and lightning, the configuration can be further simplified than when both are configured separately.

Note that if it is desired to perform conversion and demodulation simultaneously, these can be performed in a time-division manner.

Effects of the Invention According to the present invention, the conversion logic could be simplified.

[Brief explanation of the drawing]

Figures 1 to 5 are diagrams for explaining the background technology, and Figures 6 to 5 are diagrams for explaining the background technology.
FIG. 11 is a diagram for explaining the present invention. (22), (44), (50) are main logic circuits, (23)
, (45) is a sub-circuit circuit, (31) is an exclusive OR circuit, and (51) is a switching control terminal. Figure 5 f3 Figure 6

Claims (1)

[Claims] In converting m-bit information data to n-bits and demodulating the above-mentioned n-bit information data into m-bits, the above-mentioned rn
bits of information data and n-bits of information data are supplied to a single logic circuit, the logic circuit is provided with a control terminal, and the logic circuit has a first portion selected when the control terminal is 1; A second part is selected when the terminal is 0, and a third part is always selected.
An information conversion device characterized in that the information conversion device is formed in a portion of the information conversion device.