JPH0548334A - CMOS oscillator circuit - Google Patents

Abstract

(57) [Summary] [Purpose] A CMOS that can flexibly respond to a wide range of power supply voltages and stably oscillates without oscillation stop or abnormal oscillation.
An oscillator circuit is provided. [Structure] The NMOS switch N ₃ and the PMOS of the oscillating circuit section are detected by the low voltage / high voltage detection signal from the power supply voltage detecting section.
NM connected in parallel by turning on / off the switch P _3.
OS transistors N _1, N ₂ and PMOS transistor P _1, oscillation / stop the N ₂ and P ₂ of P _2, set low gain gm of the CMOS inverter as seen from the outside when a low voltage high, when a high voltage To do. [Effect] A CMOS oscillation circuit that has a sufficient margin with the minimum oscillatable voltage, does not cause abnormal oscillation due to harmonic components at high voltage, and can operate stably in a wide power supply voltage range can be obtained. ..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS oscillator circuit, and in particular, in a device driven by a battery such as a cordless telephone handset, the AC power supply is rectified even when the number of batteries is reduced and the voltage is lowered. The present invention relates to a CMOS oscillation circuit that oscillates stably and surely as in the case of being driven by a stabilized voltage and can flexibly cope with a wide power supply voltage.

[0002]

2. Description of the Related Art A conventional low voltage driving method for a CMOS crystal oscillator circuit is described in, for example, "Design for Low Power CMOS Crystal Oscillator for Wrist Watch", pp. 636-1043, 1978/10 "Journal of the Institute of Electronics and Communication Engineers". Has been.

FIG. 6 is a diagram showing a standard circuit configuration of a CMOS crystal oscillation circuit. CMOS crystal oscillator circuit is PM
The crystal unit X is provided between the input and output terminals of the inverter circuit including the OS transistor Px and the NMOS transistor Nx.
Tal is connected to the feedback resistor Rf, and the resonance capacitors C ₁ and C ₂ of the crystal oscillator are further connected. The oscillation frequency of this CMOS crystal oscillation circuit is determined by the characteristic parameter of the crystal oscillator.

[0004]

The CM having the above standard structure
In the OS oscillator circuit, the gain of the inverter, that is, MO, is adjusted so that the OS operates stably when the power supply voltage is DC 3 to 6V.
When the size of the S electrode is set, the minimum oscillation voltage is around 2V, and the operation at the power supply voltage DC 1.8 to 3V, which is a target for lowering the voltage suitable for battery driving, cannot be guaranteed.

On the other hand, a power supply voltage DC suitable for battery driving
When the gain of the inverter is increased to operate stably at 1.8 to 3V, that is, when the size of the MOS electrode is increased, abnormal oscillation due to the harmonic component occurs this time when the power supply voltage is near DC 5 to 6V. There was a problem.

When an LSI including this CMOS oscillation circuit is to be applied to a cordless telephone, for example, in a cordless telephone handset, a system dedicated to driving a battery with a power source voltage of DC 1.8 to 3V and a power source voltage DC 1.8 to 3V are used. Power supply voltage DC3 ~
A 6V switching drive system is considered. As the power supply voltage switching driving method, a method of floating charging a rechargeable battery or the like can be adopted. In this method, it is desirable that the difference between the power supply voltages can be used without any particular awareness of the user. Further, if the same LSI can be used in the parent device and the child device, the cost will be reduced.

An object of the present invention is to provide a CMOS oscillator circuit which can flexibly cope with a wide range of power supply voltages and stably oscillates without causing oscillation stop or abnormal oscillation.

[0008]

In order to achieve the above object, the present invention provides a CMOS oscillating circuit in which a crystal oscillator, a feedback resistor and a resonance capacitor are connected to a CMOS inverter, wherein the CMOS inverter is an NMOS At least two inverters formed of a pair of a transistor and a PMOS transistor and connected in parallel, and a CMOS connected to each of the other inverters except one of the plurality of inverters
The present invention proposes a CMOS oscillation circuit including a switch that turns on / off each inverter according to the power supply voltage supplied to the inverter and changes the gain of the entire CMOS inverter.

In order to achieve the above-mentioned object, the present invention further comprises at least two inverters in which the CMOS inverter comprises a pair of an NMOS transistor and a PMOS transistor and are connected in parallel, and one of a plurality of inverters. Except for the switch connected to each other inverter to turn on / off each inverter to change the gain of the CMOS inverter as a whole, and to judge whether the power supply voltage supplied to the CMOS inverter is high or low, and turn on each switch according to the power supply voltage. The present invention proposes a CMOS oscillation circuit including a power supply voltage determination circuit for turning on / off.

In order to achieve the above object, the present invention further comprises at least two inverters, wherein the CMOS inverter comprises a pair of an NMOS transistor and a PMOS transistor and are connected in parallel, and one of a plurality of inverters. Except for the switch connected to each other inverter to turn on / off each inverter to change the gain of the CMOS inverter as a whole, and to judge whether the power supply voltage supplied to the CMOS inverter is high or low, and turn on each switch according to the power supply voltage. CM that includes a power supply voltage determination circuit that turns on / off and increases the gain when the voltage is low to expand the margin of the minimum oscillation maintaining voltage, while lowering the gain when the voltage is high and suppressing abnormal oscillation
It proposes an OS oscillator circuit.

Any of the CMOS oscillator circuits can be incorporated as a part of the semiconductor integrated circuit.

Further, if any one of the above CMOS oscillation circuits is built in a cordless telephone handset, the gain of the entire CMOS inverter is increased at the time of battery driven low voltage, and the high voltage driven by the power source rectified and stabilized by the commercial power source. Sometimes CMO
The gain of the entire S inverter can be reduced, the number of batteries to be built in can be reduced, and the cordless telephone handset can be made smaller and lighter.

[0013]

According to the present invention, at least two pairs of the NMOS transistor and the PMOS transistor of the CMOS inverter circuit are connected in parallel, and the NMOS switch and the PMOS switch are connected in series with each pair except one of them. These MOS transistor circuits are used as the oscillation circuit section. Further, the power supply voltage detection unit is configured by the voltage clamp circuit using the depletion type NMOS transistor circuit and the CMOS inverter circuit.

The low voltage / high voltage detection signal from the power supply voltage detection unit causes the NMOS switch and the PMO of the oscillation circuit unit.
NMO connected in parallel by turning on / off the S switch
At least one pair of the S transistor and the PMOS transistor is oscillated / stopped. As a result, the CM seen from the outside
The gain of the OS inverter is high when the voltage is low and is low when the voltage is high, and a CMOS oscillation circuit that stably oscillates in a wide range of power supply voltage such as DC 1.8V to 6V can be obtained.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a CMOS oscillator circuit according to the present invention.
It is a circuit diagram which shows an Example. The CMOS oscillating circuit of this embodiment is configured by connecting an inverter composed of a PMOS transistor P ₁ and an NMOS transistor N ₁ and an inverter composed of a PMOS transistor P ₂ and an NMOS transistor N ₂ in parallel.
An output inverter having C2 as an output terminal is included. P ₃ is P
A MOS switch and N ₃ are NMOS switches. These MOS switches are turned on when the voltage is low and oscillate the two sets of inverters in response to signals SIG1 and SIG2 from a power supply voltage detection unit which will be described later, while they are turned off when the voltage is high and the PMOS transistor P ₁ and NMOS
Only the inverter composed of the transistor N ₁ is oscillated. This inverter output signal OSC2 is sent to the inverter IN
Received at V3, clock φosc inside CMOS integrated circuit
Supply as.

The power supply voltage detector is a depletion type NM.
The voltage clamp circuit using the NDMOS transistor which is the OS clamps the potential at the point a, and the power supply voltage Vcc ≦
When the clamp voltage VCLAMP, the power supply voltage Vcc is output as it is, and when the power supply voltage Vcc> the clamp voltage VCLAMP, the clamp voltage VCLAMP is output.

The oscillation circuit unit and the power supply voltage detection unit are CM
It is configured inside the OS integrated circuit, and the crystal oscillator Xtal and the feedback resistor Rf are provided between the input terminal OSC1 and the output terminal OSC2.
Are connected in parallel, and the input terminal OSC1 and the output terminal OSC2 are grounded through the resonance capacitors C ₁ and C ₂ , respectively.

FIG. 2 is a diagram for explaining the gain switching operation of the CMOS inverter. When switching the gain of the inverter configured to connect the oscillator circuits in parallel, the INV
1 logic threshold voltage VLT is clamp voltage VCLAM
NDMOS transistor and INV1 to match P
By setting and, it is possible to generate so as to invert the power supply voltage detection signals SIG1 and SIG2 according to the value of the power supply voltage Vcc. The output of the voltage clamp circuit using the NDMOS transistor, that is, the voltage at the point a is Vcc when Vcc ≦ VCLAMP.
And when Vcc> VCLAMP, VCLAMP. On the other hand, I
The logic threshold voltage VLT of NV1 is proportional to the power supply voltage Vcc. Therefore, the output SIG1 of INV1 switches and the output SIG2 of INV2 switches in accordance with the power supply voltage V _{1 at} which V CLAMP and V LT match.

[0019] Consequently, as shown in the table the lower half of FIG. 2, Vcc ≦ V ₁ when that is, when the low-voltage MOS switch P _3, N ₃ is turned on, the MOS switch at the time when or high voltage Vcc> V ₁ P ₃ and N ₃ are turned off. Vcc ≦ V
_At the low voltage of ₁ , the oscillating CMOS inverters are P ₁ , P ₂ ,
It is composed of four MOS transistors N ₁ and N ₂ , and the inverter gain gm is as shown in Expression 1.

[0020]

[Equation 1]

On the other hand, when the high voltage Vcc> V ₁ , the oscillation CMO
The S inverter is composed of one MOS of P ₁ and N ₁ .
The gain gm of the inverter is as shown in Equation 2.

[0022]

[Equation 2]

The gain gm ₁ is defined by the MOS transistors P ₁ and N _1.
And the gain gm ₂ is determined by the size of the MOS transistors P ₂ and N ₂ . Therefore, the inverter gains gm ₁ + gm ₂ and gm ₁ at the time of low voltage and at the time of high voltage can be freely selected, and the inverter gain value which is the most stable in the low and high voltage ranges can be selected.

FIG. 3 is a diagram showing a configuration of an embodiment of a CMOS oscillation circuit which does not include a power supply voltage detecting section in order to enhance versatility and control by an external digital signal. In this embodiment, the gain control CMOS
The number of parallel inverters is three or more, and the input terminals for the power supply voltage determination signals ENABLE and ENABLE are provided. Note that the ENABLE inversion signal should originally be displayed as an overline, but is displayed as an underline in this specification due to the limitation of the specification creation method. According to this circuit, it arbitrarily selected by controlling the gain of the CMOS inverter from gm ₁ to _{gm 1 + gm 2 + ......... +} gmx.

FIG. 4 is a block diagram showing an example of the configuration of an electronic control system using the CMOS oscillation circuit of FIG. As the power source, there are a power source obtained by AC / DC conversion of a commercial power source and a battery power source, and these power sources are switched by a power source changeover switch and used. Generally high voltage AC / D
When the output voltage of the C converter and the voltage of a low-voltage battery are different from each other, the battery weight occupies a large proportion of the total weight, especially in cordless telephone handsets, and the reduction in the number of batteries is effective in reducing the overall weight. In some devices according to the present invention, when driven by either of the power sources,
An electronic control system having a CMOS oscillating circuit that can operate stably can be obtained.

FIG. 5 is a diagram showing a modification of the MOS switches P ₃ and N ₃ of FIG. When ENABLE ₂ = “0”, the overall gain is gm ₁ , and when ENABLE ₂ = “1”, the overall gain is gm ₁ + gm ₂ .

There are various other switches that can obtain the same effects as the MOS switch of the present invention. further,
It is also possible to adopt an aluminum master slice system in which ENABLE ₂ and ENABLE ₂ are fixed to Vcc or GND depending on the operating voltage range.

In the above embodiment, the oscillator circuit section is constituted by the CMOS inverter, but the same effect can be obtained by using the bipolar transistor inverter.

[0029]

According to the present invention, according to the power supply voltage, C
The gain of the oscillation inverter of the MOS oscillation circuit can be set high at low voltage and low at high voltage. Therefore, there is a sufficient margin between the minimum voltage that can be oscillated and
Moreover, a CM capable of operating stably in a wide power supply voltage range without causing abnormal oscillation due to harmonic components at high voltage
An OS oscillator circuit can be obtained.

If the CMOS oscillator circuit of the present invention is applied to a portable device such as a cordless telephone handset, a device having a smaller size and stable performance can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a CMOS oscillator circuit according to the present invention.

FIG. 2 is a diagram illustrating a gain switching operation of a CMOS inverter.

FIG. 3 is a diagram showing a configuration of an embodiment of a CMOS oscillation circuit which does not include a power supply voltage detection unit in order to enhance versatility and control by an external digital signal.

4 is a block diagram showing an example of a configuration of an electronic control system using the CMOS oscillation circuit of FIG.

FIG. 5 is a diagram showing a modification of a gain switching MOS switch.

FIG. 6 is a diagram showing a standard circuit configuration of a conventional CMOS crystal oscillation circuit.

[Explanation of symbols]

C _1, C ₂ resonant capacitor ENABLE ₂ ~x inverted signal INV1～3 CMOS inverter NDMOS depletion type N-type MOS N ₁ of the CMOS oscillator inverter enable signal _{ENABLE 2 ~x ENABLE 2, N 2} , N 3, ~Nx, Nx + 1 N type MOS OSC1 CMOS oscillator external input terminal OSC2 CMOS oscillator external output terminal P ₁ , P ₂ , P ₃ , ~ Px, Px + 1 P type MOS Rf Feedback resistor SIG INV output signal Xtal Crystal oscillator φosc CMOS integrated Circuit internal clock

Claims (5)

[Claims] 1. A CMOS oscillator circuit comprising a CMOS inverter, a crystal oscillator, a feedback resistor, and a resonance capacitor connected to each other, wherein the CMOS inverter includes an NMOS transistor and a P-type transistor.
At least two inverters that are paired with a MOS transistor and are connected in parallel, and the CMO that is connected to each of the other inverters except one of the plurality of inverters.
And a switch for changing the gain of the entire CMOS inverter by turning on / off each of the inverters according to a power supply voltage supplied to the S inverter.
S oscillation circuit. 2. A CMOS oscillator circuit comprising a CMOS inverter connected to a crystal oscillator, a feedback resistor and a resonance capacitor, wherein the CMOS inverter comprises an NMOS transistor and a P transistor.
At least two inverters that are paired with a MOS transistor and are connected in parallel, and are connected to each of the other inverters except one of the plurality of inverters to turn on / off the respective inverters and the gain of the entire CMOS inverter. And a power supply voltage determination circuit for determining whether the power supply voltage supplied to the CMOS inverter is high or low and turning on / off each switch according to the power supply voltage. 3. A CMOS oscillator circuit comprising a CMOS inverter connected to a crystal oscillator, a feedback resistor and a resonance capacitor, wherein the CMOS inverter comprises an NMOS transistor and a P transistor.
At least two inverters that are paired with a MOS transistor and are connected in parallel, and are connected to each of the other inverters except one of the plurality of inverters to turn on / off the respective inverters and the gain of the entire CMOS inverter. And a switch for changing the power supply voltage supplied to the CMOS inverter, and each switch is turned on / off according to the power supply voltage to increase the gain when the voltage is low and expand the margin of the minimum oscillation maintaining voltage. A CMOS oscillation circuit, comprising: a power supply voltage determination circuit that lowers a gain at high voltage and suppresses abnormal oscillation. 4. A semiconductor integrated circuit having the CMOS oscillator circuit according to claim 1 built therein. 5. A built-in CMOS oscillating circuit according to any one of claims 1 to 4, which increases the gain of the CMOS inverter as a whole at a low voltage driven by a battery and rectifies and stabilizes a commercial power source. When the driving voltage is high, the above-mentioned C
A cordless telephone handset characterized by reducing the gain of the entire MOS inverter.