JPH0548498B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A plurality of processors each have a built-in buffer storage, and information read from the same storage device is stored in each buffer storage and is used to perform processing. In a system configured like this, when one processor rewrites the contents of buffer storage, if another processor already has the corresponding data in buffer storage, it is necessary to prevent this data from being used accidentally. shall immediately indicate that the data is invalid. These processes are performed by a storage control device installed between each processor and the storage device, but the process of invalidating the buffer storage contents of other processors ensures the correctness of the system's processing. It plays an important role in this process. Conventionally, the buffer invalidation processing device provided in this storage control device is tested by confirming that a buffer invalidation request signal is raised to other processors in response to a write request from one of the processors. However, the test requires the use of two processors, and since write requests or invalidation operations must be performed on a large number of addresses as in actual use, a queue must be created. The problem was that it was difficult to conduct the test in such a situation. In order to solve these conventional problems, the present invention has the following objectives:
Regarding a test method for a buffer nullification processing device that allows testing of the buffer nullification processing device using a single processor, and also allows easy testing under load conditions similar to actual usage conditions. Disclosed.

[Industrial Application Field] The present invention is intended to prevent misuse of the contents of buffer storages built into each of a plurality of processors that share a storage device when the information stored in the corresponding storage device is updated. This relates to a test method for a device that invalidates a device.

[Prior Art] FIG. 3 is a diagram illustrating the operation of a buffer invalidation processing device, in which 51 and 52 are processors;
Reference numerals 3 and 54 represent buffer storages, 55 a storage control device, 56 a shared storage control device, 57 a buffer invalidation processing device, and 58 a shared storage device.

In the figure, a processor 51 and a processor 52 can access a shared storage device 58 via a storage control device 55.

However, accessing the shared storage device 58 every time necessary data is read or written is inefficient, so data is stored in the buffer storage 53 or 54 in the processor in advance in units of a certain size area. The information in the shared storage device 58 is copied, and each processor performs processing using the contents of these buffer storages.

At this time, if the processor updates the data in the buffer storage, the data in the shared storage device 58 must be updated as well.

Furthermore, if another processor holds information in the corresponding area in the buffer storage, it is necessary to indicate that the data is invalid to prevent it from being used incorrectly.

Such invalidation processing is performed by the storage control device 55.
This is performed by the buffer invalidation processing device 57 in the buffer.

FIG. 4 is a block diagram showing the configuration of the buffer invalidation processing device, in which 59 and 60 are ports, 61 is a priority circuit, 62 is an access information register (MSAR), 63 is an input control circuit, etc. 6
4 is an invalidation processing circuit for processor 1, 65 is an invalidation processing circuit for processor 2, 66 ₁ to 66 ₄ are address registers, 67 is a selector, 68 is an address register, and 69 is a buffer storage for the corresponding processor. A memory stores the address of the area of the shared storage device being copied, 70 is a comparator, and 71 is a register. Processor 1 or processor 2 in this figure is
This corresponds to processor 51 or processor 52 in the figure.

FIG. 5 is a diagram showing an example of the configuration of an input control circuit of a conventional invalidation processing device, in which 62 is a register (MSAR), 62 ₁ is an address section, 62 ₂ is a function section, 62 ₃ is an iD section, and 72 is a Function decoding section, 73 is iD decoding section, 74, 75
represents an AND circuit.

An outline of the operation of the buffer invalidation processing circuit will be explained with reference to FIGS. 3 to 5.

For example, when the processor 52 rewrites the contents of the buffer storage 54, the shared storage device 5
In order to also rewrite the contents of 8, the shared storage control device 56 of the storage control device 55 is notified by signal A (write request signal).

This write request is input to the priority circuit 61 from the port 60 in FIG.

On the other hand, this information is input to the input control circuit 63 in FIG.

As shown in FIG. 5, the input control circuit 63 decodes the information in the function section ₆₂₂ with a function decoding circuit 72, outputs "1" if it is a write request, and outputs "1" between this and the iD section. The AND circuit 75 outputs the AND circuit 75 as a signal C with the signal on the processor 2 side that is output as a result of the iD decoding circuit 73 decoding the contents of 62 ₃ .

As a result, address information related to writing by processor 2 is stored in register ₆₆₁ . At this time, when subsequent address information arrives, they are successively shifted to 66 ₂ to 66 ₄ and held.
These pieces of address information are selected by the selector 67 from the first one and set in the register 68.

Since the address of the shared storage device 58 held in the buffer storage 53 of the processor 51 is held in the memory 69, it is searched using part of the address information (for example, a page) in the register 68 as a key, and the lower address of the read address is stored. The value of comparator 7
0 and when they match, the corresponding address is set in the register 71 and sent to the processor 51 as a buffer invalidation request signal E.

[Problems to be Solved by the Invention] The conventional buffer invalidation processing device as described above plays an important role in maintaining the uniformity of stored information within the system and ensuring system reliability. Therefore, it must always be operating correctly, and therefore it is necessary to frequently check it with a test program.

However, as mentioned above, the buffer invalidation processing device has the configuration shown in Figure 4, so in order to reliably check this, it is necessary to transfer a large number of address values from one processor to the other. Since it is necessary to use an inspection method in which a buffer invalidation request signal is generated for each processor and compared with each other, there are problems in that two processors are required and the test takes a long time.

SUMMARY OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a mechanism that allows a buffer invalidation processing device to be easily tested using a single processor.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, the present invention includes an instruction means for displaying on a storage control device that the buffer invalidation processing device is in a test state, and when the instruction means indicates that the buffer invalidation processing device is in a test state, an instruction from any processor is provided. When a write request to a storage device is received, means is provided for issuing a buffer invalidation request signal to the processor to invalidate information in a corresponding area of the buffer storage.

FIG. 1 is a diagram for explaining the principle of the present invention, in which 1 and 2 are processors, 3 and 4 are buffer storages, 5 is a storage control device, 6 is a shared storage control device, and 7 is a buffer invalidation device. A processing device, 8 a shared storage device, 9 an input control circuit, and 10 a flag for setting a test state.

[Operation] In FIG. 1, when testing the function of the buffer invalidation processing device 7, the flag 10 is set to "1" to put the device in a test state.

When the flag is "1" in this way, for example, when the processor 1 issues a write request A to the shared storage device 8, the input control circuit 9 activates the buffer invalidation processing circuit corresponding to the processor 1. As a result, an invalidation request is made to the processor 1 in response to the signal E.

Similarly, a write request B is sent from processor 2.
Also, when the invalidation request F is issued to the processor 2.

Therefore, the buffer invalidation processing device can be tested by having any one processor run the test program.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention, showing a flag for setting a test state and a part of an input control circuit.

In the same figure, 11 is a register (MSAR), 1
1 ₁ is address word, 11 ₂ is function part, 1
1 ₃ is the iD section, 12 is the function decoding circuit,
13 is an iD decoding circuit, 14 is a flag, 15 is an inverter, 16 to 19 are AND circuits, 20,2
1 represents an OR circuit.

Under normal conditions, the flag 14 is set to "0", and in response to a write request from the processor 1, the output of the OR circuit 20 becomes "1", which is used as a signal D to perform buffer invalidation processing for the processor 2. A circuit (such as phase 65 in FIG. 4) is activated and the corresponding contents of the buffer storage of processor 2 are invalidated.

In addition, in response to a write request from processor 2, the output of OR circuit 21 becomes "1", and this is used as a C signal to activate the buffer invalidation processing circuit for processor 1, thereby disabling the corresponding buffer storage of processor 1. The content to be used will be invalidated.

In the figure, the flag 14 is set to "1" in order to put the buffer invalidation processing device into a test state.

In this state, for example, when a write request is received from the processor 1, the output of the AND circuit 17 becomes "1", which is passed through the OR circuit 21 as a C signal.
Start up the buffer invalidation processing device for processor 1. Therefore, the buffer storage of the processor 1 is invalidated by the signal E shown in FIG.

In this way, the buffer invalidation request signal is returned to the processor that issued the write request, so
By running a test program on one processor, it is possible to easily check whether invalidation processing is performed normally for each address.

[Effects of the Invention] As explained above, according to the present invention, it is possible to test a buffer invalidation processing device with one processor, and therefore it is possible to continuously make write requests for a large number of address values. This has the advantage that it is possible to easily conduct a test in accordance with the actual operating state while increasing the load on the buffer invalidation processing device.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram for explaining the operation of the buffer invalidation processing device, and FIG. 4 is a diagram for explaining the operation of the buffer invalidation processing device. FIG. 5 is a block diagram showing the configuration of a buffer invalidation processing device. FIG. 5 is a diagram showing an example of the configuration of an input control circuit of a conventional buffer invalidation processing device. DESCRIPTION OF SYMBOLS 1, 2...Processor, 3, 4...Buffer storage, 5...Storage control device, 6...Shared storage control device, 7...Buffer invalidation processing device, 8...Shared storage device, 9...Input control circuit, 10...Test Flag for setting status, 11...Register, 11 ₁
...Address word, 11 ₂ ...Function part, 11 ₃
...iD section, 12...function decoding circuit,
13...iD decoding circuit, 14...flag, 15...
Inverter, 16-19...AND circuit, 20,2
1...OR circuit.

Claims (1)

[Scope of Claims] 1. A plurality of processors can access the same storage device, each processor has a built-in buffer storage, and the contents of a necessary area of the storage device are copied to the buffer storage. In a system configured to be used as a processor, the processor is located between each processor and the storage device, and when one of the processors rewrites information in the storage device, the other processors have already copied the information to the buffer storage. In a storage control device equipped with a buffer invalidation processing device that issues a buffer invalidation request signal for invalidating information in a corresponding area, the buffer invalidation processing device is in a test state. , When the instruction means indicates that it is in a test state, when a write request to the storage device is received from any processor, information on the corresponding area of the buffer storage is sent to the processor. 1. A buffer invalidation processing device testing method, comprising: means for issuing a buffer invalidation request signal for invalidating a buffer invalidation processing device.