JPH0551208B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic gain control circuit.

[Prior Art] Conventionally, a commonly used automatic gain control circuit has a configuration as shown in FIG. Since each output of the differential output type gain control circuit G cannot be directly supplied to the comparator C, the transistors T7 and T8
The comparator C is configured so that a level difference is applied to each input of the comparator C through a circuit including resistors R ₁ and R ₂ .

To explain the operation, when the output voltage v _i from the gain control circuit G is applied to the bases of the transistors T ₇ and T ₈ , let i ₁ be the change in the collector current of the transistors T ₇ and T ₈ , and let the bias current be 2I. ,
Currents (I+i ₁ ) and (I-i ₁ ) flow through the transistors T ₇ and T ₈ , respectively, and as a result, the collector potential V _C7 of the transistor T ₇ decreases, and the collector potential V _C8 of the transistor T ₈ increases. , V _C7 = V _CC −R ₁ (I + i ₁ ) V _C8 = V _CC − R ₂ (I − i ₁ ) ∴i ₁ = (R ₂ − R ₁ ) I/(R ₁ + R ₂ ), Since the comparison level is given by V _C7 = V _C8 , for example, the resistance values of resistors R ₁ and R ₂ are set to 1:2.
When set to , when i ₁ = I/3 or more,
The collector voltage of transistor T ₇ is the transistor
_T8 becomes lower than that of T8, comparator C operates, and the output of gain control circuit G is fed back to become smaller.

By this operation, i ₁ = I/3,
The output of the gain control circuit is automatically controlled.

[Problems to be Solved by the Invention] In the above circuit configuration, the resistors R ₁ and R ₂ are used to set the start level of gain control, that is, to set the differential input at which the output current begins to appear. This required relative accuracy for each resistor, making it unsuitable for integration.

Furthermore, since a level setting circuit and a comparator are required, the overall configuration becomes complicated.

According to the present invention, the starting level of gain control can be set arbitrarily and accurately, and the circuit configuration is simplified and the configuration is suitable for integration.

[Means for Solving the Problem] The present invention provides a method in which one differential output from a gain control circuit is common to the bases of m (m=2, 3...) transistors connected in parallel forming a first circuit. n (n=
1, 2..., where n<m) transistors connected in parallel and forming a third circuit (m-n)
A first circuit is connected in series to the bias side of the current mirror circuit, a second circuit is connected in series to the output side of the current mirror circuit, and a second circuit is connected in series to the output side of the current mirror circuit. A third circuit is connected in parallel to the series circuit consisting of the output side of the current mirror circuit and the second circuit, and the base of the control transistor is connected to the connection point of the current mirror circuit and the second circuit. The output of the transistor is fed back to the gain control circuit to control its differential output, and the start level of the gain control is set by the number of transistors in the first, second and third circuits. , has achieved the above objectives.

[Example] In FIG. 1, G is a gain control circuit that generates a differential output, T ₁ and T ₂ are transistors that make up the first circuit, T ₃ is a transistor that makes up the second circuit, and T ₄ is a transistor that makes up the second circuit. a transistor constituting a third circuit;
D and _T5 are a diode and a transistor, respectively, forming a current mirror circuit. _T6 is a control transistor, C is a capacitive element, and the differential output of the gain control circuit G is controlled by the charging voltage thereof. R is a transistor for discharging the charge of the capacitive element C with an appropriate time constant.

Next, the operation will be explained. First, let I be the bias current of transistors T ₁ to _{T 4} , let i ₁ be the change in the collector current of transistors T ₁ and T ₂ due to the input signal, and let i ₂ be the change in the collector current of transistors T ₃ and T ₄ due to the input signal. . Therefore, when a differential output as shown in the first diagram is generated from the gain control circuit G, from the basic characteristics of the differential amplifier circuit, 2(I-i ₁ )+2(I+i ₂ )=4I −2i ₁ +2i ₂ =0 ∴ i ₂ = i ₁ . Therefore, when _an input signal is applied, ₂ (I-
A collector current of (I+ _{i 1 )} flows through the collectors of the transistors T ₃ and T ₄ , respectively.

Since the diode D and the transistor T5 form a current mirror circuit, a collector current of 2(I-i ₁ ) flows through the collector of the transistor T ₅ , and a current I _b6 flowing through the base of the transistor T ₆ is equal to the collector current of the transistor T _{3 .} The collector current of I _c3 and the transistor T ₅
Therefore, I _b6 =2(I-i ₁ )-(I+i ₁ )=I-3i ₁ .

When no input signal is applied (i ₁ = 0), the transistor T ₆ is in the cut-off state because I _b6 > 0, but when the input signal is applied, i ₁ becomes I/3
When it becomes larger, transistor T ₆ becomes active and collector current flows through transistor T ₆ . Therefore, the charging voltage of the capacitive element C increases, and feedback is applied to the gain control circuit G, causing its differential output to decrease. This reduction in differential output
When i ₁ becomes equal to I/3, the base current I _b6 of transistor T ₆ becomes 0 and transistor T ₆ is cut off. Therefore, the charge in the capacitive element C is discharged through the resistor R, the feedback voltage to the gain control circuit G decreases, and its differential output increases.

By repeating the above operation, i ₁ = I/3
The gain is automatically controlled.

Note that in the above embodiment, two transistors are connected in parallel as the first circuit, and one transistor is used as the second circuit, but the present invention is not limited to this. m (m=2, 3...) as the first circuit
n transistors are connected in parallel as a second circuit, n (n=1, 2..., where m<n) transistors are connected in parallel, and a third circuit is (m-
n) transistors are connected in parallel, and these m and n
The reference current i ₁ can be set to any value by setting . That is, in the case of the above configuration, the first
Each of the m transistors in the circuit has (I-
i ₁ ) flows, and currents (I+i ₁ ) flow in each transistor of the second circuit and the third circuit, so the base current I _b6 of transistor T ₆
I _b6 =m(I-i ₁ )-n(I+i ₁ )=(m-n)I-(m+n)i ₁ . The reference current i ₁ for which I _b6 = 0 is, i ₁ = (m-
n) I/(m+n), and the number of transistors m
The start level of automatic gain control can be arbitrarily set by setting n and n.

[Effects of the Invention] According to the present invention, the circuit configuration is simpler than the conventional one, and the start level of automatic gain control can be set depending on the number of transistors. Accuracy can be improved, making it suitable for integration.

Furthermore, since all the transistors in the conversion circuit operate at the same operating point, balance can be maintained.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is an electric circuit diagram showing an example of a conventional circuit configuration. G...gain control circuit, _T1 , _T2 ...first circuit,
T ₃ ... second circuit, T ₄ ... third circuit, D, T ₅
...Current mirror circuit, T ₆ ...Control transistor,
C...capacitive element, R...resistance.

Claims (1)

[Claims] 1. A gain control circuit that generates a differential output for gain control, and m (m=2, 3...) transistors each having one output from this gain control circuit as a common base input. Connect in parallel to form a first circuit, and use the other output from the gain control circuit as a common base input n (n=1, 2..., however, n<m)
A second circuit is constructed by connecting transistors in parallel, and a third circuit is constructed by connecting (m-n) transistors in parallel, each of which uses the other output from the gain control circuit as a common base input. A first circuit is connected in series to the bias side of the current mirror circuit, a second circuit is connected in series to the output side of the current mirror circuit, and the output side of the current mirror circuit and the second circuit are connected in series. A third circuit is connected in parallel to the series circuit consisting of the above current mirror circuit and the second circuit, and the base input side is connected to the connection point between the above current mirror circuit and the second circuit, and the current flowing to the output side of the above current mirror circuit and A control transistor is provided that produces an output according to the current flowing through the second circuit, and a feedback circuit that feeds back the output of the control transistor to the gain control circuit to control the differential output thereof, and an automatic gain control circuit characterized in that a start level of gain control is set depending on the number of transistors in the third circuit.