JPH0554268B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device (hereinafter abbreviated as IC).

In recent years, CMOS (Complementary Metal Oxide)
EPROM (Electrically
Programmable Read Only Memory) is being developed. In this type of CMOS type EPROM, the gate electrode of each MOSFET is formed from the first layer of polysilicon, and the gate oxide film has two thicknesses, for example, 500 Å and 1000 Å. It has been proposed to use this for high-voltage FETs. However, with this structure, when converting to CMOS, the gate oxide film thickness
A mask for ion implantation must be added to control the threshold voltage of the 1000 Å FET, which increases the number of manufacturing steps. On the other hand, the gate oxide film thickness of the FET whose gate electrode is formed from the first polysilicon layer is approximately 800 Å, and the gate oxide film thickness of the other FET whose gate electrode is formed from the second polysilicon layer is approximately 1200 Å. It is known that In this case, in order to lower the threshold voltage of an FET with a thick gate oxide film, it is necessary to add a mask similar to the above, making manufacturing difficult, and increasing the breakdown voltage itself is not easy.

Therefore, an object of the present invention is to provide an IC that simplifies the manufacturing process and at the same time allows easy control of threshold voltage.
The purpose of this invention is to provide a method for manufacturing the same.

The configuration of the present invention to achieve this objective is as follows:
A step of selectively forming a field insulating film for demarcating an element formation region on the main surface of the semiconductor substrate, followed by forming a gate insulating film of a predetermined thickness on the surface of one of the demarcated element formation regions. forming a gate electrode on the insulating film; thereafter, forming a gate insulating film thinner than the gate insulating film on the surface of the other divided element forming region; The present invention is characterized in that it includes the steps of introducing an impurity having a desired conductivity type into the thin gate insulating film, and forming a gate electrode on the thin gate insulating film.

According to the present invention, which is comprised of such steps, since the gate insulating film for the high voltage MISFET and the gate electrode formed on the insulating film are formed in advance, the formation of the low voltage MISFET (forming a thin gate insulating film and forming the threshold voltage) is performed in advance. Introducing impurities into the substrate for voltage control) can be easily performed with good controllability.
In other words, when forming the low-voltage MISFET side, the high-voltage MISFET side is protected by a thicker gate insulating film than the gate insulating film on the low-voltage MISFET side.
Moreover, it is protected by a film called a gate electrode on the gate insulating film. Therefore, it is possible to form the low voltage MISFET side with good controllability without adding any process (addition of mask) and without affecting the high voltage MISFET side (changes in threshold voltage, etc.). be.

Hereinafter, an embodiment in which the present invention is applied to a CMOS type EPROM will be described in detail with reference to the drawings.

The EPROM according to this example will be explained along with its manufacturing process.

First, as shown in FIG. 1, an N-type well 2 and a field SiO ₂ film 3 for element isolation are formed in a predetermined pattern on one main surface side of a P-type silicon substrate 1 according to known semiconductor manufacturing techniques. 4 in the diagram is this field
This is an oxidation-resistant mask (silicon nitride) used when forming SiO ₂ films using selective oxidation technology. field
With the SiO ₂ film 3, element area A for high voltage MISFET, element area B for memory, N-channel MISFET and P-channel that constitute CMOS
Element regions C and D for MISFET are separated.

Next, as shown in Figure 2, the mask 4 and the base
After removing the SiO ₂ film 5 by etching, the entire surface is thermally oxidized to form a relatively thick gate oxide film 6 with a thickness of 750 Å.
is grown over the entire device area.

Next, as shown in FIG. 3, the entire surface is irradiated with an ion beam 7 of P-type impurities, such as boron, at an energy of 75 KeV and a dose of 2×10 ¹¹ /cm ² to implant boron ions through the gate oxide film 6. A boron implanted region 8 is formed directly below. By this boron implantation, the gate oxide film 6 is used.
The threshold voltage of MISFET is controlled to be low, around 0.5V.

Next, as shown in FIG. 4, impurity-doped (low resistance) polysilicon grown on the entire surface using chemical vapor deposition technology is patterned by etching to form a first layer of polysilicon on the gate oxide film 6 in device regions A and B. A gate electrode 9 and a floating gate layer 10 made of silicon are respectively formed.

Next, as shown in FIG.
Then, using the field SiO ₂ film 3 as a mask, SiO ₂ is etched to completely remove the gate oxide film 6 in the device regions C and D.

Next, as shown in FIG. 6, by thermally oxidizing the entire surface, a relatively thin gate oxide film 11 with a thickness of 500 Å is grown in device regions C and D. Element area A
In this case, a film thickness of 500 Å is applied on both sides of the gate oxide film 6.
SiO ₂ film 11 of 1000 Å thick is simultaneously formed on the surface of each polysilicon layer 9 and 11.
A SiO ₂ film 12 grows.

Next, as shown in Figure 7, the entire surface is irradiated with an ion beam 13 of P-type impurity, such as boron, at an energy of 30 KeV and a dose of 4 x 10 ¹¹ /cm ² to form a thin layer.
Boron ions are implanted into the substrate side through the SiO ₂ film 11. As a result, boron 14 is implanted into the element regions C and D so as to overlap with the boron implanted region 8 described above (double implantation), thereby increasing the boron concentration. This double implantation of boron controls the threshold voltage of the MISFET using the gate oxide film 11 to be as low as about 0.5V. In order to obtain this low threshold voltage, it is necessary to take into account the phenomenon that the implanted boron is eaten up by the SiO ₂ film 11, but boron is implanted at a high concentration under the SiO ₂ film 11 by the double implantation. Therefore, it is possible to sufficiently compensate for boron being eaten away and maintain a sufficient boron concentration.

Next, as shown in FIG. 8, a second layer of impurity-doped low-resistance polysilicon is grown on the entire surface using chemical vapor deposition technology, and this is patterned by etching to form a second layer in device regions B, C, and D. A polysilicon control gate electrode 15 and CMOS gate electrodes 16 and 17 are formed, respectively. In Figure 8, each gate electrode is used as a mask to remove the underlying layer.
A state in which the SiO ₂ films 11 and 12 have been etched, and the floating gate 10 and the SiO ₂ film 6 under the control gate electrode 15 have also been etched (overlapped) is shown. Note that the boron double implant area (8+14) shown in Figure 7 is + in Figure 8.
It is indicated by mark 18.

Next, as shown in FIG. 9, the entire surface is lightly thermally oxidized to form a SiO ₂ film 19 on the silicon and polysilicon surfaces.
Grow 20.

Next, as shown in FIG. 10, N-type impurities (for example, phosphorus) and P-type impurities (for example, boron) are alternately implanted using a known ion implantation technique using each gate electrode as part of a mask. As a result, N ⁺ type diffusion regions 21, 22, 2 as source or drain regions are formed in the element regions A, B, and C.
3 and 24, 25 and 26, and P ⁺ type diffusion regions 27 and 28 as source or drain regions are formed in the element region D.

Next, as shown in FIG. 11, a phosphosilicate glass film 29 is deposited on the entire surface using chemical vapor deposition technology.
is processed by photo etching to open each contact hole, and the aluminum deposited by vacuum evaporation technique is further processed by photo etching to form each aluminum wiring 30, 31, 32 deposited in each of the contact holes. .

Through the above process, the following four types of
A CMOS type EPROM with MISFET is created.

MOS1: N with a relatively thick gate oxide film 6 of 750 Å and a low concentration of boron doped in the channel, high breakdown voltage and low threshold voltage (0.5V).
Channel MISFET.

MOSm: A low threshold memory element having a relatively thick gate oxide film of 750 Å and having a two-layer polysilicon gate structure including a floating gate 10 and a control gate 15.

MOS2: N-channel MISFET that has a relatively thin gate oxide film 11 of 500 Å, the channel portion is doped with boron at a high concentration, and constitutes a high-speed CMOS with MOS3.

MOS3: A low threshold voltage P-channel MISFET that has a relatively thin gate oxide film 11 of 500 Å, the channel portion is heavily doped with boron, and constitutes a high-speed CMOS with MOS2.

As described above, according to this embodiment, both the MOS1 and the memory element, which have the first layer polysilicon as a gate, have a relatively thick gate oxide film, and have a channel portion doped with boron at a low concentration, have a low threshold. It shows high voltage resistance and high breakdown voltage. This allows the gate oxide film to be selectively thickened and at the same time
Since boron ion implantation is performed only once, it can be achieved with good reproducibility. On the other hand, MOS3, which uses the second layer of polysilicon as a gate, has a relatively thin gate oxide film, and has a channel portion doped with boron at a high concentration, achieves low threshold and high speed.
Can create CMOS. This is because the gate oxide film is selectively thinned and boron ions are implanted twice.

In this way, various types of MOS can be easily manufactured without adding masks, and their threshold voltages can be easily controlled by selective implantation of boron, and each element can be manufactured with high density. can.

Note that in the above example, the thickness of the gate oxide film of each MOS is not limited to the above, and may be varied variously. Further, the conductivity type of each of the semiconductor regions described above may be converted to the opposite type. Furthermore, in addition to EPROM, the present invention also applies to ICs made of MISFETs that have high breakdown voltage, low threshold voltage, and high speed performance.
Generally applicable.

[Brief explanation of the drawing]

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 are according to embodiments of the present invention. 3A and 3B are cross-sectional views showing a method for manufacturing an EPROM in order of steps; FIG. In addition, in the symbols shown in the drawings, 6...relatively thick gate oxide film, 7 and 13... boron ion beam, 8, 14 and 18... boron implantation region, 9 and 10... first layer polysilicon gate ,
11... Relatively thin gate oxide film, 15, 16 and 17... Second layer polysilicon gate, MOS1
...N-channel with high withstand voltage and low threshold voltage
MISFET, MOSm...2-layer polysilicon structure memory element, MOS2...N channel for CMOS
MISFET, MOS3...P-channel MISFET with low threshold voltage for CMOS.

Claims (1)

[Claims] 1. MISFET as a memory cell having a control gate and a floating gate on one main surface of a semiconductor substrate, a high breakdown voltage MISFET, and a low breakdown voltage
A step of selectively forming a field insulating film for demarcating the element formation regions in which each MISFET is to be formed, forming a gate insulating film of a predetermined thickness on the surface of each demarcated element formation region; introducing an impurity having the same conductivity type as the semiconductor substrate into the respective regions through the film; A step of forming a single layer of gate electrodes, and then exposing the surface of the device region where a low breakdown voltage MISFET is to be formed in the divided device formation region, and depositing a gate insulator thinner than the gate insulating film on the exposed surface. forming an interlayer insulating film by thermal oxidation on the surface of the first layer gate electrode of the MISFET serving as the memory cell; introducing an impurity having the same conductivity type as the semiconductor substrate through the film; forming a second layer gate electrode on the interlayer insulating film on the surface of the first layer gate electrode and on the thin gate insulating film, respectively; A method of manufacturing a semiconductor integrated circuit device, comprising: