JPH0554694B2 - - Google Patents

Info

Publication number
JPH0554694B2
JPH0554694B2 JP60501419A JP50141985A JPH0554694B2 JP H0554694 B2 JPH0554694 B2 JP H0554694B2 JP 60501419 A JP60501419 A JP 60501419A JP 50141985 A JP50141985 A JP 50141985A JP H0554694 B2 JPH0554694 B2 JP H0554694B2
Authority
JP
Japan
Prior art keywords
chip
leads
forming
row
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP60501419A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61501538A (ja
Inventor
Danieru Jei Kuin
Uein Ei Maruhorando
Robaato Eichi Bondo
Maikeru Ei Ora
Jerii Esu Kapuruzu
Iria Eru Tsuitofuisukii
Baabara Aaru Mozudozen
Chaaruzu Efu Herudo
Rinda Esu Uiruson
Ien Tei Guuien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of JPS61501538A publication Critical patent/JPS61501538A/ja
Publication of JPH0554694B2 publication Critical patent/JPH0554694B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP60501419A 1984-03-22 1985-03-19 集積回路に電気リードを取付ける方法 Granted JPS61501538A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59218684A 1984-03-22 1984-03-22
US592186 1984-03-22

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5064660A Division JPH0719792B2 (ja) 1984-03-22 1993-03-01 集積回路

Publications (2)

Publication Number Publication Date
JPS61501538A JPS61501538A (ja) 1986-07-24
JPH0554694B2 true JPH0554694B2 (de) 1993-08-13

Family

ID=24369668

Family Applications (2)

Application Number Title Priority Date Filing Date
JP60501419A Granted JPS61501538A (ja) 1984-03-22 1985-03-19 集積回路に電気リードを取付ける方法
JP5064660A Expired - Fee Related JPH0719792B2 (ja) 1984-03-22 1993-03-01 集積回路

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP5064660A Expired - Fee Related JPH0719792B2 (ja) 1984-03-22 1993-03-01 集積回路

Country Status (4)

Country Link
EP (1) EP0179802A4 (de)
JP (2) JPS61501538A (de)
KR (1) KR960009090B1 (de)
WO (1) WO1985004518A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900007231B1 (ko) * 1986-09-16 1990-10-05 가부시키가이샤 도시바 반도체집적회로장치
JPH07111971B2 (ja) * 1989-10-11 1995-11-29 三菱電機株式会社 集積回路装置の製造方法
EP1600249A1 (de) 2004-05-27 2005-11-30 Koninklijke Philips Electronics N.V. Lotzusammensetzung und Methode der Produktion eines Lötmittelanschlusses
US8169081B1 (en) 2007-12-27 2012-05-01 Volterra Semiconductor Corporation Conductive routings in integrated circuits using under bump metallization
CN106604547B (zh) * 2016-11-22 2018-12-11 深圳市洁简达创新科技有限公司 一种无污染电子线路板制造工艺

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386008A (en) * 1964-08-31 1968-05-28 Cts Corp Integrated circuit
US3518751A (en) * 1967-05-25 1970-07-07 Hughes Aircraft Co Electrical connection and/or mounting arrays for integrated circuit chips
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
US4197555A (en) * 1975-12-29 1980-04-08 Fujitsu Limited Semiconductor device
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers

Also Published As

Publication number Publication date
EP0179802A1 (de) 1986-05-07
KR860700074A (ko) 1986-01-31
JPH0719792B2 (ja) 1995-03-06
WO1985004518A1 (en) 1985-10-10
JPH06318615A (ja) 1994-11-15
JPS61501538A (ja) 1986-07-24
EP0179802A4 (de) 1987-06-01
KR960009090B1 (ko) 1996-07-10

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Legal Events

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