JPH0556852B2 - - Google Patents
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- Publication number
- JPH0556852B2 JPH0556852B2 JP61147380A JP14738086A JPH0556852B2 JP H0556852 B2 JPH0556852 B2 JP H0556852B2 JP 61147380 A JP61147380 A JP 61147380A JP 14738086 A JP14738086 A JP 14738086A JP H0556852 B2 JPH0556852 B2 JP H0556852B2
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- Prior art keywords
- chamber
- substrate
- substrate temperature
- trisilane
- silicon film
- Prior art date
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Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、経時変化の少ない薄膜トランジス
タ等に用いるシリコン膜の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a silicon film used for thin film transistors and the like that undergoes little change over time.
この発明は、トリシラン以上の高次シランを用
いた熱CVDにより、高品質で安定なアモルフア
スシリコン膜を製造するものである。
This invention manufactures a high quality and stable amorphous silicon film by thermal CVD using a higher order silane than trisilane.
〔従来の技術〕
プラズマ等の荷電粒子によるダメージのないシ
リコン膜の製造方法に熱CVDがある。[Prior Art] Thermal CVD is a method for manufacturing silicon films that is not damaged by charged particles such as plasma.
従来、水素化アモルフアスシリコン膜を熱
CVD法で成膜する場合、原料ガスにモノシラン
（SiH4）を用いると基板温度を600〜650℃の高温
にする必要があり、膜中の構造欠陥を補償する結
合水素量が極めて少なく膜の特性が良くなかつ
た。ジシラン（Si2H6）を用いた場合、基板温度
400〜500℃で適当に水素を含むアモルフアスシリ
コン膜が形成できるとの報告が、Yoshinori
ASHIDAら（Yoshinori ASHIDA、Yasuyoshi
MISHIMA、Masataka HIROSE、Yukio
OSAKA and Kenichi KOJIMA、J.J.Appl.
Phys.23（1984）129）によりなされている。 Conventionally, hydrogenated amorphous silicon films were heated
When forming a film by the CVD method, if monosilane (SiH 4 ) is used as the raw material gas, the substrate temperature must be raised to a high temperature of 600 to 650°C, and the amount of bonded hydrogen to compensate for structural defects in the film is extremely small. The characteristics were not good. When using disilane (Si 2 H 6 ), the substrate temperature
Yoshinori reported that an amorphous silicon film containing appropriate hydrogen can be formed at 400 to 500℃.
ASHIDA et al. (Yoshinori ASHIDA, Yasuyoshi
MISHIMA, Masataka HIROSE, Yukio
OSAKA and Kenichi KOJIMA, JJAppl.
Phys. 23 (1984) 129).
しかし、従来のジシランによる熱CVD法では
基板加熱以外に、チヤンバーも加熱するホツトウ
オール型の反応装置を用いていた。ホツトウオー
ル型ではデポジシヨンレートは高いもののチヤン
バー内壁の不純物をシリコン膜中にとり込み易く
膜質の向上がむずかしい。また、気相反応により
基板表面にシリコン粒子が堆積し、表面が荒れて
しまうという問題があつた。
However, the conventional thermal CVD method using disilane uses a hot wall type reactor that not only heats the substrate but also heats the chamber. Although the hot wall type has a high deposition rate, impurities on the inner wall of the chamber are easily incorporated into the silicon film, making it difficult to improve the film quality. Another problem was that silicon particles were deposited on the substrate surface due to the gas phase reaction, resulting in a rough surface.
一方、チヤンバーは加熱せず基板のみを加熱す
るコールドウオール型の反応装置ではデポジシヨ
ンレートが低いという問題があつた。 On the other hand, a cold wall type reactor in which only the substrate is heated without heating the chamber has a problem in that the deposition rate is low.
そこで、この発明はコールドウオール型の反応
装置においても低い基板温度で十分なデポジシヨ
ンレートがあり、良好な電気特性をもつ安定なア
モルフアスシリコン膜の形成を目的としている。 Therefore, the object of the present invention is to form a stable amorphous silicon film having a sufficient deposition rate at a low substrate temperature and good electrical properties even in a cold wall type reactor.
この発明では、原料ガスにトリシラン以上の高
次シランを用い、熱CVDにおける成膜条件とシ
リコン膜の特性の関係を明らかにすることにより
問題を解決した。
In this invention, the problem was solved by using a higher-order silane higher than trisilane as the raw material gas and by clarifying the relationship between the film formation conditions in thermal CVD and the characteristics of the silicon film.
ジシランに比べトリシラン以上の高次シランは
反応性が高いので、十分なデポジシヨンレートが
あり、膜質に関係する基板温度、反応圧力等の成
膜条件を最適化することができる。
Since higher-order silanes such as trisilane and higher have higher reactivity than disilane, they have a sufficient deposition rate, and film forming conditions such as substrate temperature and reaction pressure, which are related to film quality, can be optimized.
まず、この発明に用いる装置例を第１図ａおよ
びｂにより説明する。
First, an example of the apparatus used in the present invention will be explained with reference to FIGS. 1a and 1b.
第１図ａにおいて、１はチヤンバーで、内部に
ヒーター等の基板加熱手段２を有し、熱伝導の良
いサセプター３が固定され、加熱される。サセプ
ター３上には石英板、ガラス板、ステンレス板、
シリコンウエハー等の基板４が載せられている
（下向き等の場合には止め金具等で固定される）。
さらに、基板４の近傍にガス吹出部５を形成し、
ガス供給手段６とチヤンバー１内を排気手段７が
チヤンバー１に接続されている。ガス供給手段６
からガス吹出部までの系はヒーター等により原料
ガスの沸点（トリシランでは53.1℃）以上の温度
に保たれている。このほか、必要に応じて、チヤ
ンバー１の側面に真空ゲージ、観察窓等が設けら
れ、冷却のための空冷ないしは水冷パイプが接続
されている。 In FIG. 1a, a chamber 1 has a substrate heating means 2 such as a heater inside, and a susceptor 3 having good thermal conductivity is fixed and heated. On the susceptor 3 are a quartz plate, a glass plate, a stainless steel plate,
A substrate 4 such as a silicon wafer is placed thereon (if it is facing downward, it is fixed with a stopper or the like).
Further, a gas blowing part 5 is formed near the substrate 4,
A gas supply means 6 and an exhaust means 7 are connected to the chamber 1 . Gas supply means 6
The system from the gas outlet to the gas outlet is kept at a temperature higher than the boiling point of the raw material gas (53.1°C for trisilane) using a heater or the like. In addition, if necessary, a vacuum gauge, an observation window, etc. are provided on the side surface of the chamber 1, and an air cooling or water cooling pipe for cooling is connected thereto.
第１図ｂは、基板加熱手段２にランプ加熱を用
いた場合で、チヤンバー１は光吸収の少ない石
英、サセプター３は光吸収の良いカーボン等の材
質のものを各々用いる。 FIG. 1b shows a case where lamp heating is used as the substrate heating means 2, the chamber 1 is made of quartz which absorbs little light, and the susceptor 3 is made of a material such as carbon which has good light absorption.
このような装置において基板温度を400℃程度
に加熱し、トリシラン以上の高次シランをチヤン
バー１内に導入すると、熱分解反応により、基板
４表面にアモルフアスシリコン膜を形成すること
ができる。この場合、チヤンバー１の壁面の温度
は200℃前後であるが、さらに冷却する場合は、
空気、N2ガス等をチヤンバー１外から吹きつけ
ればよい。以下にデポジシヨンの詳細な条件を示
す。 In such an apparatus, when the substrate temperature is heated to about 400° C. and higher-order silane of trisilane or higher is introduced into the chamber 1, an amorphous silicon film can be formed on the surface of the substrate 4 through a thermal decomposition reaction. In this case, the temperature of the wall surface of chamber 1 is around 200℃, but if further cooling is required,
Air, N2 gas, etc. can be blown from outside the chamber 1. Detailed conditions for deposition are shown below.
第２図は100％トリシランを用いた石英基板上
へのアモルフアスシリコン膜のデポジシヨンレー
トのデータの一例を示すものである。第３図で横
軸は基板温度Tsubの逆数（１／Ｋ）、縦軸はデポ
ジシヨンレート（Å／min）であり、△、□、
○、◇、▽印はそれぞれ反応圧力が１、２、５、
10、12Torrの場合である。10Torr、420℃で60
Å／minのデポジシヨンレートがあり、半導体素
子を生産するのに十分な値である。 FIG. 2 shows an example of data on the deposition rate of an amorphous silicon film on a quartz substrate using 100% trisilane. In Figure 3, the horizontal axis is the reciprocal of the substrate temperature Tsub (1/K), and the vertical axis is the deposition rate (Å/min), △, □,
○, ◇, and ▽ marks indicate reaction pressures of 1, 2, 5, and 1, respectively.
This is the case at 10 and 12 Torr. 60 at 10Torr, 420℃
It has a deposition rate of Å/min, which is sufficient for producing semiconductor devices.
H2、N2、He、Ar等の雰囲気ガスで希釈した
場合のデポジシヨンは、トリシランの分圧が第３
図の反応圧力と同じなら、デポジシヨンレートも
ほぼ等しくなる。 When the deposition is diluted with an atmospheric gas such as H 2 , N 2 , He, or Ar, the partial pressure of trisilane is
If the reaction pressure is the same as shown in the figure, the deposition rate will also be approximately the same.
第３図は100％トリシランを用いて反応圧力
5Torrの場合の光学バンドギヤツプと結合水素量
の基板温度依存性の一例を示したものである。基
板温度が480℃以下では光学バンドギヤツプは約
1.65eV、結合水素量は約7.5％でほぼ一定である。
基板温度が480℃を越える温度では光学バンドギ
ヤツプ、結合水素量ともに減少する。これよりト
リシラン以上の高次シランの熱CVDでは基板温
度480℃を越える温度で水素脱離が起こることが
解つた。 Figure 3 shows the reaction pressure using 100% trisilane.
This figure shows an example of the substrate temperature dependence of the optical bandgap and the amount of bound hydrogen at 5 Torr. When the substrate temperature is below 480℃, the optical bandgap is approximately
1.65eV, and the amount of bound hydrogen is approximately constant at approximately 7.5%.
When the substrate temperature exceeds 480°C, both the optical bandgap and the amount of bound hydrogen decrease. This shows that in thermal CVD of higher order silanes than trisilane, hydrogen desorption occurs at substrate temperatures exceeding 480°C.
第４図は、100％トリシランを用いて反応圧力
5Torrの場合の暗導電率（●印）とAM１スペク
トラム60ｍＷ／cm2の光照射での光導電率（○印）
の基板温度依存性を示したものである。光導電率
は高くないが、光導電率と暗導電率の比は３桁以
上ある。また、基板温度480℃を越える温度では、
水素脱離により光導電率、暗導電率ともに低下す
る。 Figure 4 shows the reaction pressure using 100% trisilane.
Dark conductivity at 5 Torr (● mark) and photoconductivity under AM1 spectrum 60 mW/cm 2 light irradiation (○ mark)
This figure shows the substrate temperature dependence of . Although the photoconductivity is not high, the ratio of photoconductivity to dark conductivity is more than three orders of magnitude. In addition, when the substrate temperature exceeds 480℃,
Both photoconductivity and dark conductivity decrease due to hydrogen desorption.
第５図は、赤外吸収特性の一例を示したもので
ある。一般に2000cm-1付近にピークを持つSiH結
合の伸縮振動と2100cm-1付近にピークを持つ
SiH2結合の伸縮振動が観察されるが、トリシラ
ンの熱CVDによるアモルフアスシリコン膜では
SiH2結合のピークはほとんど観測されず、SiH
結合が主であり良質な膜であるといえる。 FIG. 5 shows an example of infrared absorption characteristics. Generally, the stretching vibration of SiH bond has a peak around 2000 cm -1 and the peak around 2100 cm -1
Stretching vibrations of SiH 2 bonds are observed, but this is not the case in amorphous silicon films produced by thermal CVD of trisilane.
Almost no SiH 2 bond peak was observed, and SiH
It can be said that it is a high-quality film, mainly due to bonding.
以上のデポジシヨンのデータを利用して作成し
た薄膜トランジスタの断面図の一例を第６図に示
す。低抵抗ｐ型シリコン基板を利用したゲート６
と、前記シリコン基板を1100℃、dryO2雰囲気中
で熱酸化した約900Åのゲート絶縁膜７の上に、
トリシラン以上の高次シランの熱CVDによるノ
ンドープアモルフアスシリコン膜８を約500Åデ
ポジシヨンする。さらにn+アモルフアスシリコ
ン層とNi等の金属層の二層よりなるソース９及
びドレイン１０を形成する。 FIG. 6 shows an example of a cross-sectional view of a thin film transistor created using the above deposition data. Gate 6 using low resistance p-type silicon substrate
Then, on the gate insulating film 7 of about 900 Å, which is obtained by thermally oxidizing the silicon substrate at 1100° C. in a dryO 2 atmosphere,
A non-doped amorphous silicon film 8 of about 500 Å is deposited by thermal CVD using higher order silane than trisilane. Further, a source 9 and a drain 10 are formed of two layers: an n + amorphous silicon layer and a metal layer such as Ni.
第７図は実際の薄膜トランジスタの出力特性の
一例である。ゲート・ソース電圧は20〜30Vまで
2Vステツプで変化させ、チヤネル幅Ｗとチヤネ
ル長Ｌの比はＷ／Ｌ＝40である。ソース・ドレイ
ン電圧は０→10→0Vと掃引した場合のヒステリ
シスは非常に小さく安定である。この薄膜トラン
ジスタのON／OFF電流比は６桁以上あり、飽和
領域から求めたしきい値電圧と電子移動度は各々
18V、0.1cm2／Ｖ・Ｓと良好なものであつた。 FIG. 7 shows an example of the output characteristics of an actual thin film transistor. Gate-source voltage up to 20-30V
It is changed in 2V steps, and the ratio of channel width W to channel length L is W/L=40. When the source-drain voltage is swept from 0 to 10 to 0V, the hysteresis is very small and stable. The ON/OFF current ratio of this thin film transistor is more than 6 orders of magnitude, and the threshold voltage and electron mobility determined from the saturation region are respectively
The voltage was good at 18V and 0.1cm 2 /V·S.
ドレイン電流Idの時間変化を、モノシランのプ
ラズマCVDで作製した薄膜トランジスタと比較
して第８図に示す。プラズマCVD試料は熱CVD
と同じチヤンバーを用い、基板温度300℃、反応
圧力0.7Torr、高周波電力10Wで製膜したもので
ある。第８図の横軸は、ドレイン電流を1μA流す
のに必要なバイアスを印加してからの時間、縦軸
のドレイン電流の初期値Id（０）に対する各時間
における値Idの比である。実線が熱CVD、破線
がプラズマCVDによる薄膜トランジスタの場合
である。熱CVDによる薄膜トランジスタの方が、
プラズマCVDによるものよりドレイン電流の時
間変化が小さく安定である。 FIG. 8 shows the temporal change in drain current Id in comparison with that of a thin film transistor fabricated by monosilane plasma CVD. Plasma CVD samples are thermal CVD
Using the same chamber as above, the film was formed at a substrate temperature of 300°C, reaction pressure of 0.7 Torr, and high-frequency power of 10 W. The horizontal axis of FIG. 8 is the time after applying the bias necessary to cause a drain current of 1 μA to flow, and the vertical axis is the ratio of the value Id at each time to the initial value Id (0) of the drain current. The solid line is for thermal CVD, and the broken line is for plasma CVD thin film transistors. Thin film transistors made by thermal CVD are better.
Compared to plasma CVD, the drain current changes over time and is more stable.
第９図ａ及びｂはそれぞれ実際のデポジシヨン
の手順の一例を示したもので、横軸は時間、縦軸
はチヤンバー圧と基板温度を示している。第９図
ａは100％トリシランの場合で、真空引きしたチ
ヤンバー１にトリシランを導入するとデポジシヨ
ンが始まる。この時、チヤンバー圧が急に増加す
ると基板加熱手段２とサセプター３、及びサセプ
ター３と基板４間の熱伝導が良くなり、基板温度
が20℃程度も上昇する。しばらくすると温度制御
が追従し、基板温度が安定する。チヤンバー圧が
10Torr以上でこの現象は顕著である。このデポ
ジシヨン開始時の基板温度変化は、デポジシヨン
時間が短かい場合、膜厚の制御や膜質の均一性を
悪くする。 FIGS. 9a and 9b each show an example of an actual deposition procedure, with the horizontal axis representing time and the vertical axis representing chamber pressure and substrate temperature. FIG. 9a shows the case of 100% trisilane, and when trisilane is introduced into the evacuated chamber 1, deposition begins. At this time, if the chamber pressure suddenly increases, heat conduction between the substrate heating means 2 and the susceptor 3, and between the susceptor 3 and the substrate 4 improves, and the substrate temperature increases by about 20°C. After a while, the temperature control will follow suit and the substrate temperature will stabilize. Chamber pressure
This phenomenon is noticeable above 10 Torr. This change in substrate temperature at the start of deposition deteriorates control of film thickness and uniformity of film quality when the deposition time is short.
そこで、第９図ｂに示すように、あらかじめ
H2、N2、He、Ar等の希釈ガスを10Torr以上チ
ヤンバー１内に導入しておき、基板温度が安定し
てからトリシランを導入すると、基板温度の変化
は１℃以下におさえることができ、安定なデポジ
シヨンを行うことができる。この安定化効果は
5Torr前後のチヤンバー圧でも認められた。 Therefore, as shown in Figure 9b,
If a diluent gas such as H 2 , N 2 , He, or Ar is introduced into chamber 1 at a rate of 10 Torr or more, and trisilane is introduced after the substrate temperature has stabilized, the change in substrate temperature can be kept to 1°C or less. , stable deposition can be performed. This stabilizing effect is
It was also observed at chamber pressures around 5 Torr.
以上詳細に説明したように、この発明はトリシ
ラン以上の高次シランを用いて基板温度480℃以
下で熱CVDを行つた場合、電気特性の良い安定
なアモルフアスシリコン膜が得られる利点があ
る。
As described in detail above, the present invention has the advantage that a stable amorphous silicon film with good electrical properties can be obtained when thermal CVD is performed at a substrate temperature of 480° C. or lower using a higher order silane than trisilane.
また、雰囲気ガスをあらかじめチヤンバー内に
導入し、基板温度が安定した後に原料ガスを導入
して熱CVDを行うと、成膜時の基板温度変化を
非常に小さくすることができる。 Furthermore, if an atmospheric gas is introduced into the chamber in advance and the source gas is introduced after the substrate temperature has stabilized to perform thermal CVD, changes in the substrate temperature during film formation can be made very small.
さらに、低温でしかも荷電粒子のダメージのな
いプロセスであることから、LSI等のプロセスと
組合せた場合でも、既に形成済みの他の素子に悪
い影響を与えることがないことは明白である。 Furthermore, since it is a low-temperature process and does not cause damage from charged particles, it is clear that it will not adversely affect other devices that have already been formed, even when combined with processes such as LSI.
第１図ａはこの発明に用いるヒーター加熱によ
る装置の断面略図、第１図ｂは同様にランプ加熱
による装置の断面略図、第２図はこの発明の100
％トリシランを用いた熱CVDのデポジシヨンレ
ートの基板温度依存性を示す図、第３図は、この
発明の光学バンドギヤツプと水素含有率の基板温
度依存性を示す図、第４図はこの発明の導電率の
基板温度依存性を示す図、第５図はこの発明のシ
リコン膜の赤外吸収特性図、第６図は第２図から
第５図までのデータを利用して作製した薄膜トラ
ンジスタの断面図、第７図は第６図の薄膜トラン
ジスタの出力特性図、第８図は同じく、ドレイン
電流の時間変化を示す図、第９図ａは100％トリ
シランを用いた場合のデポジシヨンの手順例を示
す図、第９図ｂは同様に雰囲気ガスで希釈した場
合のデポジシヨンの手順例を示す図である。図
中、１はチヤンバー、２は基板加熱手段、３はサ
セプタ、４は基板、５はガス吹出部、６はガス供
給手段、７は排気手段、８はシリコン膜、９はソ
ース、１０はドレインである。
FIG. 1a is a schematic cross-sectional view of a device heated by a heater used in this invention, FIG. 1b is a schematic cross-sectional view of a device heated by a lamp, and FIG.
3 is a diagram showing the dependence of the deposition rate on the substrate temperature in thermal CVD using % trisilane, FIG. 3 is a diagram showing the dependence of the optical bandgap and hydrogen content on the substrate temperature of the present invention, and FIG. A diagram showing the dependence of conductivity on substrate temperature, Figure 5 is a diagram of infrared absorption characteristics of the silicon film of the present invention, and Figure 6 is a cross section of a thin film transistor manufactured using the data from Figures 2 to 5. Figure 7 is an output characteristic diagram of the thin film transistor shown in Figure 6, Figure 8 is a diagram showing the change in drain current over time, and Figure 9a is an example of the deposition procedure when using 100% trisilane. 9B are diagrams showing an example of the deposition procedure in the case of dilution with atmospheric gas. In the figure, 1 is a chamber, 2 is a substrate heating means, 3 is a susceptor, 4 is a substrate, 5 is a gas blowing part, 6 is a gas supply means, 7 is an exhaust means, 8 is a silicon film, 9 is a source, 10 is a drain It is.
Claims (1)
段とガス供給手段とが接続された装置を用い、原
料ガスとしてトリシラン（Si3H8）以上の高次シ
ランを前記チヤンバー内に導入し、基板温度480
℃以下で、かつ前記チヤンバー壁面の温度を前記
基板温度より低く保ち、熱CVDによりシリコン
膜を成長させることを特徴とするシリコン膜の製
造方法。 ２ 雰囲気ガス（H2、N2、He、Ar等）をあら
かじめ前記チヤンバー内に導入し、基板温度が安
定した後に、原料ガスを導入してシリコン膜を成
長させることを特徴とする特許請求範囲第１項記
載のシリコン膜の製造方法。[Claims] 1. Using a device in which an exhaust means and a gas supply means are connected to a chamber containing a substrate heating means, high-order silane of trisilane (Si 3 H 8 ) or higher is introduced into the chamber as a raw material gas. Introduced, substrate temperature 480℃
A method for producing a silicon film, characterized in that the silicon film is grown by thermal CVD at a temperature of 0.degree. 2. The scope of claims characterized in that an atmospheric gas (H 2 , N 2 , He, Ar, etc.) is introduced into the chamber in advance, and after the substrate temperature is stabilized, a source gas is introduced to grow a silicon film. 2. The method for manufacturing a silicon film according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14738086A JPS633414A (en) | 1986-06-24 | 1986-06-24 | Manufacture of silicon film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14738086A JPS633414A (en) | 1986-06-24 | 1986-06-24 | Manufacture of silicon film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS633414A JPS633414A (en) | 1988-01-08 |
| JPH0556852B2 true JPH0556852B2 (en) | 1993-08-20 |
Family
ID=15428933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14738086A Granted JPS633414A (en) | 1986-06-24 | 1986-06-24 | Manufacture of silicon film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS633414A (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2889924B2 (en) * | 1989-06-30 | 1999-05-10 | 日本電信電話株式会社 | Manufacturing method of thin film field effect transistor |
| US5614257A (en) * | 1991-08-09 | 1997-03-25 | Applied Materials, Inc | Low temperature, high pressure silicon deposition method |
| JP3121131B2 (en) * | 1991-08-09 | 2000-12-25 | アプライド マテリアルズ インコーポレイテッド | Low temperature and high pressure silicon deposition method |
| AU2002306436A1 (en) | 2001-02-12 | 2002-10-15 | Asm America, Inc. | Improved process for deposition of semiconductor films |
| US7026219B2 (en) | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| US6815007B1 (en) | 2002-03-04 | 2004-11-09 | Taiwan Semiconductor Manufacturing Company | Method to solve IMD-FSG particle and increase Cp yield by using a new tougher UFUN season film |
| US7294582B2 (en) | 2002-07-19 | 2007-11-13 | Asm International, N.V. | Low temperature silicon compound deposition |
| WO2004009861A2 (en) | 2002-07-19 | 2004-01-29 | Asm America, Inc. | Method to form ultra high quality silicon-containing compound layers |
| US7186630B2 (en) | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| US7092287B2 (en) | 2002-12-18 | 2006-08-15 | Asm International N.V. | Method of fabricating silicon nitride nanodots |
| US7629270B2 (en) | 2004-08-27 | 2009-12-08 | Asm America, Inc. | Remote plasma activated nitridation |
| US7253084B2 (en) | 2004-09-03 | 2007-08-07 | Asm America, Inc. | Deposition from liquid sources |
| US7966969B2 (en) | 2004-09-22 | 2011-06-28 | Asm International N.V. | Deposition of TiN films in a batch reactor |
| US7427571B2 (en) | 2004-10-15 | 2008-09-23 | Asm International, N.V. | Reactor design for reduced particulate generation |
| US7674726B2 (en) | 2004-10-15 | 2010-03-09 | Asm International N.V. | Parts for deposition reactors |
| US7553516B2 (en) | 2005-12-16 | 2009-06-30 | Asm International N.V. | System and method of reducing particle contamination of semiconductor substrates |
| US7691757B2 (en) | 2006-06-22 | 2010-04-06 | Asm International N.V. | Deposition of complex nitride films |
| US7851307B2 (en) | 2007-08-17 | 2010-12-14 | Micron Technology, Inc. | Method of forming complex oxide nanodots for a charge trap |
| US9054206B2 (en) | 2007-08-17 | 2015-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US7833906B2 (en) | 2008-12-11 | 2010-11-16 | Asm International N.V. | Titanium silicon nitride deposition |
| US9837271B2 (en) | 2014-07-18 | 2017-12-05 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| US9443730B2 (en) | 2014-07-18 | 2016-09-13 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| US10460932B2 (en) | 2017-03-31 | 2019-10-29 | Asm Ip Holding B.V. | Semiconductor device with amorphous silicon filled gaps and methods for forming |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59126680A (en) * | 1983-01-11 | 1984-07-21 | Mitsui Toatsu Chem Inc | Amorphous silicon solar battery and manufacture thereof |
-
1986
- 1986-06-24 JP JP14738086A patent/JPS633414A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS633414A (en) | 1988-01-08 |
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