JPH0560834A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Purpose] First, to facilitate timing design during scanning and reduce constraints on scan design. Secondly, it is possible to prevent erroneous operation at the time of mode switching and reduce restrictions on scan design. [Structure] Scan storage elements 111 to 114 and a mode select terminal 10 for switching between a normal operation and a scan operation.
4 and by providing the delay element 110 on the test clock signal line 140, a time difference occurs between the test clock signal and the normal clock signal, and the signal of the external input terminal 103 is changed before switching from the scan mode to the normal mode. Even if the test clock signal is switched to the normal clock signal, the test clock signal reaches the scan chain later than the signal of the external input terminal 103 by the delay time of the delay element 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for efficiently performing circuit failure inspection by scan-in and scan-out.

[0002]

2. Description of the Related Art Conventionally, timing guarantee at the time of a scan operation of a scan storage element has been solved by adopting a master storage system as the scan storage element. A conventional semiconductor integrated circuit using this master-slave system will be described with reference to FIGS.

FIG. 6 is a circuit diagram of a conventional semiconductor integrated circuit. In FIG. 6, 101 is an external input terminal that also serves as a normal external input terminal and a scan-in terminal, 102 is an external input terminal that also serves as a normal external input terminal and a data select terminal, and 104 is a normal operation and a scan operation. Mode select terminal for switching between, an external output terminal 105, an AND gate 106, an inverter 107,
08 is a combinational circuit, 109 is a selector that selects normal external output data and scan-out data, 121 is a scan-out signal line of the scan storage element 603 and a scan-in signal of the scan storage element 604, and 122 is a scan of the scan storage element 604. Out and scan-in signal line of scan storage element 605, 123 scan-out signal line of scan storage element 605 and scan-in signal line of scan storage element 606, 124 scan-out signal line of scan storage element 606, and 130 AND
An output signal line of the gate 106, 131 is a clock input signal line of the scan storage elements 603 and 604, 132 is a clock input signal line of the scan storage elements 605 and 606, 60
1 is a normal clock input terminal and a master storage element 216
(FIG. 7) is an external input terminal which also serves as a test clock input terminal for operating, and 602 is a slave storage element 703.
External input terminals for a test clock for operating (FIG. 7), 610 and 611 are scan storage elements 603 to 606.
The signal line of the test clock input of is shown.

FIG. 7 shows the scan storage elements 603 to 6 of FIG.
It is a circuit block diagram which shows the specific example of 06. In FIG.
201 is a normal data input terminal, 202 is a scan-in terminal, and 203 is a signal for selecting a signal of the normal data input terminal 201 (input data signal) and a signal of the scan-in terminal 202 (scan-in data signal). Data select terminal, 204 is a normal clock input terminal, 20
6 is a mode select terminal for selecting the normal mode and the scan mode, 207 is a scan out terminal, 208 is a normal data output terminal, and 210 is a data select terminal 203.
A selector 211 which outputs a normal input data signal when the signal value of is 0, and a scan-in data signal when the signal value of the data select terminal 203 is 1;
Is the signal of the normal clock input terminal 204 when the signal value of the mode select terminal 206 is "0" (normal clock signal)
Is output and the signal (test clock signal) of the test clock input terminal 701 is output when the signal value of the mode select terminal 206 is “1”, 216 is a master storage element, 220 is an output signal line of the selector 211, 221 is an output signal line of the selector 210, 701 is a test clock input terminal for driving the master storage element 216 in the scan mode, 702 is a test clock input terminal for driving the slave storage element 703 in the scan mode, and 704 is a slave storage element 703. The test clock input signal line is shown.

FIG. 8 is a time chart for explaining the operation of the semiconductor integrated circuit configured as described above. In FIG. 8, reference numerals 801 to 804 denote signal waveforms on the signal line 220 inside the scan storage elements 603 to 606, respectively. Other reference numerals indicate signals on the signal lines or external terminals that match the reference numerals in FIG. The operation of this semiconductor integrated circuit will be described below with reference to FIGS.

When the signal value of the mode select terminal 104 is "0", the normal mode is set and normal operation is performed. That is, the selector 211 outputs the signal of the normal clock input terminal 204, and the signal value of the data select terminal 203 is always “0” in the normal mode. Therefore, the selector 210 outputs the signal of the normal data input terminal 201. Therefore, the scan storage elements 603 to 606 act as normal storage elements that operate with a normal clock signal, a normal input data signal, and a normal output data signal.

When the signal value of the mode select terminal 104 is "1", the scan mode is set, and the selector 211
Outputs a signal from the test clock input terminal 701, and the selector 109 outputs a scan-out signal from the scan storage element 606. Further, the selectors 210 and 211 select the signals of the scan-in terminal 202 and the test clock input terminal 701, respectively, and the master storage element 216 operates by the clock signal of the external input terminal 601. The slave storage element 703 operates according to the clock signal from the external input terminal 602. Therefore, first, the external input terminal 60
The output value of the master storage element 216 is set to the shift-in signal value by operating the clock signal of 1 and the output value of the slave storage element 703 is set to the shift-in signal value of the master storage element 216 by operating the clock signal of the external input terminal 602. Use as output value. As a result, the scan data is transferred to the master storage element 21 due to the delay of the clock signal or the like.
Even when skipping over 6, scan data is temporarily stopped in the slave storage element 703, so that it is possible to prevent the risk of jumping over the scan data storage element.

[0008]

However, according to the above conventional configuration, the design of the test clock line for adjusting the timing of the scan operation of each of the scan storage elements 603 to 606 has been manually performed, and therefore, the test clock lines having different phases cannot be used. When designing a scan chain that includes storage elements that operate with clock signals, a complex test clock signal design is required to operate all scan storage elements in the scan chain in the same phase of one test clock signal. The required and complicated scan design makes it extremely troublesome, which is a major obstacle to automation of the scan design.

Further, in order to suppress an increase in the number of external terminals due to the addition of the test external terminal, only the mode select terminal 104 for switching between the normal operation and the scan operation is used as the test external terminal. Prepare,
The other terminals for the scan test are also used as the external terminals for the normal operation, and the external terminals that are also used by the mode switching by the mode select terminal 104 are used separately for the normal operation and the scan operation. But,
This may cause a malfunction when one scan chain includes storage elements that operate at different phases of the clock signal during normal operation. That is, since the external input terminal 601 serves both as the normal clock input terminal and the test clock input terminal for operating the master storage element 216, the signal value of the external input terminal 601 is changed before the scan mode is switched to the normal mode. It is necessary to restore the signal value used in scan mode to the signal value used in normal mode. Therefore, the waveform is 60 in FIG.
If the last signal value used in the scan mode is "1" and the signal value must be "0" when switching to the normal mode, the mode is changed from the scan mode to the normal mode. Before switching to the mode, the signal value must be changed from "1" to "0". At this time, in the clock signal of the master memory element 216 in the scan memory element 604, an unintended fall of the signal occurs when the scan mode is switched to the normal mode, and data destruction indicated by 824 in FIG. 8 occurs. .. Also, in the scan storage element 605, an unintended rising edge signal of the clock signal similarly occurs, and the scan storage element 605 has a voltage of 83 in FIG.
Data destruction shown in 4 occurs.

A first object of the present invention is to provide a semiconductor integrated circuit which facilitates timing design at the time of scanning and reduces restrictions on scan design. A second object is to provide a semiconductor integrated circuit capable of preventing malfunction (data destruction) at the time of mode switching and reducing restrictions on scan design.

[0011]

A semiconductor integrated circuit according to claim 1 has a plurality of normal clock input terminals for performing a normal operation, and a test clock input terminal and a test clock output terminal for performing a scan operation. In the scan storage element, the delay element is incorporated between the test clock input terminal and the test clock output terminal.

According to another aspect of the semiconductor integrated circuit of the present invention, one external input terminal also serves as the input of the normal clock and the test clock, and the delay element is provided on the internal test clock signal line. According to another aspect of the semiconductor integrated circuit of the present invention, one external input terminal also serves as an input of a normal clock and a test clock, and holds a signal value of an internal test clock signal line when switching from scan operation to normal operation. Is provided.

[0013]

According to the structure of claim 1, a delay element is provided between the test clock input terminal and the test clock output terminal in the plurality of scan storage elements, so that each scan can be performed when designing a scan chain. The scan terminal of the storage element can be connected to the scan terminal of the corresponding scan storage element to perform the scan design in which the timing of the scan operation is adjusted.

According to the second aspect of the invention, the input of the normal clock and the test clock is shared by one external input terminal, and the delay element is provided on the internal test clock signal line. A time difference occurs between the scan modes, a malfunction (data destruction) at the time of mode switching from the scan mode to the normal mode can be prevented, and any storage element that operates with clocks of different phases can be used as one scan chain. it can.

According to the third aspect of the present invention, the input of the normal clock and the test clock is shared by one external input terminal, and when the scan operation is switched to the normal operation, the signal value of the internal test clock signal line is changed. By providing the holding means, it is possible to prevent a malfunction (data destruction) at the time of switching the mode from the scan mode to the normal mode, and use one storage chain that operates with arbitrary storage elements that operate with clocks of different phases. be able to.

[0016]

【Example】

[First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, 101 is an external input terminal that also serves as a normal external input terminal and a scan-in terminal, 102 is an external input terminal that also serves as a normal external input terminal and a data select terminal, and 1
Reference numeral 03 denotes an external input terminal which also serves as a normal clock input terminal and a test clock input terminal, 104 denotes a mode select terminal for switching between a normal operation and a scan operation, 10
5 is an external output terminal, 106 is an AND gate, 107 is an inverter, 108 is a combinational circuit, 109 is a selector for selecting normal external output data and scan-out data,
Reference numeral 110 is a delay element that causes a time difference between the normal clock from the external input terminal 103 and the signal of the test clock signal line 140, 111 and 113 are scan storage elements that operate at the rising edge of the clock, and 112 and 114 are falling edges of the clock. Scan storage element that operates in 1
Reference numeral 21 denotes a signal line for scan-out of the scan storage element 111 and scan-in of the scan storage element 112, 12
2 is a signal line for scan-out of the scan storage element 112 and scan-in of the scan storage element 113;
Is a scan-out signal line of the scan storage element 113 and a scan-in signal line of the scan storage element 114, 124 is a scan-out signal line of the scan storage element 114, 13
0 is an output signal line of the AND gate 106, 131 is a clock input signal line of the scan storage elements 111 and 112, 13
Reference numeral 2 is a clock input signal line of the scan storage elements 113 and 114, 140 is a test clock input signal line of the scan storage element 114, 141 is a test clock input signal line of the scan storage element 113 and a test clock output signal line of the scan storage element 114 , 142 is the scan storage element 1
12 test clock inputs and scan storage elements 11
Reference numeral 3 denotes a test clock output signal line, and 143 denotes a test clock input signal line of the scan storage element 111 and a test clock output signal line of the scan storage element 112.

FIG. 2A shows the scan storage element 11 of FIG.
It is a circuit block diagram which shows the specific example of 1,113. Figure 2 (a)
, 201 is a normal data input terminal, 202 is a scan-in terminal, and 203 is a normal data input terminal 201.
Signal (input data signal) and a signal of the scan-in terminal 202 (scan-in data signal) are input to select data, 204 is a normal clock input terminal, 205 is a test clock input terminal, and 206 is a normal mode. And a mode select terminal for selecting a scan mode, 207 is a scan out terminal, 208 is a normal data output terminal, 209 is a test clock output terminal, and 210
When the signal value of the data select terminal 203 is "0", a normal input data signal is output, and the data select terminal 2
A selector that outputs a scan-in data signal when the signal value of 03 is "1", 211 is a mode select terminal 20
When the signal value of 6 is "0", the normal clock input terminal 204
Signal (normal clock signal) is output, and when the signal value of the mode select terminal 206 is “1”, the signal (test clock signal) of the test clock input terminal 205 is output. The selectors 212 and 213 are inverters (delay elements). ), 214 is a storage element driven by the rise of the clock signal from the selector 211, and 220 is the selector 2
Reference numeral 11 denotes an output signal line and 221 denotes an output signal line of the selector 210.

FIG. 2B shows the scan storage element 11 of FIG.
It is a circuit block diagram which shows the specific example of 2,114. Figure 2 (b)
In FIG. 2A, reference numeral 215 denotes a storage element driven by the fall of the clock signal from the selector 211.
The same reference numerals are attached to the same components. In the scan storage elements 112 and 114, the signal (test clock signal) from the test clock input terminal 205 is transmitted to the inverter 21.
Since the phase is inverted by 2, during scan mode,
The memory element 215 is driven when the signal of the test clock input terminal 205 rises, and when the signal of the test clock input terminal 205 rises, like the scan memory elements 111 and 113 shown in FIG. Drive to perform shift operation. Further, since the signal of the test clock input terminal 205 is inverted by the inverter 212 and then inverted by the inverter 213 again, the phase of the signal of the test clock output terminal 209 is the same as that of the test clock input terminal 2.
It becomes the same as the signal of 05.

FIG. 3 is a time chart for explaining the operation of the semiconductor integrated circuit configured as described above. 3, reference numerals 301 to 304 denote signal waveforms on the signal line 220 inside the scan storage elements 111 to 114, respectively, and 310 to 313, 320 to 323, 330.
Reference numerals 333, 340 to 343 denote scan-out data signals of the scan storage elements 111, 112, 113, 114, respectively. Regarding other reference numerals, the waveforms of signals in the signal lines or the external terminals that match the reference numerals in FIG. 1 are shown.

The operation of the semiconductor integrated circuit will be described below with reference to FIGS. Mode select terminal 104
When the signal value of 1 is "0", the normal mode is set and normal operation is performed. That is, the selector 211 outputs the signal of the normal clock input terminal 204, and the signal value of the data select terminal 203 is always “0” in the normal mode. Therefore, the selector 210 outputs the signal of the normal data input terminal 201. And the scan storage elements 111 to 1
Reference numeral 14 functions as a normal memory element that operates with a normal clock signal, a normal input data signal, and a normal output data signal.

When the signal value of the mode select terminal 104 is "1", the scan mode is set and the selector 211
Outputs a signal from the test clock input terminal 205, and the selector 109 outputs a scan-out signal from the scan storage element 114. As described above, during the scan mode, all the scan storage elements 111 to 114 are driven in the same phase by the signal of the test clock input terminal 205. Therefore, a storage element that operates at the rising edge of the clock during normal operation, a storage element that operates at the falling edge of the clock during normal operation, and a storage element that operates according to clocks with different phases can all be in the same scan chain.

When reading the signal value of the normal data input terminal 201 of the scan storage elements 111 to 114, first, when "0" is input to the external input terminal 102, the selector 210 causes the signal of the normal data input terminal 201 to be input. Select. When the clock signal of the external input terminal 103 is operated in this state, the output signal values of the storage elements 214 and 215 become the same as the signal values of the normal data input terminal 201, and the scan out terminals 2 of the scan storage elements 111 to 114.
The signal values of 07 are 310, 320, 330 and 34, respectively.
It becomes 0. Next, when "1" is input to the external input terminal 102, the selector 210 selects the signal of the scan-in terminal 202, and when the clock signal of the external input terminal 103 is operated in this state, the shift operation is performed on the scan chain. , Scan storage elements 111, 112, 113, 114
Signals are shifted like 311, 321, 331, and 341, and the signal value of the scan-out terminal 207 is that the signal values of the scan storage elements 111, 112, 113, and 114 are serially output from the external output terminal 105. become.

On the other hand, when it is not necessary to read the signal value of the normal data input terminal 201 of the scan storage elements 111 to 114 by only performing scan-in to the scan chain, the external input terminal (data select terminal) 102 is set to "1". When the selector 210 selects the signal from the scan-in terminal 202 and operates the clock signal from the external input terminal (test clock input terminal) 103 in this state, the shift operation is performed on the scan chain and each scan storage The signal values serially in the elements 111, 112, 113, 114 are set.

Next, the operation at the time of mode switching will be described. When switching from the scan mode to the normal mode, before switching to the normal mode, the external input terminal 10 that serves as both a normal external input and an external input during scanning is used.
It is necessary to return the signals 1 to 103 to the normal mode data. Therefore, the signal of the external input terminal 103 must be switched from the test clock signal to the normal clock signal before switching to the normal mode.

In this embodiment, the test clock signal line 1
Since the delay element 110 is provided on the 40, a time difference occurs between the test clock signal and the normal clock signal, and the signal of the external input terminal 103 is switched from the test clock signal to the normal clock signal before switching from the scan mode to the normal mode. However, the test clock signal is delayed by the delay element 11
The signal reaches the scan chain later than the signal from the external input terminal 103 by the delay time of 0. Therefore, by switching to the normal mode after switching the signal of the external input terminal 103 and before changing the test clock signal reaching the scan chain, it is possible to switch to the normal mode in the state where the test clock signal is "1". This makes it possible to prevent data destruction when switching modes.

When a scan storage element is newly inserted in the scan chain, the scan-in terminal 202, scan-out terminal 207, test clock input terminal 205, and test clock output terminal 209 of the newly added scan storage element are connected. Designing the timing and phase of the test clock signal during the scan operation is sufficient by connecting the scan storage elements before and after the insertion and connecting the data select terminal 203 and the mode select terminal 206 to the signal line 130 and the mode select terminal 104, respectively. Scan design is greatly facilitated since it does not need to be performed.

Therefore, according to this embodiment, the timing design at the time of scanning can be facilitated, and even if a circuit is used in combination with a storage element for a multiphase clock, a rising clock operation, and a falling clock operation, it can be arbitrarily selected. Since the storage elements can be used as one scan chain, design restrictions when using scan can be reduced.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIGS. 2, 4 and 5. Figure 4
FIG. 6 is a circuit configuration diagram of a semiconductor integrated circuit of a second embodiment of the present invention. In FIG. 4, 401 is an external input terminal that also serves as a normal external input terminal and a data input terminal of a storage element 403 that controls a test clock signal, and 402 is a normal external input terminal and a clock input terminal of the storage element 403. An external input terminal is also used, 403 is a storage element that operates with a rising clock, 404 is an OR gate, and 410 is an output signal line of the storage element 403. The parts corresponding to those in FIG. 1 are designated by the same reference numerals.

FIG. 5 is a time chart for explaining the operation of this semiconductor integrated circuit. In FIG. 5, 501
˜504 show the waveforms of signals in the signal lines 220 (FIG. 2) inside the scan storage elements 111˜114, respectively, 310˜313, 320˜323, 330˜33.
Reference numerals 3, 340 to 343 denote scan storage elements 11 respectively.
The scan-out data signals of 1,112,113,114 are shown. Regarding other symbols, the waveforms of the signals in the signal lines or the external terminals that match the symbols in FIG. 4 are shown.

Hereinafter, based on FIGS. 2, 4 and 5,
The operation of this semiconductor integrated circuit will be described. The operation in the normal mode is similar to that of the first embodiment. The operation in the scan mode will be described. First, the external input terminals 401, 4
The signal value of 02 is set to “0” when the scan mode is entered.
Next, when the signal value of the external input terminal 402 is set to "1",
The signal value of the output signal line 410 of the memory element 403 becomes “0”. Therefore, since the signal value of the external input terminal 103 is output as it is from the output of the OR gate 404, the signal value of the test clock signal line 140 is controlled by the signal value of the external input terminal 103. The scan operation of the scan chain for the test clock signal is the same as in the first embodiment.

Next, the operation at the time of mode switching will be described. When switching from the scan mode to the normal mode, before switching to the normal mode, the external input terminal 10 that serves as both a normal external input and an external input during scanning is used.
It is necessary to return the signals 1 to 103 to the normal mode data. Therefore, the signal of the external input terminal 103 must be switched from the test clock signal to the normal clock signal before switching to the normal mode.

In this embodiment, the signal value of the external input terminal 401 is set to "1" before the signal of the external input terminal 103 is switched from the test clock signal to the normal clock signal.
By setting the signal value of the external input terminal 402 to "0" and then setting the signal value of the external input terminal 402 to "1", the signal value of the output signal line 410 of the memory element 403 becomes "1", and the OR Test clock signal line 1 by gate 404
The signal value of 40 is held at "1". After that, even if the signal values of the external input terminals 103, 401, and 402 are returned to the signal values of the normal mode, the signal value of the test clock signal line 140 is still held at “1”, so that the test clock signal becomes “1”. In this state, the scan mode can be switched to the normal mode, and the data destruction at the time of mode switching can be prevented.

Therefore, according to this embodiment, the timing design at the time of scanning is facilitated, and even if the circuit is used in combination with the storage elements for the multi-phase clock, the rising clock operation, and the falling clock operation, the test is performed. Since only one external input terminal can be added to make any storage element into one scan chain, it is possible to reduce design restrictions when using scan.

[0034]

According to the first aspect of the present invention, a delay element is built in a plurality of scan storage elements between a test clock input terminal and a test clock output terminal, so that a scan chain can be designed. By connecting the scan terminal of each scan storage element to the scan terminal of the corresponding scan storage element, it is possible to perform a scan design in which the timing of the scan operation is adjusted,
It makes the scan design much easier and is very useful for automating the scan design.

According to the second aspect of the invention, the input of the normal clock and the test clock is shared by one external input terminal, and the delay element is provided on the internal test clock signal line. A time difference occurs between the scan modes, a malfunction (data destruction) at the time of mode switching from the scan mode to the normal mode can be prevented, and any storage element that operates with clocks of different phases can be used as one scan chain. it can. Therefore, the scan design becomes very easy, which is very useful for automating the scan design.

According to the third aspect of the present invention, one external input terminal serves as both the input of the normal clock and the input of the test clock, and when the scan operation is switched to the normal operation, the signal value of the internal test clock signal line is changed. By providing the holding means, it is possible to prevent a malfunction (data destruction) at the time of switching the mode from the scan mode to the normal mode, and use one storage chain that operates with arbitrary storage elements that operate with clocks of different phases. be able to.
Therefore, the scan design becomes very easy, which is very useful for automating the scan design.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a specific example of a scan storage element in FIGS. 1 and 4.

FIG. 3 is a time chart for explaining the operation of the semiconductor integrated circuit of the first embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of the semiconductor integrated circuit of the second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a conventional semiconductor integrated circuit.

FIG. 7 is a circuit configuration diagram showing a specific example of the scan storage element in FIG.

FIG. 8 is a time chart for explaining the operation of the conventional semiconductor integrated circuit.

[Explanation of symbols]

104 mode select terminal 103 external input terminal (also serves as a normal clock input terminal and a test clock input terminal) 110 delay element 111 to 114 scan storage element 140 test clock signal line 204 normal clock input terminal 205 test clock input terminal 209 test clock output Terminals 212 and 213 Inverter (delay element) 403 Storage element (holding means) 404 OR gate (holding means)

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[Procedure amendment]

[Submission date] June 19, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 7]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 8]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/66 Z 7013-4M

Claims (3)

[Claims] 1. A semiconductor integrated circuit, comprising: a plurality of scan storage elements; and a mode select terminal for switching between a normal operation and a scan operation, wherein the plurality of scan storage elements are for normal operation. A semiconductor integrated circuit having a clock input terminal, a test clock input terminal and a test clock output terminal for performing a scan operation, and a delay element built in between the test clock input terminal and the test clock output terminal. circuit. 2. A semiconductor integrated circuit comprising a plurality of scan storage elements and a mode select terminal for switching between a normal operation and a scan operation, wherein one external input terminal serves as both a normal clock and a test clock input. A semiconductor integrated circuit is characterized in that a delay element is provided on the internal test clock signal line. 3. A semiconductor integrated circuit comprising a plurality of scan storage elements and a mode select terminal for switching between a normal operation and a scan operation, wherein one external input terminal also serves as an input of a normal clock and a test clock. A semiconductor integrated circuit is provided with means for holding the signal value of the internal test clock signal line when switching from the scan operation to the normal operation.