JPH056236A - Timer for information processor - Google Patents
Timer for information processorInfo
- Publication number
- JPH056236A JPH056236A JP3157321A JP15732191A JPH056236A JP H056236 A JPH056236 A JP H056236A JP 3157321 A JP3157321 A JP 3157321A JP 15732191 A JP15732191 A JP 15732191A JP H056236 A JPH056236 A JP H056236A
- Authority
- JP
- Japan
- Prior art keywords
- timer
- firmware
- holding means
- word
- interrupt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Landscapes
- Executing Machine-Instructions (AREA)
- Microcomputers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は情報処理装置におけるタ
イマに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer in an information processing device.
【０００２】[0002]
【従来の技術】従来、この種のタイマは、装置内に何種
類か存在し、それらすべてをレジスタで持ち、周期に応
じたカウントアップまたはカウントダウン回路をすべて
ハードウェアで構成していた。2. Description of the Related Art Conventionally, there are several kinds of timers of this type in a device, all of them are held by registers, and a count-up or count-down circuit according to a cycle is entirely constituted by hardware.
【０００３】[0003]
【発明が解決しようとする課題】この従来の情報処理装
置におけるタイマでは、タイマ個々にカウントアップま
たはカウトダウン機能が必要となるため、回路構成が複
雑のうえに、ハードウェア量が増加してしまう問題点が
ある。In the conventional timer of the information processing apparatus, each timer requires a count-up or count-down function, so that the circuit configuration is complicated and the amount of hardware increases. There is a point.
【０００４】[0004]
【課題を解決するための手段】本発明の情報処理装置に
おけるタイマは、ファームウェアが自由に読み書き可能
な保持手段と、周期Ｔのタイマを実現するために、装置
内にある既存の別のタイマからの一定周期ｔ（Ｔ≧ｔ）
の信号によってファームウェアに割込む手段とを有し、
割込んだ先のファームウェアによって前記保持手段の１
語を計数手段として使用し、前記割込毎にファームウェ
アで計数し、Ｔ／ｔ回に達したら、前記保持手段の別の
１語に設定した周期Ｔのタイマのタイマ値を更新する制
御をファームウェアで行うことを特徴とする。A timer in an information processing apparatus according to the present invention includes a holding unit that can be freely read and written by firmware and another existing timer in the apparatus in order to realize a timer having a period T. Constant period t (T ≧ t)
And a means to interrupt the firmware by the signal of
Depending on the firmware of the interrupt destination, one of the holding means
The word is used as the counting means, the firmware counts each interrupt, and when it reaches T / t times, the firmware updates the timer value of the timer of the cycle T set in another word of the holding means. It is characterized by performing in.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００６】図１は本発明の一実施例のタイマにおける
タイマ更新のファームウェア処理長れ図である。本例で
実現するタイマの使用は、周期１０秒でカウントアップ
するタイマＡである。FIG. 1 is a firmware processing length diagram for updating a timer in a timer according to an embodiment of the present invention. The use of the timer realized in this example is the timer A that counts up at a cycle of 10 seconds.
【０００７】この装置内には他にハードウェア制御で動
作するタイマＢが存在し、周期１秒毎にファームウェア
に割込信号を発生する。タイマＡはファームウェアが自
由に読み書きできるメモリの１語を使用し、また、１秒
毎の割込を１０回カウントするためのカウンタもこのメ
モリの１語を使用する。In this device, there is also a timer B which operates under hardware control, and an interrupt signal is generated in the firmware every cycle of 1 second. The timer A uses one word of the memory that can be freely read and written by the firmware, and also uses one word of this memory as a counter for counting 10 interrupts per second.
【０００８】１秒毎に割込まれたファームウェアの処理
を図によって説明する。The processing of the firmware interrupted every one second will be described with reference to the drawings.
【０００９】まずカウンタを１増加させる。そしてカウ
ント値をチェックし、９以下であればカウンタＡは更新
せずに終了する。カウント値が１０であるならば、１０
秒が経過したことを示すのでタイマＡの値を１増加し、
カウント値を０にリセットして終了する。First, the counter is incremented by 1. Then, the count value is checked, and if it is 9 or less, the counter A ends without updating. If the count value is 10, then 10
Since the second has passed, the value of timer A is incremented by 1,
The count value is reset to 0 to finish.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、装置内の
タイマのいくつかをファームゥェアで実現したので、ハ
ードウェア量が削減できる効果を有する。１秒に１回数
ステップのファームウェア処理が追加される程度では性
能にはほとんど影響はない。As described above, according to the present invention, some of the timers in the apparatus are realized by firmware, so that the amount of hardware can be reduced. The performance is hardly affected by the addition of the firmware processing of one step per second.
【図１】本発明の一実施例のファームウェア流れ図であ
る。FIG. 1 is a firmware flow chart of one embodiment of the present invention.
Claims (1)
保持手段と、周期Ｔのタイマを実現するために、装置内
にある既存の別のタイマからの一定周期ｔ（Ｔ≧ｔ）の
信号によってファームウェアに割込む手段とを有し、割
込んだ先のファームウェアによって前記保持手段の１語
を計数手段として使用し、前記割込毎にファームウェア
で計数し、Ｔ／ｔ回に達したら、前記保持手段の別の１
語に設定した周期Ｔのタイマのタイマ値を更新する制御
をファームウェアで行うことを特徴とする情報処理装置
におけるタイマ。Claim: What is claimed is: 1. In order to realize a holding unit that can be freely read and written by firmware and a timer having a period T, a predetermined period t (T ≧ t) from another existing timer in the device. ) Signal to interrupt the firmware, and the interrupted firmware uses one word of the holding means as counting means, and the firmware counts each interrupt and reaches T / t times. Then, another one of the holding means
A timer in an information processing apparatus, wherein firmware controls to update a timer value of a timer having a period T set in a word.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3157321A JPH056236A (en) | 1991-06-28 | 1991-06-28 | Timer for information processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3157321A JPH056236A (en) | 1991-06-28 | 1991-06-28 | Timer for information processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH056236A true JPH056236A (en) | 1993-01-14 |
Family
ID=15647142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3157321A Pending JPH056236A (en) | 1991-06-28 | 1991-06-28 | Timer for information processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056236A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0325519A (en) * | 1989-06-23 | 1991-02-04 | Yagi Antenna Co Ltd | Timer control method |
-
1991
- 1991-06-28 JP JP3157321A patent/JPH056236A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0325519A (en) * | 1989-06-23 | 1991-02-04 | Yagi Antenna Co Ltd | Timer control method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19971014 |